WO2011111137A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2011111137A1
WO2011111137A1 PCT/JP2010/006785 JP2010006785W WO2011111137A1 WO 2011111137 A1 WO2011111137 A1 WO 2011111137A1 JP 2010006785 W JP2010006785 W JP 2010006785W WO 2011111137 A1 WO2011111137 A1 WO 2011111137A1
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WO
WIPO (PCT)
Prior art keywords
wire
semiconductor device
conductor
solder
semiconductor element
Prior art date
Application number
PCT/JP2010/006785
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English (en)
French (fr)
Japanese (ja)
Inventor
靖 池田
知丈 東平
Original Assignee
株式会社日立製作所
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Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to DE112010005383.9T priority Critical patent/DE112010005383B4/de
Publication of WO2011111137A1 publication Critical patent/WO2011111137A1/ja

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Definitions

  • the present invention relates to a power semiconductor device having an element upper surface electrode connection portion with low electrical resistance and high connection reliability.
  • wire bonding 1 using a thick Al wire having a diameter of 300 to 400 ⁇ m as shown in FIG. 1 is generally used as a wiring method for the upper electrode of the power semiconductor element.
  • the Al wire bonding portion, the power semiconductor element, and the like generate heat due to Joule heat.
  • a temperature change occurs due to this heat generation, a stress is generated in the Al wire bonding portion due to a difference in thermal expansion coefficient between the Al wire and the element. Therefore, when energization is repeatedly turned on and off, the vicinity of the bonding interface of the Al wire bonding portion undergoes fatigue failure due to thermal stress.
  • the capacity of power modules has been increased, and the current to be supplied to each power semiconductor element has increased, and it has been a problem to ensure the connection reliability of the wire bonding portion against thermal stress.
  • One way to reduce the thermal stress generated in the Al wire bonding part is to increase the number of Al wires. By reducing the current that flows per Al wire, the amount of heat generated in the wire bonding portion can be reduced and the connection reliability can be improved.
  • the number of Al wires that can be bonded is limited by the area of the power semiconductor element, it is difficult to greatly reduce the heat generation. Further, when the size of the power semiconductor element is increased in order to increase the number, the power module is increased in size. Therefore, there is a need for a low electrical resistance wiring method that replaces Al wire bonding.
  • Patent Document 1 a wide Al ribbon is ultrasonically bonded instead of an Al wire. Since the size of the Al ribbon is larger than that of the Al wire, the size of the tool for applying ultrasonic waves necessary for bonding and the ultrasonic energy during bonding increase. For this reason, there is a risk of damaging the power semiconductor element during bonding, and there is a limit to the size of the Al ribbon that can be bonded. There is also a choice to use a Cu ribbon with a low electrical resistance, but Cu has a higher ultrasonic energy during bonding than Al, so the possibility of further damaging the element becomes higher.
  • the Cu member is joined to the element upper surface electrode with solder as shown in FIG.
  • the electrical resistivity of Cu is about 1.7 ⁇ 10 -8 ⁇ ⁇ m (20 ° C) to 2.9 ⁇ 10 -8 ⁇ ⁇ m (200 ° C)
  • the electrical resistivity of Al is about 2.7 ⁇ 10 -8 ⁇ ⁇ m ( Since it is lower than 20 ° C to 4.8 ⁇ 10 -8 ⁇ ⁇ m (200 ° C), the electrical resistance can be greatly reduced.
  • the present invention has been made in order to solve the above-described problems, and realizes a wiring connection in which a large current can be passed by lowering an electrical resistance of an element upper surface junction, and a semiconductor device having a high connection reliability.
  • the purpose is to provide.
  • the conductor Is a knitted wire conductor in which a plurality of conductive wires are knitted.
  • the present invention it is possible to obtain a semiconductor device in which the electrical resistance of the upper surface wiring of the knitting element is suppressed, the distortion of the solder is suppressed, and connection reliability can be ensured even when a large current is applied. .
  • FIG. 3 is a cross-sectional view of the power semiconductor module according to the present embodiment
  • FIG. 4 is a plan view thereof.
  • a power semiconductor element 6 is connected to an electrode (not shown) provided on the substrate 3 via a conductive bonding material (solder) 2.
  • a mesh wire conductor 8 is connected on the semiconductor element 6 via a conductive bonding material (solder) 9.
  • the mesh wire conductor 8 is connected to another electrode (not shown) on the substrate 9 via a conductive bonding member (solder) 9.
  • the length in which the knitted wire conductor is connected by the joining member 9 is 1/3 or more of the size of the semiconductor element 6 in the same direction.
  • a woven wire conductor 8 is connected to the upper surface electrode of the semiconductor element 6 by a conductive bonding material 9.
  • a conductive bonding material 9 As a result, even when a material harder than Al is used, it is possible to bend the knitting wire by adjusting the diameter of a single wire constituting the knitting wire, which occurs at the upper surface connection portion of the semiconductor element 6. Stress to be reduced. Further, by forming the knitted wire, the wires can be laminated via the conductive bonding material as shown in FIG. 5, so that the electric resistance is lowered and the current can be increased.
  • the braided wire conductor is made of Cu or a wire made of a Cu alloy having an electrical resistivity of less than 2.7 ⁇ 10 ⁇ 8 ⁇ ⁇ m.
  • the electrical resistance can be reduced as compared with Al wire bonding.
  • the higher the Cu content the smaller the electrical resistance. Therefore, the Cu content is preferably 95% or more.
  • the rigidity of Cu is about 0.44 ⁇ 10 11 Pa, which is about 1.7 times the rigidity of Al of 0.26 ⁇ 10 11 Pa.
  • the diameter of Cu and Cu alloy wire is desirably 0.2 mm or less. Further, when the diameter is less than 0.01 mm, there is a possibility that the Cu wire may be melted by reacting with the solder when connecting to the conductive bonding material using the solder.
  • FIG. 7 shows a deterioration state of the connection part due to thermal shock when a Cu plate is used as a conductor as in Patent Documents 2 and 3. Cracks develop from the periphery of the conductive bonding material and deteriorate.
  • FIG. 8 shows a crack progress situation due to thermal shock when the braided wire conductors are connected by solder.
  • An object of the present invention is to provide a semiconductor device in which a woven wire conductor is made of Cu or a wire made of a Cu alloy having an electrical resistivity of less than 2.7 ⁇ 10 ⁇ 8 ⁇ ⁇ m and a wire made of a low thermal expansion coefficient material.
  • the knitted wire conductor As an advantage of the knitted wire conductor, a plurality of materials can be combined by weaving as shown in FIG.
  • the coefficient of thermal expansion of Cu is about 17ppm / K, and the coefficient of thermal expansion of semiconductor elements is 3ppm / K.
  • the thermal expansion coefficient as a conductor can be made smaller than that of a conductor made of a single Cu or Cu alloy wire by braiding a low thermal expansion coefficient wire together with a Cu or Cu alloy wire as necessary. It is possible to reduce the thermal stress generated in the conductor connecting portion.
  • Invar, Mo, and W are suitable as the low thermal expansion material. Any of these materials can be processed into a desired wire diameter by drawing or the like. Invar has a coefficient of thermal expansion of about 4ppm / K, Mo is 5ppm / K, and W is 4.5ppm / K. By combining it with Cu or Cu alloy wire, the coefficient of thermal expansion of the woven wire conductor is reduced. be able to.
  • At least one of Ni, Ni-P, and Ni-B plating may be formed on the surface of Cu or a Cu alloy having an electrical resistivity of less than 2.7 ⁇ 10 ⁇ 8 ⁇ ⁇ m.
  • Sn-based lead-free solder gets wet with Cu and Cu alloy, Cu and Sn react to form a Cu-Sn compound at the connection interface.
  • the Cu-Sn compound is formed thick, a portion where the distance between Cu lines is narrow may be connected by the compound. In that case, the stress buffering ability as a knitted wire is reduced.
  • Ni-based plating can be applied to the surface of Cu and Cu alloy wires to suppress compound growth at the connection interface and maintain stress buffering ability.
  • the Ni-based plating thickness is desirably 1 to 5 ⁇ m.
  • the Ni-based plating thickness is less than 1 ⁇ m, the Ni-based plating may disappear due to the interfacial reaction, and the plating effect may not be obtained. If the Ni plating thickness is 5 ⁇ m or more, the uniformity of the plating thickness may be impaired, and Ni may be harder than Cu, which may reduce the stress buffering ability.
  • the conductive bonding material that connects the knitted wire conductor is Sn-based lead-free solder.
  • solder Since Sn-based lead-free solder is easily wettable and reactive with Cu or Cu alloys with an electrical resistivity of less than 2.7 ⁇ 10 -8 ⁇ ⁇ m, conductors can be connected well. Moreover, since the solder fills the gaps in the braided wire by capillary action, the connection with low electrical resistance is achieved.
  • An object of the present invention is to provide a semiconductor device in which the conductive bonding material for connecting the braided wire conductor is pure Sn, Sn-Cu eutectic solder.
  • Example 1 to 11 In order to demonstrate the effects of the present invention, the following samples (Examples 1 to 11) were prepared. As shown in FIG. 3, a 200 ⁇ m thick Sn-7Cu (mass%) solder foil 2 is placed on a substrate 3 and a power semiconductor element 6 of 10 mm ⁇ 10 mm. Is laminated thereon to form an H 2 reducing atmosphere. The connection was made at 300 ° C for 5 min.
  • the solder foil 9 having a thickness of 100 ⁇ m used in each of the embodiments shown in FIG.
  • the on-resistance of the semiconductor element after assembling this semiconductor device was measured.
  • a temperature cycle test of -40 ° C. (10 min.) To 125 ° C. (10 min.) was conducted 1000 cycles, and the on-resistance variation after the temperature cycle test was measured.
  • the on-resistance at the time of assembly the case where the on-resistance was low compared with the semiconductor device using the Al ribbon bonding which is Comparative Example 2 was marked as ⁇ , and the case where the on-resistance was equal or higher.
  • the on-resistance after assembly was smaller than that of the semiconductor device using the Al ribbon bonding of Comparative Example 2.
  • the on-resistances of Examples 1 to 9 were about 0.8 times that of the Al ribbon bonding semiconductor device, and Examples 10 and 11 were about 0.9 times.
  • the increase in on-resistance was 1.2 times or less of the initial value even after 1000 cycles.
  • the values of Examples 1 to 9 were about 1.1 times the initial value, and Examples 10 and 11 showed almost no change from the initial value.
  • the element upper surface wiring connection having a low electrical resistance and high connection reliability is possible.
  • the entire structure is described as a process of separately connecting the knitted wire conductor and the semiconductor element, and the connection between the semiconductor element and the substrate.
  • the knitted wire substrate, the solder foil, the semiconductor element, the solder foil, and the substrate are laminated. Later, you may connect in a single process.
  • Sn-7Cu (mass%) solder foil having a thickness of 200 [mu] m, performed thereon by laminating a 10 mm ⁇ 10 mm.
  • Comparative Example 1 12 Al wires having a diameter of 0.4 mm are bonded between the electrodes on the semiconductor element and the substrate, and in Comparative Example 2, the electrodes between the semiconductor element and the electrodes on the substrate are 0.1 mm thick and 3 mm wide. Two Al wires were bonded. After that, a case was attached to the substrate 3, and a gel was injected around the connection portion and cured to produce a semiconductor device.
  • the on-resistance of the semiconductor element after this semiconductor device assembly was measured, and the on-resistance after 1000 cycles of a temperature cycle test of ⁇ 40 ° C. (10 min.) To 125 ° C. (10 min.) was measured.
  • the on-resistance at the time of assembly the case where the on-resistance was low compared with the semiconductor device using the Al ribbon bonding which is Comparative Example 2 was marked as ⁇ , and the case where the on-resistance was equal or higher.
  • Comparative Example 3 On a substrate, placing an Sn-7Cu (mass%) solder foil having a thickness of 200 [mu] m, performed thereon by laminating a 10 mm ⁇ 10 mm. Of the power semiconductor element, in H 2 reducing atmosphere, a connection 300 ° C. 5min. In It was.
  • the on-resistance of the semiconductor element after this semiconductor device assembly was measured, and the on-resistance after 1000 cycles of a temperature cycle test of ⁇ 40 ° C. (10 min.) To 125 ° C. (10 min.) was measured.
  • the on-resistance at the time of assembly the case where the on-resistance was low compared with the semiconductor device using the Al ribbon bonding which is Comparative Example 2 was marked as ⁇ , and the case where the on-resistance was equal or higher.
  • the on-resistance after assembly is about 0.6 times that of the semiconductor device using Al ribbon bonding of Comparative Example 2, which is the lowest value among all the semiconductor devices including Examples 1 to 11. It became.
  • the on-resistance increased to about 1.5 times the initial value, which was the lowest reliability among all the semiconductor devices including Examples 1 to 11.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
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JP2014103183A (ja) 2012-11-19 2014-06-05 Mitsubishi Electric Corp 電子回路、その製造方法、および電子部品
JP2015216290A (ja) * 2014-05-13 2015-12-03 カルソニックカンセイ株式会社 ビームリード、半導体装置、および、半導体装置の製造方法
DE102015103779A1 (de) * 2015-03-16 2016-09-22 Pac Tech-Packaging Technologies Gmbh Chipanordnung und Verfahren zur Ausbildung einer Kontaktverbindung
DE102016108656A1 (de) * 2016-05-11 2017-11-16 Danfoss Silicon Power Gmbh Leistungselektronische Baugruppe mit vibrationsfreier Kontaktierung
JP2017157847A (ja) * 2017-04-21 2017-09-07 三菱電機株式会社 電子回路
DE102019215438A1 (de) * 2019-10-09 2020-08-20 Vitesco Technologies Germany Gmbh Bondbändchen, Elektronikanordnung mit einem Bondbändchen, Verfahren zum Herstellen eines Bondbändchens

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JP2003037130A (ja) * 2001-07-24 2003-02-07 Sony Corp ボンディングワイヤ、半導体装置及びその製造方法
JP2004319740A (ja) * 2003-04-16 2004-11-11 Fuji Electric Holdings Co Ltd パワー半導体装置およびその製造方法
WO2007125939A1 (ja) * 2006-04-27 2007-11-08 Neomax Materials Co., Ltd. 配線接続用クラッド材及びそのクラッド材から加工された配線接続部材

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JP4640345B2 (ja) 2007-01-25 2011-03-02 三菱電機株式会社 電力用半導体装置
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JP2004319740A (ja) * 2003-04-16 2004-11-11 Fuji Electric Holdings Co Ltd パワー半導体装置およびその製造方法
WO2007125939A1 (ja) * 2006-04-27 2007-11-08 Neomax Materials Co., Ltd. 配線接続用クラッド材及びそのクラッド材から加工された配線接続部材

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