WO2011102440A1 - Dispositif de stockage, substrat, contenant de liquide et système - Google Patents

Dispositif de stockage, substrat, contenant de liquide et système Download PDF

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Publication number
WO2011102440A1
WO2011102440A1 PCT/JP2011/053444 JP2011053444W WO2011102440A1 WO 2011102440 A1 WO2011102440 A1 WO 2011102440A1 JP 2011053444 W JP2011053444 W JP 2011053444W WO 2011102440 A1 WO2011102440 A1 WO 2011102440A1
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WO
WIPO (PCT)
Prior art keywords
voltage level
storage device
reset
clock
terminal
Prior art date
Application number
PCT/JP2011/053444
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English (en)
Japanese (ja)
Inventor
潤 佐藤
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セイコーエプソン株式会社
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Publication date
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Publication of WO2011102440A1 publication Critical patent/WO2011102440A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17526—Electrical contacts to the cartridge
    • B41J2/1753—Details of contacts on the cartridge, e.g. protection of contacts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17553—Outer structure

Definitions

  • the present invention relates to a storage device, a substrate, a liquid container, a system, and the like.
  • Patent Document 1 discloses a technique for detecting the presence / absence of an ink cartridge by providing a detection terminal on a printer and an ink cartridge and detecting the presence / absence of electrical continuity. .
  • this method has a problem that the number of terminals increases.
  • Patent Document 2 discloses a technique in which a terminal for detecting the remaining amount of ink is also used for detecting whether or not an ink cartridge is mounted.
  • this method has a problem that the number of terminals cannot be reduced even when the detection of the remaining amount of ink is changed to another method.
  • a storage device a substrate, a liquid container, a system, and the like that can efficiently detect connection without increasing the number of terminals.
  • One aspect of the present invention includes a storage unit, a storage control unit that controls access to the storage unit, a control unit that performs communication processing with a host device, a data terminal, a reset terminal, and a clock terminal,
  • the control unit operates when the voltage level of the reset terminal changes from a voltage level indicating a reset state to a voltage level indicating a reset release state during a period in which the voltage level of the clock terminal is the first voltage level.
  • This relates to a storage device that determines that the operation mode is the connection detection mode when the level is changed.
  • control unit can determine whether the operation mode is the normal communication mode or the connection detection mode based on the voltage levels of the clock terminal and the reset terminal. Therefore, the number of terminals can be reduced. As a result, it is possible to efficiently detect the connection of the storage device.
  • the host device is electrically connected to first to nth storage devices (n is an integer of 2 or more) including the storage device via a bus, and the reset A reset signal output from the host device via the bus may be input to the terminal.
  • the storage device determines whether the operation mode is the normal communication mode or the connection detection mode based on the reset signal, and if it is the connection detection mode, responds to the host device.
  • a signal can be output. As a result, it is possible to efficiently detect the connection of the storage device.
  • the reset terminal may include a reset corresponding to the storage device from among a first reset signal to an nth (n is an integer of 2 or more) reset signal output from the host device.
  • a signal may be input.
  • the storage device determines whether the operation mode is the normal communication mode or the connection detection mode based on the reset signal input to its own reset terminal. Can output a response signal to the host device. As a result, it is possible to efficiently detect the connection of the storage device.
  • the control unit determines that the operation mode is the connection detection mode
  • the voltage level of the clock terminal is changed from the second voltage level to the first voltage level.
  • a response signal for notifying that the storage device is connected may be output to the host device via the data terminal in accordance with the clock after the change.
  • control unit can output a response signal for notifying that the storage device is connected to the host device via the data terminal. Can be eliminated and the number of terminals can be reduced. As a result, it is possible to efficiently detect the connection of the storage device.
  • a clock including first to n-th (n is an integer of 2 or more) clock cycles is input to the clock terminal, and the control unit has the operation mode set to the operation mode.
  • the first clock to the nth clock cycle after the voltage level of the clock terminal changes from the second voltage level to the first voltage level.
  • the data may be output to the host device via the data terminal.
  • the storage device can output a response signal in the clock cycle corresponding to its own ID information, the detection time can be shortened. As a result, it is possible to efficiently detect the connection of the storage device.
  • the control unit determines that the operation mode is the normal communication mode
  • the voltage level of the clock terminal is changed from the first voltage level to the second voltage level.
  • the information output from the host device may be acquired via the data terminal according to the clock after the change.
  • control unit can acquire information output from the host device in the normal communication mode, for example, a process of receiving write data output from the host device and writing to the storage unit And so on.
  • control unit acquires a command as the information output from the host device, analyzes the acquired command, and receives data from the host device based on an analysis result.
  • a process of transmitting data to the host device may be performed.
  • control unit receives the write data output from the host device based on the command from the host device and writes the data to the storage unit, or from the storage unit. A process of reading data and transmitting it to the host device can be performed.
  • control unit determines that the voltage level of the reset terminal indicates the reset state from the voltage level indicating the reset release state after determining that the operation mode is the connection detection mode.
  • a process for ending the connection detection mode may be performed.
  • Another aspect of the present invention relates to a substrate including the storage device described above.
  • Another aspect of the present invention relates to a liquid container including any of the storage devices described above.
  • Another aspect of the present invention relates to a system including any of the storage devices described above and the host device.
  • the host device since the host device can efficiently detect whether or not the storage device is properly connected, the reliability of the system can be improved.
  • FIG. 1 is a first configuration example of a system.
  • FIG. 2 shows a second configuration example of the system.
  • FIG. 3 shows a basic configuration example of the storage device.
  • FIG. 4 is an example of a timing chart of the normal communication mode of the storage device.
  • FIGS. 5A and 5B are first examples of timing charts of the connection detection mode of the storage device.
  • 6A and 6B are a second example of a timing chart of the connection detection mode of the storage device.
  • 7A and 7B are a third example of a timing chart of the connection detection mode of the storage device.
  • 8A and 8B are diagrams illustrating an operation and a configuration example of a mode determination unit.
  • FIG. 9 shows a basic configuration example of the response unit.
  • FIG. 10 shows an example of the correspondence between ID information and clock cycles.
  • FIG. 11 shows another example of the correspondence between ID information and clock cycles.
  • FIG. 12 shows a detailed configuration example of the liquid container.
  • 13A and 13B show detailed configuration examples of the circuit board.
  • FIGS. 14A to 14C are detailed configuration examples of a four-color integrated liquid container and a substrate.
  • FIG. 15 shows a basic configuration example of the host device.
  • FIG. 16 is a diagram illustrating power supply periods in a normal communication mode and a connection detection mode.
  • FIG. 1 shows a first configuration example of a system according to this embodiment.
  • the first configuration example of the system according to the present embodiment includes a first storage device 100-1 to an nth storage device 100-n (n is an integer of 2 or more), and n substrates 200 on which the storage devices are mounted. -1 to 200-n, n liquid containers 300-1 to 300-n including a substrate, and a host device 400 are included.
  • the system of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.
  • the first storage device 100-1 to the nth storage device 100-n each include a reset terminal XRST, a clock terminal SCK, a data terminal SDA, a first power supply terminal VSS, and a second power supply terminal VDD.
  • the storage devices of the first to nth storage devices 100-1 to 100-n and the host device 400 are electrically connected via a bus as shown in FIG.
  • This bus includes a reset signal line, a clock signal line, and a data signal line, and communication between each of the storage devices 100-1 to 100-n and the host device 400 is performed via this bus.
  • the bus may also include first and second power lines for supplying first and second power to each storage device.
  • Each storage device has a normal communication mode (normal operation mode) and a connection detection mode as operation modes.
  • the normal communication mode is a mode in which data in the storage unit is transmitted to the host device or data in the storage unit is updated with data received from the host device.
  • the connection detection mode is an operation mode of the storage device when the host device detects whether each storage device is connected to the host device.
  • each storage device sends a response signal for notifying that the storage device is connected, via the data terminal SDA, corresponding to the clock cycle of the clock supplied from the host device 400. Output to the host device 400.
  • the clock cycle is not a physical cycle of a clock signal supplied from the host device 400 but a logical cycle for controlling communication processing between the host device 400 and the storage device 100.
  • one clock cycle may be one physical cycle of the clock signal, or one clock cycle may be two physical cycles of the clock signal.
  • the host device 400 includes first host side terminals to kth (k is an integer of 2 or more) host side terminals. Specifically, for example, a host side reset terminal HRST, a host side clock terminal HCK, a host side data terminal HDA, a first host side power supply terminal HVSS, and a second host side power supply terminal HVDD are included.
  • the host device 400 is, for example, a printer main body, and as will be described later, whether or not each storage device is connected by response signals from the storage devices 100-1 to 100-n, that is, the liquid containers 300-1 to 300-n. It can be determined whether or not 300-n is attached.
  • FIG. 2 shows a second configuration example of the system according to the present embodiment.
  • the second configuration example is different from the first configuration example described above in that the reset signal line is not a bus configuration but a reset signal line is individually provided for each storage device.
  • the host device 400 includes first to fourth host-side reset terminals HRST1 to HRST4 (first to nth (n is an integer of 2 or more) in a broad sense). 1st to 4th reset signals (first to nth reset signals in a broad sense) are output. The first to fourth reset signals are input to reset terminals XRST1 to XRST4 of the first to fourth storage devices 100-1 to 100-4 (first to nth storage devices in a broad sense), respectively. . That is, a reset signal corresponding to the storage device among the first to n-th reset signals output from the host device 400 is input to the reset terminal.
  • each storage device 100 sends a response signal for notifying that the storage device is connected to the host device 400 via the data terminal SDA. Can be output. By doing so, a terminal for detecting the presence or absence of the liquid container 300 becomes unnecessary, and the number of terminals can be reduced.
  • FIG. 3 shows a basic configuration example of the storage device 100 of the present embodiment.
  • the storage device 100 of this embodiment includes a control unit 110, a storage control unit 120, a storage unit 130, a data terminal SDA, a reset terminal XRST, and a clock terminal SCK.
  • the storage device 100 of the present embodiment is not limited to the configuration of FIG. 3, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.
  • the storage unit 130 stores ID information written during manufacturing, manufacturing information, and information written from the host device 400.
  • the storage unit 130 stores manufacturing date information, ink color information, and the like as manufacturing information, and stores ink remaining amount information as information written from the host device 400.
  • the storage unit 130 is configured by a non-volatile memory such as FERAM (ferroelectric memory) or flash memory, for example.
  • ID information for identifying the storage device 100 in the storage unit 130 is not an essential configuration requirement.
  • ID information can be stored using a fuse element, or ID information can be output by a logic circuit.
  • the storage control unit 120 controls access to the storage unit 130 in the normal communication mode (normal operation mode) and the connection detection mode.
  • the control unit 110 includes a communication unit 140, a mode determination unit 150, and a response unit 160.
  • the communication unit 140 communicates with the host device 400.
  • the mode determination unit 150 determines whether the operation mode is the normal communication mode (normal operation mode) or the connection detection mode. When it is determined that the communication mode is the normal communication mode, the control signal SCOM for the storage control unit 120 is set to the active level, and when it is determined that the connection detection mode is selected, the control signal SDET for the response unit 160 is set to the active level.
  • the communication unit 140 determines whether the ID information transmitted from the host apparatus 400 matches its own ID information, analyzes the received command (write command, read command, etc.), etc. I do.
  • the normal communication mode is an operation mode in which data communication for exchanging data such as ink remaining amount is performed between the host device 400 and the storage device 100.
  • the connection detection mode is an operation mode for detecting whether or not the storage device 100 is connected.
  • the response unit 160 instructs the communication unit 140 to output a response signal for notifying that the storage device is connected.
  • the response unit 160 is read from the storage unit 130 via the storage control unit 120 when the control signal SDET from the mode determination unit 150 is at the active level. Based on the ID information, the communication unit 140 is instructed to output a response signal in the clock cycle corresponding to the ID information.
  • the response unit 160 instructs to output a response signal according to the clock.
  • the host device 400 can designate a storage device that enters the connection detection mode by a reset signal, it is not necessary to read out ID information from the storage unit 130.
  • the internal oscillation circuit 170 generates an internal clock of the storage device 100 and supplies it to the control unit 110, the storage control unit 120, the storage unit 130, and the like.
  • the power-on reset (POR) circuit 180 performs a power-on reset process based on the second power supply voltage VDD. That is, the storage device 100 is reset until the power is turned on, and the reset of the storage device 100 is released when the power is turned on. Specifically, the power-on reset circuit 180 is powered on from the host device 400, and when the difference between the second power supply voltage VDD and the first power supply voltage VSS becomes equal to or higher than a threshold voltage (predetermined voltage), The power-on reset signal POROUT is set to the H level (high potential level, in a broad sense, the second voltage level).
  • a response signal for notifying that the storage device is connected can be output to the host device via the data terminal SDA. .
  • a terminal for detecting the presence or absence of the liquid container becomes unnecessary, and the number of terminals can be reduced.
  • the ID information is stored in the storage unit, in the connection detection mode, it is only necessary to read out the ID information from the storage unit. Therefore, by prohibiting (masking) access to other data, It is possible to prevent destruction of stored contents.
  • the detection time can be shortened.
  • the presence or absence of the liquid container can be detected by detecting a communication time-out error.
  • the bus connection because of the bus connection, it takes time until a timeout error occurs, and the time until detection becomes longer. If the time required for detection becomes longer, the risk of errors occurring during communication increases. As a result, it may be determined that the liquid container is not attached although the liquid container is attached.
  • FIG. 4 is an example of a timing chart of the normal communication mode of the storage device 100.
  • FIG. 4 shows a timing chart when transmitting write data from the host device 400 to the first to fourth storage devices 100-1 to 100-4 in the first configuration example (FIG. 1) of the system.
  • the host device 400 starts supplying power supply voltage to each storage device via the first power supply line and the second power supply line.
  • the voltage of the second power supply terminal VDD of each storage device reaches a predetermined voltage value (the voltage value is a voltage value based on the potential supplied from the first power supply line) (E1 in FIG. 4).
  • the power-on reset is released by the power-on reset (POR) circuit 180.
  • the host device 400 changes the reset signal level (voltage level of the reset terminal XRST in a broad sense) from the L level (voltage level indicating a reset state in a broad sense) to the H level (voltage level indicating a reset release state in a broad sense). (E2 in FIG. 4).
  • the mode determination unit 150 (control unit 110 in a broad sense) is configured such that the voltage level of the reset terminal XRST indicates the reset state (L) during the period in which the voltage level of the clock terminal SCK is the first voltage level (L level).
  • the level is changed to a voltage level (H level) indicating a reset release state (E2 in FIG. 4)
  • the operation mode is the normal communication mode (normal operation mode).
  • the control unit 110 determines that the operation mode is the normal communication mode, the voltage level of the clock terminal SCK changes from the L level (first voltage level in a broad sense) to the H level (second voltage in a broad sense).
  • the information output from the host device 400 is acquired via the data terminal SDA according to the clock after the change to (level). More specifically, the control unit 110 acquires a command as information output from the host device 400, analyzes the acquired command, receives data from the host device 400 based on the analysis result, or A process of transmitting data to the host device 400 is performed.
  • the host device 400 can send ID information before sending a command to designate a storage device.
  • the ID information is composed of i + 1 bits of I0 to Ii (i is a natural number), and a parity bit IP is added thereto.
  • the write command is composed of j + 1 bits of C0 to Cj (j is a natural number), and a parity bit CP is added thereto.
  • data is composed of k + 1 bits D0 to Dk, and a parity bit DP is added thereto.
  • Parity bits IP, CP, and DP are bits added for parity check, and are added so that the number of 1s is always even or odd.
  • the host device 400 can designate one storage device and set the normal communication mode. For example, when writing data is transmitted to the first storage device, the voltage level of the reset terminal XRST1 of the first storage device is set from L level to H level. In this way, the host device 400 can transmit a write command and write data to the first storage device. In this case, since the destination storage device can be designated by the reset signal, there is no need to transmit ID information.
  • the host device 400 can transmit write data to the first to fourth storage devices 100-1 to 100-4 and write data to the storage unit 130 of each storage device. it can. Similarly, the host device 400 can receive read data from the storage unit 130 of each storage device.
  • FIG. 5A and 5B are a first example of a timing chart of the connection detection mode of the storage device 100.
  • FIG. This first example is based on the first configuration example of the system shown in FIG.
  • FIG. 5A illustrates a second power supply voltage VDD, a reset signal (a signal input to the reset terminal XRST in a broad sense), a clock signal (a signal input to the clock terminal SCK in a broad sense), and a data signal (broad sense).
  • FIG. 5B is a detailed timing chart of a period in which each response signal ANSm (m is at least one integer satisfying 1 ⁇ m ⁇ n) is in the active state ACT.
  • the second power supply voltage VDD rises (A1 in FIG. 5A), and when VDD reaches a predetermined voltage value, the power-on reset (POR) circuit 180 generates a power-on reset signal POROUT (not shown).
  • the reset is released at the H level (high potential level, the second voltage level in a broad sense).
  • the clock signal level (the voltage level of the clock terminal SCK in a broad sense) changes from the L level (low potential level, the first voltage level in a broad sense) to the H level (A2 in FIG. 5A).
  • the reset signal level (voltage level of the reset terminal XRST in a broad sense) changes from the L level (voltage level indicating a reset state in a broad sense) to the H level (voltage level indicating a reset release state in a broad sense) (FIG. 5). (A) A3).
  • the mode determination unit 150 (control unit 110 in a broad sense) is configured such that the voltage level of the reset terminal XRST indicates a reset state (L) during a period in which the voltage level of the clock terminal SCK is the second voltage level (H level).
  • the level changes to a voltage level (H level) indicating a reset release state (A3 in FIG. 5A)
  • it is determined that the operation mode is the connection detection mode.
  • the voltage level of the clock terminal SCK changes from the H level to the L level (A4 in FIG. 5A).
  • This timing is the start timing of the first clock cycle T1. That is, after the power is turned on, the response unit 160 changes the voltage level of the clock terminal SCK from the first voltage level (L level) to the second voltage level (H level), and then the second voltage level (H level). ) To the first voltage level (L level) is determined to be the start timing of the first clock cycle T1.
  • the controller 110 corresponds to the m-th (m is 1 ⁇ 1) corresponding to the ID information of the storage device 100 in the first to n-th (n is an integer of 2 or more) clock cycles of the clock input to the clock terminal SCK.
  • the response signal ANSm is output to the host device 400 via the data terminal SDA in the clock cycle of at least one integer where m ⁇ n.
  • the control unit 110 determines that the operation mode is the connection detection mode
  • the voltage level of the clock terminal SCK is changed from the second voltage level (H level) to the first voltage level (L level).
  • the response signal ANSm for notifying that the storage device is connected is output to the host device 400 via the data terminal SDA in accordance with the clock after the change to.
  • one clock cycle is one physical cycle of the clock signal, but the present invention is not limited to this.
  • two physical cycles of the clock signal may be set as one clock cycle.
  • the storage device 100-1 whose ID information is 1 outputs a response signal ANS1 in the first clock cycle T1.
  • the storage device 100-2 whose ID information is 2 outputs the response signal ANS2 in the second clock cycle T2.
  • response signals ANS3 and ANS4 are output.
  • the ID information of each storage device is read from the storage unit 130 of each storage device 100 in the ID information read period TRM before the start timing of the first clock cycle T1 after it is determined that the connection detection mode is set. .
  • the control unit 110 After determining that the operation mode is the connection detection mode, the control unit 110 changes the voltage level of the reset terminal XRST from the voltage level indicating the reset release state (H level) to the voltage level indicating the reset state (L level). In this case, a process for terminating the connection detection mode is performed.
  • the length from the power-on timing (A1 in FIG. 5A) to the start timing of the first clock cycle T1 (A4 in FIG. 5A) is TP, and each clock of the clock input to the clock terminal SCK When the cycle length is TC, TP> TC. That is, the response unit 160 has a timing at which the voltage level of the clock terminal SCK changes from the second voltage level (H level) to the first voltage level (L level) after a period longer than TC elapses from the power-on timing. Is determined to be the start timing.
  • each circuit of the storage device 100 starts operating, and then the mode determination unit 150 determines that it is in the connection detection mode. Subsequently, the time until the ID information is read from the storage unit 130 can be secured.
  • FIG. 5B is a detailed timing chart of a period in which the response signal ANSm is in the active state ACT.
  • the response signal ANSm changes from the high impedance state (Hi-Z) to the H level, then changes from the H level to the L level, and again in the high impedance state (Hi-Z).
  • the first delay time TD1 has elapsed from the start timing of the m-th clock cycle Tm (that is, the falling timing of SCK)
  • the response signal ANSm changes from the high impedance state (Hi-Z) to the H level.
  • the second delay time TD2 has elapsed from the rise timing of SCK, the level changes from the H level to the L level.
  • FIG. 6A and 6B are second examples of timing charts of the connection detection mode of the storage device 100.
  • FIG. This second example is based on the first configuration example of the system shown in FIG.
  • FIG. 6A illustrates a second power supply voltage VDD, a reset signal (a signal input to the reset terminal XRST in a broad sense), a clock signal (a signal input to the clock terminal SCK in a broad sense), a data signal (a broad sense).
  • FIG. 6B is a detailed timing chart during a period in which each response signal ANSm is in the active state ACT.
  • the mode determination is the same as that of FIG. 5A described above, but the waveform of the response signal is different.
  • the second power supply voltage VDD rises (F1 in FIG. 6A), and when VDD reaches a predetermined voltage value, the power-on reset (POR) circuit 180 generates a power-on reset signal POROUT (not shown). Set to H level to release reset.
  • the clock signal level (the voltage level of the clock terminal SCK in a broad sense) changes from the L level to the H level (F2 in FIG. 6A), and then the reset signal level (the voltage level of the reset terminal XRST in a broad sense). ) Changes from L level to H level (F3 in FIG. 6A).
  • the mode determination unit 150 indicates the reset release state from the voltage level (L level) where the voltage level of the reset terminal XRST indicates the reset state during the period when the voltage level of the clock terminal SCK is the second voltage level (H level).
  • the voltage level (H level) is changed (F3 in FIG. 6A)
  • it is determined that the operation mode is the connection detection mode.
  • the voltage level of the clock terminal SCK changes from H level to L level (F4 in FIG. 6A).
  • This timing is the start timing of the first clock cycle T1. That is, after the power is turned on, the response unit 160 changes the voltage level of the clock terminal SCK from the first voltage level (L level) to the second voltage level (H level), and then the second voltage level (H level). ) To the first voltage level (L level) is determined to be the start timing of the first clock cycle T1.
  • the control unit 110 transmits the response signal ANSm to the data terminal SDA in the mth clock cycle corresponding to the ID information of the storage device 100 among the first to nth clock cycles of the clock input to the clock terminal SCK. To the host device 400 via
  • two physical cycles of the clock signal are defined as one clock cycle.
  • each of the first to fourth clock cycles T1 to T4 is two physical cycles of the clock signal.
  • the storage device 100-1 whose ID information is 1 outputs a response signal ANS1 in the first clock cycle T1.
  • the storage device 100-2 whose ID information is 2 outputs the response signal ANS2 in the second clock cycle T2.
  • response signals ANS3 and ANS4 are output.
  • the ID information of each storage device is read from the storage unit 130 of each storage device 100 in the ID information read period TRM before the start timing of the first clock cycle T1 after it is determined that the connection detection mode is set. .
  • the length from the power-on timing (F1 in FIG. 6A) to the start timing of the first clock cycle T1 (F4 in FIG. 6A) is TP, and the clock terminal When the length of each clock cycle of the clock input to SCK is TC, TP> TC.
  • FIG. 6B is a detailed timing chart of a period in which the response signal ANSm is in the active state ACT.
  • the control unit 110 sets the voltage level of the data terminal SDA to the second voltage level (H level) in the first period of the mth clock cycle Tm.
  • the response signal ANSm is output by setting the data terminal SDA to the high impedance state Hi-Z.
  • the two response signals interfere with each other when the response signal is output in the next clock cycle. Can be prevented.
  • the data terminal SDA Since a pull-down resistor is provided between the data terminal HDA of the host device 400 and the first power supply terminal HVSS, the data terminal SDA is set to the high impedance state Hi-Z in the second period of the clock cycle. Then, the voltage level of the data terminal SDA gradually falls from the H level to the L level. As a result, for example, as shown in FIG. 6A, in the clock cycles T1 to T4 corresponding to the first to fourth storage devices, they become the H level in the first period and gradually in the second period. A signal that falls to L level is output.
  • FIG. 7A and 7B show a third example of a timing chart of the connection detection mode of the storage device 100.
  • FIG. This third example is based on the second configuration example of the system shown in FIG.
  • FIG. 7A is a timing chart of the second power supply voltage VDD, first to fourth reset signals, clock signals, data signals, and response signals ANS1 to ANS4 input to the first to fourth storage devices. is there.
  • FIG. 7B is a detailed timing chart of a period in which the response signal ANSm (m is an integer satisfying 1 ⁇ m ⁇ 4) is in the active state ACT.
  • the second power supply voltage VDD rises (B1 in FIG. 7A), and when VDD reaches a predetermined voltage value, the power-on reset (POR) circuit 180 generates a power-on reset signal POROUT (not shown). Set to H level to release reset.
  • the clock signal level (voltage level of the clock terminal SCK) changes from the L level to the H level (B2 in FIG. 7A), and then the first reset signal level (the reset terminal XRST1 of the first memory device).
  • Voltage level changes from L level (voltage level indicating the reset state) to H level (voltage level indicating the reset release state) (B3 in FIG. 7A).
  • the mode determination unit 150 determines the voltage level of the reset terminal XRST1 during the period when the voltage level of the clock terminal SCK is the second voltage level (H level). Is changed from the voltage level (L level) indicating the reset state to the voltage level (H level) indicating the reset release state (B3 in FIG. 7A), it is determined that the operation mode is the connection detection mode.
  • the voltage level of the clock terminal SCK changes from the H level to the L level (B4 in FIG. 7A).
  • the control unit 110 of the first storage device 100-1 sets the response signal ANS1 to the active state ACT at this timing. That is, the response signal ANS1 is output to the host device 400 via the data terminal SDA in accordance with the clock after the voltage level of the clock terminal SCK has changed from the H level to the L level.
  • the first reset signal level changes from the H level (voltage level indicating the reset release state) to the L level (voltage level indicating the reset state) (FIG. 7A). B5).
  • the control unit 110 of the first storage device 100-1 performs processing to end the connection detection mode.
  • the clock signal level (the voltage level of the clock terminal SCK) changes from the L level to the H level again, and then the second reset signal level (the voltage level of the reset terminal XRST2 of the second memory device) is set to the L level ( It changes from a voltage level indicating a reset state) to an H level (voltage level indicating a reset release state).
  • the mode determination unit 150 (control unit 110 in a broad sense) of the second storage device 100-2 performs the voltage level of the reset terminal XRST2 during the period in which the voltage level of the clock terminal SCK is the second voltage level (H level). Is changed from the voltage level indicating the reset state (L level) to the voltage level indicating the reset release state (H level), it is determined that the operation mode is the connection detection mode.
  • the control unit 110 of the second storage device 100-2 sets the response signal ANS2 to the active state ACT at this timing. That is, the response signal ANS2 is output to the host device 400 via the data terminal SDA in accordance with the clock after the voltage level of the clock terminal SCK has changed from the H level to the L level.
  • the second reset signal level changes from the H level (voltage level indicating the reset release state) to the L level (voltage level indicating the reset state).
  • the control unit 110 of the second storage device 100-2 performs processing to end the connection detection mode.
  • connection detection period TDET2 of the second storage device 100-2 is provided after the connection detection period TDET1 of the first storage device 100-1, and further, the third and fourth Connection detection periods TDET3 and TDET4 of the storage devices 100-3 and 100-4 are sequentially provided.
  • connection detection periods TDET1 to TDET4 in order as shown in FIG. 7A, and the order of connection detection is arbitrary. For example, it is possible to start with TDET4 and end with TDET1. Alternatively, connection detection can be performed only for any one of the first to fourth storage devices 100-1 to 100-4.
  • FIG. 7B is a detailed timing chart of the response signal ANSm.
  • the control unit 110 of the m-th storage device 100-m changes the voltage level of the data terminal SDA from the high impedance state (Hi-Z) to the H level in the m-th connection detection period TDETm, and then from the H level. Change to L level and set to high impedance state (Hi-Z) again. By setting the high impedance state (Hi-Z) after the end of the connection detection period, it is possible to prevent interference with the response signal output in the next connection detection period.
  • the waveform of the response signal ANSm is not limited to that shown in FIG. 7B, and various waveforms are possible.
  • the voltage level of the data terminal SDA may be changed from the high impedance state (Hi-Z) to the H level, and then changed from the H level to the high impedance state (Hi-Z).
  • the period set to the H level may be two physical cycles of the clock signal.
  • FIG. 8A is a diagram for explaining the operation of the mode determination unit 150.
  • the mode determination unit 150 indicates the reset release state from the voltage level (L level) where the voltage level of the reset terminal XRST indicates the reset state during the period when the voltage level of the clock terminal SCK is the second voltage level (H level).
  • the control signal SDET for the response unit 160 is set to the active level (H level).
  • the voltage level of the reset terminal XRST is changed from the voltage level (L level) indicating the reset state to the voltage level (H level) indicating the reset release state.
  • the control signal SCOM for the storage control unit 120 is set to the active level (H level).
  • FIG. 8B shows a configuration example of the mode determination unit 150.
  • the mode determination unit 150 is configured using a D flip-flop circuit. The operation of this circuit is the same as that of a normal D flip-flop circuit. That is, at the rising edge of the voltage level of the reset terminal XRST, the voltage level of the clock terminal SCK is captured and held as the output SDET, and at the same time, the inverted output is held as the output SCOM.
  • FIG. 9 shows a basic configuration example of the response unit 160.
  • the response unit 160 includes an ID match determination unit 161, a counter 162, an ID holding unit 163, and an output unit 165.
  • the ID match determination unit 161 determines a match between the count value of the counter 162 and the value of the ID information read from the storage unit 130.
  • the counter 162 counts the clock CLK input to the clock terminal SCK after the start timing of the first clock cycle T1.
  • the ID holding unit 163 holds the value of the ID information read from the storage unit 130 and outputs it to the ID match determination unit 161.
  • the output unit 165 outputs an output instruction RSP for outputting a response signal ANS to the communication unit 140 based on the determination result of the ID match determination unit 161.
  • the response unit 160 issues a response signal output instruction when the count value matches the ID information value.
  • the mode determination unit 150 determines that the operation mode is the connection detection mode (A3 in FIG. 5A)
  • the mode determination unit. 150 sets the control signal SDET to an active level.
  • the storage control unit 120 reads the value of the ID information from the storage unit 130 in the ID information reading period TRM, and the ID holding unit 163 holds the value of the ID information.
  • the counter 162 starts the count process of the clock CLK after the start timing of the first clock cycle T1 (A4 in FIG. 5A).
  • the ID match determination unit 161 determines whether the count value of the counter 162 matches the value of the ID information, and outputs a response signal ANS from the output unit 165 to the communication unit 140 if they match.
  • the storage device 100 does not need to output a response signal in a clock cycle corresponding to its own ID information. Therefore, the response unit 160 may output the output instruction RSP for outputting the response signal ANS when the mode determination unit 150 determines the connection detection mode. By doing so, the configuration of the response unit 160 can be simplified.
  • FIG. 10 shows an example of the correspondence between ID information and clock cycles.
  • FIG. 11 shows another example of the correspondence between ID information and clock cycles.
  • FIG. 11 shows an integrated liquid container in which one liquid container stores a plurality of colors of liquid, in addition to a single color liquid container in which one liquid container (ink cartridge) stores one color of liquid (such as ink). Also shown.
  • a response signal can be output in clock cycles T2 to T4.
  • the response unit 160 issues a response signal output instruction in a plurality of clock cycles among the first to nth clock cycles T1 to Tn. Can do.
  • the liquid container 300 of the present embodiment when the liquid container 300 stores liquids of a plurality of colors, in a plurality of clock cycles corresponding to a plurality of colors among the first to nth clock cycles T1 to Tn.
  • a response signal can be output.
  • the 1st to nth clock cycles can be associated with n color inks respectively, so the firmware of the host device can be changed regardless of whether the ink cartridge is a single color type or an integral type. It becomes possible to cope without doing.
  • the storage device that outputs the response signal that is, the storage device that is the target of connection detection can be specified. Even when the container 300 stores liquids of a plurality of colors, the storage device does not need to output a plurality of response signals.
  • the host device 400 is an ink jet printer
  • the liquid container 300 is an ink cartridge
  • the substrate 200 is a circuit board provided in the ink cartridge
  • the host device, the liquid container, and the substrate may be other devices, containers, and substrates.
  • the host device may be a memory card reader / writer
  • the substrate may be a circuit board provided on the memory card.
  • An ink chamber (not shown) for containing ink is formed inside the ink cartridge 300 (liquid container in a broad sense) shown in FIG.
  • the ink cartridge 300 is provided with an ink supply port 340 that communicates with the ink chamber.
  • the ink supply port 340 is for supplying ink to the print head unit when the ink cartridge 300 is mounted on the printer.
  • the ink cartridge 300 includes a circuit board 200 (substrate in a broad sense).
  • the circuit board 200 is provided with the storage device 100 of this embodiment, and stores data and transmits / receives data to / from the host device 400.
  • the circuit board 200 is realized by a printed circuit board, for example, and is provided on the surface of the ink cartridge 300.
  • the circuit board 200 is provided with a terminal such as a second power supply terminal VDD. Then, when the ink cartridge 300 is mounted on the printer, the terminals and the terminals on the printer side come into contact (electrically connected) to exchange power and data.
  • FIG. 13A and 13B show a detailed configuration example of the circuit board 200 provided with the storage device 100 of the present embodiment.
  • a terminal group having a plurality of terminals is provided on the surface (surface connected to the printer) of the circuit board 200.
  • This terminal group includes a first power supply terminal VSS, a second power supply terminal VDD, a reset terminal XRST, a clock terminal SCK, and a data terminal SDA.
  • Each terminal is realized by, for example, a metal terminal formed in a rectangular shape (substantially rectangular shape).
  • Each terminal is connected to the storage device 100 via a wiring pattern layer or a through hole (not shown) provided on the circuit board 200.
  • the storage device 100 of this embodiment is provided on the back surface of the circuit board 200 (the surface on the back side of the surface connected to the printer).
  • the storage device 100 can be realized by, for example, a semiconductor storage device having a ferroelectric memory.
  • the storage device 100 stores various data related to the ink or the ink cartridge 300, and stores data such as ID information for identifying the ink cartridge 300 and ink consumption.
  • the ink consumption data is data indicating the total amount of ink consumed when printing is performed on the ink stored in the ink cartridge 300.
  • the ink consumption data may be information indicating the ink amount in the ink cartridge 300 or information indicating the ratio of the consumed ink amount.
  • FIGS. 14A to 14C show detailed configuration examples of the four-color integrated liquid container 300 and the substrate 200.
  • FIG. A four-color integrated liquid container (ink cartridge) 300 shown in FIG. 14A stores four colors of liquid (ink) of black K, cyan C, magenta M, and yellow Y.
  • the substrate 200 is a common substrate (substrate in a broad sense) used for the four-color integrated liquid container 300, and has four sets of terminal groups corresponding to the four colors (C, M, Y, K). .
  • This terminal group includes a first power supply terminal VSS, a second power supply terminal VDD, a reset terminal XRST, a clock terminal SCK, and a data terminal SDA.
  • FIG. 14B shows a first configuration example of the common substrate (substrate) 200.
  • This configuration example includes first to fourth storage devices 100-1 to 100-4, and these four storage devices correspond to four colors (C, M, Y, K), respectively.
  • the first storage device 100-1 has ID information corresponding to the cyan C liquid color, and outputs a response signal during a clock cycle corresponding to the cyan C liquid color in the connection detection mode.
  • each storage device is provided on the back surface of the common substrate 200 (the surface opposite to the surface having the terminals), and thus is indicated by a broken line.
  • FIG. 14C shows a second configuration example of the common substrate (substrate) 200.
  • This configuration example includes one storage device 100.
  • the storage device 100 is provided at a position corresponding to the cyan C liquid color, but may be provided at a position corresponding to another liquid color.
  • the position corresponding to magenta M or the position corresponding to yellow Y may be used.
  • a terminal group corresponding to a liquid color (magenta M, yellow Y, black K) without a storage device is electrically connected to a terminal group corresponding to cyan C with a storage device. May be electrically connected or electrically disconnected.
  • the reset terminal XRST corresponding to magenta M may be electrically connected to the reset terminal XRST corresponding to cyan C, or may be electrically disconnected.
  • a configuration in which the number of storage devices provided on the common substrate (substrate) 200 is two or three is also possible.
  • a first storage device corresponding to black K and a second storage device corresponding to the other three colors may be provided.
  • a first storage device corresponding to black K, a second storage device corresponding to cyan C, and a third storage device corresponding to the other two colors may be provided.
  • FIG. 15 shows a basic configuration example of the host device 400 of this embodiment.
  • the host device 400 is, for example, a printer main body, and includes a power supply unit 410, a communication processing unit 420, a monitoring unit 430, a host control unit 440, a display unit 450, and a display control unit 460. Further, the host device 400 includes first to k-th (k is an integer of 2 or more) host-side terminals. Specifically, for example, a host side reset terminal HRST, a host side clock terminal HCK, a host side data terminal HDA, a first host side power supply terminal HVSS, and a second host side power supply terminal HVDD are included.
  • the power supply unit 410 supplies power to the first to nth storage devices 100-1 to 100-n.
  • the communication processing unit 420 includes first to nth storage devices 100-1 to 100-th through first to kth host-side terminals, for example, a host-side reset terminal HRST, a host-side clock terminal HCK, and a host-side data terminal HDA. Communication processing with 100-n is performed.
  • the host device 400 includes first to nth host side reset terminals HRST1 to HRSTn as host side reset terminals.
  • the monitoring unit 430 includes the first to nth storage devices in each of the first to nth clock cycles T1 to Tn of the clock supplied to the first to nth storage devices 100-1 to 100-n. Whether response signals from 100-1 to 100-n are output is monitored.
  • the monitoring unit 430 receives from the storage device that is the target of connection detection among the first to nth storage devices 100-1 to 100-n. It is monitored whether or not a response signal is output.
  • the host control unit 440 performs control processing of the power supply unit 410, the communication processing unit 420, the monitoring unit 430, and the display unit 450.
  • the display unit 450 is, for example, an LCD (liquid crystal display) or the like, and displays an operation screen, an operation state, an error message, and the like of the host device 400 (printer). In the connection detection mode, the display unit 450 displays the connection detection result based on the monitoring result of the monitoring unit 430.
  • the display control unit 460 performs control to display the connection detection result on the display unit 450.
  • the display control unit 460 is realized by a known display controller or the like.
  • FIG. 16 is a diagram for explaining power supply periods in the normal communication mode and the connection detection mode.
  • the power supply unit 410 supplies power such that TA> TB, where TA is the length of the power supply period in the normal communication mode and TB is the length of the power supply period in the connection detection mode.
  • a power supply period in the connection detection mode may be provided between the power supply period in the normal communication mode and the power supply period in the next normal communication mode.
  • the power supply period in the connection detection mode may be provided a plurality of times in succession.
  • connection detection mode period can be provided in a short period between one normal communication mode period and the next normal communication mode period, it interferes with normal data communication. Ink cartridge connection detection can be performed. As a result, the reliability of the printer system can be improved.
  • connection of the ink cartridge can be detected in a short time, the presence or absence of the ink cartridge can be displayed on the display unit 450 in real time. As a result, an error when the user replaces the ink cartridge can be prevented and operability can be improved.
  • a method of detecting a communication timeout error in the normal communication mode can be considered.
  • this method has a problem that it takes time until a timeout error occurs due to the bus connection, and the connection detection time becomes long. For this reason, there is a greater possibility that an error will occur during communication. If an error occurs, it may be determined that the ink cartridge is not installed even though the ink cartridge is installed.
  • connection detection mode different from the normal communication mode is provided, and connection detection is performed in the period of n clock cycles in the connection detection mode, for example, as shown in FIGS. 5 (A) and 6 (A). Can be completed.
  • the length TB of the power supply period in the connection detection mode is calculated from the length TA of the power supply period in the normal communication mode. Can be small enough. By doing this, it is possible to set a short connection detection mode period between one normal communication mode period and the next normal communication mode period, and to perform connection detection there.
  • connection detection mode it is not necessary to perform connection detection in the normal communication mode, and by providing the connection detection mode, it is possible to prevent the bandwidth of the normal communication mode from being limited.
  • the detection result can be displayed in real time, and errors during detection can be reduced.

Landscapes

  • Ink Jet (AREA)

Abstract

L'invention porte sur un dispositif de stockage, un substrat, un contenant de liquide et un système capables de détecter efficacement une connexion sans augmenter le nombre de bornes. Un dispositif de stockage (100) comprend une unité de stockage (130), une unité de commande de stockage (120) pour gérer l'accès à l'unité de stockage (130), une unité de commande (110) pour traiter des communications avec un dispositif hôte, une borne de données (SDA), une borne de réinitialisation (XRST) et une borne d'horloge (SCK). L'unité de commande (110) détermine que le mode de fonctionnement est un mode de communication ordinaire si le niveau de tension de la borne de réinitialisation (XRST) passe d'un niveau de tension indiquant un état de réinitialisation à un niveau de tension indiquant un état d'annulation de réinitialisation durant une période dans laquelle le niveau de tension de la borne d'horloge (SCK) est à un premier niveau de tension, et détermine que le mode de fonctionnement est un mode de détection de connexion si le niveau de tension de la borne de réinitialisation (XRST) passe du niveau de tension indiquant l'état de réinitialisation au niveau de tension indiquant l'état d'annulation de réinitialisation durant une période dans laquelle le niveau de tension de la borne d'horloge (SCK) est un second niveau de tension.
PCT/JP2011/053444 2010-02-22 2011-02-18 Dispositif de stockage, substrat, contenant de liquide et système WO2011102440A1 (fr)

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