WO2011097883A1 - 一种体接触器件结构及其制造方法 - Google Patents

一种体接触器件结构及其制造方法 Download PDF

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Publication number
WO2011097883A1
WO2011097883A1 PCT/CN2010/077274 CN2010077274W WO2011097883A1 WO 2011097883 A1 WO2011097883 A1 WO 2011097883A1 CN 2010077274 W CN2010077274 W CN 2010077274W WO 2011097883 A1 WO2011097883 A1 WO 2011097883A1
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Prior art keywords
stack
layer
source
drain
region
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French (fr)
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梁擎擎
钟汇才
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/058,996 priority Critical patent/US20120018739A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Definitions

  • the present invention generally relates to a semiconductor device and a method of fabricating the same, and, in particular, to a body contact device structure based on a gate replacement process and a method of fabricating the same.
  • the body contact structures currently used in the silicon-on-insulator (S0I) technology are mainly T-gates and H-gate structures, but both of these structures require the formation of the body contact region (701) of the active region and the body contact thereon ( 702), and a barrier (703) is needed to isolate the body contact region (701) and the source and drain regions (704).
  • S0I silicon-on-insulator
  • H-gate structures both of these structures require the formation of the body contact region (701) of the active region and the body contact thereon ( 702), and a barrier (703) is needed to isolate the body contact region (701) and the source and drain regions (704).
  • the parasitic gate capacitance (720) refers to the barrier (703) and the present
  • the parasitic capacitance between the body (700), the parasitic contact resistance (730) refers to the parasitic resistance between the body contact (702) and the intrinsic body (700).
  • the present invention provides a method of fabricating a body contact device structure, the method comprising: providing a semiconductor substrate having an isolation region therein; forming a dummy gate stack on the semiconductor substrate and the isolation region, and Forming a sidewall in the sidewall of the dummy gate stack, and forming a source region and a drain region in the semiconductor substrate, and covering the source region, the drain region, and the isolation region to form an insulating dielectric layer; One end of the dummy gate stack is removed, the substrate and the isolation region are exposed to form an opening, wherein the un-removed portion of the dummy gate stack is a body extraction stack, and the body extraction stack includes a body extraction layer, the body The extraction layer is in direct contact with the substrate; forming a replacement gate stack in the opening, the replacement gate stack including a gate dielectric layer and a gate electrode; forming source-drain contacts on the source and drain regions, The body is brought up to form a body contact on the body extraction layer in the stack and a material different from the
  • the present invention also provides a body contact device structure, the structure comprising: having a semiconductor substrate, wherein the semiconductor substrate has an isolation region; a source region and a drain region formed on the semiconductor substrate; a semiconductor substrate between the source region and the drain region and a body on the isolation region to extract a stack and a replacement gate stack; wherein the body extraction stack includes a body extraction layer; the replacement gate stack includes a gate dielectric layer and a gate An electrode; a sidewall formed on the sidewall of the body extraction stack and the replacement gate stack; a source-drain contact formed in the source region and the drain region, and a body contact on the body extraction layer, and A material different from the substrate is formed.
  • FIG. 1 shows a plan view of a body contact device structure of an embodiment of the invention
  • FIGS. 2 is a flow chart showing a method of fabricating a body contact device structure according to an embodiment of the present invention
  • FIGS. 3-6 are plan views showing respective manufacturing stages of the body contact device structure of the embodiment of the present invention
  • FIGS. 3A-6A show AA'-direction view of each manufacturing stage of the body contact device structure of the embodiment of the present invention
  • 3B-6B are views showing a BB' direction of each manufacturing stage of the body contact device structure of the embodiment of the present invention.
  • 4C-6C are views showing a CC' direction of each manufacturing stage of the body contact device structure of the embodiment of the present invention.
  • Figure 7 shows a top view of the T-gate structure
  • Fig. 8 is a BB' arrow view of the T-gate structure of Fig. 7. detailed description
  • the present invention generally relates to a semiconductor device and a method of fabricating the same, and, in particular, to a body contact device structure based on a gate replacement process and a method of fabricating the same.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIG. 1 there is shown a body contact device structure formed based on a back gate process in which a replacement gate stack 500 and a body extraction stack 400 are formed in a source region and a drain, in accordance with an embodiment of the present invention.
  • the body extraction layer 204 of the body extraction stack 400 is formed directly over the substrate 200 and the isolation region 202, and a body contact is formed on the body extraction layer 204. 238, the device structure effectively reduces parasitic effects and device area.
  • a semiconductor substrate 200 is provided, the semiconductor substrate having an isolation region 202, with reference to Figure 3A.
  • the substrate 200 includes a silicon substrate (e.g., a wafer) located in a crystal structure, and may also include other basic semiconductors or compound semiconductors such as Ge, GeSi, GaAs, InP, SiC, or diamond.
  • the substrate 200 can include various doping configurations in accordance with design requirements known in the art (e.g., a p-type substrate or an n-type substrate). Additionally, substrate 200 can optionally include an epitaxial layer that can be altered by stress to enhance performance, and can include a silicon-on-insulator (SOI) structure.
  • the isolation region 202 can include silicon dioxide or other material that can separate the active regions of the device.
  • a dummy gate stack 300 is formed on the semiconductor substrate 200 and the isolation region 202, and a sidewall spacer 210 is formed on the sidewall of the dummy gate stack 300, and A source region and a drain region 214 are formed in the semiconductor substrate, and the source region 214, the drain region 214, and the isolation region 202 are formed to form an insulating dielectric layer 216, as shown in FIG. 3 (top view), FIG. 3A (AA' To the view) and Figure 3B ( ⁇ ' to the view).
  • the device structure shown in Figure 3 can be formed by conventional process steps, materials, and equipment, as will be apparent to those skilled in the art.
  • the dummy gate stack 300 may be formed by sequentially depositing a body extraction layer 204, a first oxide cap layer 206, and a second nitride cap layer 208 on the substrate 200 and the isolation region 202, and then using dry or wet etching. Techniques are formed by patterning the body extraction layer 204, the first oxide cap layer 206, and the second nitride cap layer 208.
  • the body extraction layer 204 may be formed of a semiconductor or semiconductor compound material different from the substrate 200, such as Ge, GeSi, GaAs, InP, SiC, polysilicon or diamond, etc., and the oxide cap layer 206 may be an oxide.
  • a material such as Si0 2 or the like, the second nitride cap layer 208 may be a nitride material such as SiN or the like.
  • the sidewall spacers 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride doped silicon glass, low k dielectric materials, and combinations thereof, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the side wall 210 may be plasma enhanced by including an atomic deposition method.
  • the side wall is a two-layer structure including a first side wall 210-1 and a second side wall 210-2, as shown in Fig. 3A.
  • a source/drain shallow region 212 is formed in the semiconductor substrate 200, and after the second spacer 210-2 is formed, a source is formed in the semiconductor substrate 200.
  • the source/drain shallow region 212 and the source and drain regions 214 may be formed by implanting p-type or n-type dopants or impurities into the substrate 200 according to a desired transistor structure, which may be Formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes.
  • the formation of the source/drain shallow junction region includes source/drain extension and/or halo implantation.
  • the insulating dielectric layer 216 may be formed by first depositing (eg, PECVD) an insulating dielectric layer 216 on the device and then planarizing the insulating dielectric layer 216, such as by chemical mechanical polishing (CMP). The method removes the insulating dielectric layer 216 over the dummy gate stack 300, with the second nitride cap layer 208 as a stop layer, forming a structure as shown in FIG. 3A.
  • the insulating dielectric layer 216 may be, but not limited to, for example, undoped silicon oxide (SiO 2 ), doped silicon oxide (eg, Borosilicate glass, borophosphosilicate glass, etc.).
  • the dummy gate stack 300-end is removed, and the substrate 200 and the isolation region 202 are exposed to form an opening 218, wherein the un-removed portion of the dummy gate stack 300 is a body-extracting stack 400, as shown in FIG.
  • the first gate of the dummy gate stack 300 is masked by the RIE method, and the first oxide cap layer 206, the body lead-out layer 204, and the substrate 200 are respectively used as a stop layer, and the second end of the dummy gate stack 300 without the mask is sequentially removed.
  • the take-up layer 204, the first oxide cap layer 206, and the second nitride cap layer 208 are as shown in FIG. 4A and FIG. 4C (C-direction view).
  • a replacement gate stack 500 is formed within the opening 218, the replacement gate stack 500 including a gate dielectric layer 230 and a gate electrode 232, as shown in FIG. 5 (top view), FIG. 5 ( ⁇ 's view), and FIG. ( ⁇ , to the view) as shown.
  • a gate dielectric layer 230 and a gate electrode 232 are sequentially deposited on the device, and the gate dielectric layer 230 may include, but is not limited to, a high-k dielectric material (for example, a material having a high dielectric constant compared to silicon oxide).
  • high-k dielectric materials include, for example, germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide (HfTaO), niobium oxide (HfTiO). , yttria-yttria (HfZrO), combinations thereof and/or other suitable materials.
  • germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide (HfTaO), niobium oxide (HfTiO).
  • germanium-based materials such as hafnium oxide (Hf0 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium oxide (HfTaO
  • the gate electrode 232 may be a one-layer or multi-layer structure, and may be, but not limited to, one or more elements selected from the group consisting of: TaN, Ta 2 C, HfC, TiC, TiN, TiAl , MoN, MoC, TaTbN, TaErN, TaYbN, TaSiN, TaAlN, TiAlN, TaHf, TiHf, HfSiN, MoSiN, MoAlN, Mo, Ru, RuO 2 , RuTa x , NiTa x , polysilicon and metal silicide, and their combination.
  • gate dielectric layer 230 and gate electrode 232 can be formed using conventional deposition processes such as sputtering, PLD, MOCVD, ALD, PEALD, or other suitable methods. Then, the gate dielectric layer 230 and the gate electrode 232 over the body extraction stack 400 and the insulating dielectric layer 216 may be removed by a chemical mechanical polishing (CMP) method with the second nitride cap layer 208 as a stop layer.
  • CMP chemical mechanical polishing
  • a replacement gate stack 500 including a gate dielectric layer 230 and a gate electrode 232 is formed in the opening 218 as shown in FIG. 5A (AA'-view) and FIG. 5B (BB, view). In this step, the body lead stack 400 has not changed, as shown in Figure 5C.
  • a source/drain metal silicide layer 234 is formed on the semiconductor substrate 200 of the source and drain regions 214, and a body extraction metal is formed on the body extraction layer 204.
  • the silicide layer 235 is shown in Fig. 6A (AA' view), Fig. 6B ( ⁇ 's view), and Fig. 6C (CC, view).
  • a second dielectric layer 217 is formed on the insulating dielectric layer 216.
  • the second dielectric layer 217 may be, but not limited to, for example, undoped silicon oxide (SiO 2 ), doped silicon oxide (such as boron). Silicon glass, borophosphosilicate glass, etc.).
  • the layer 235, the metal silicided material may be, for example, Co, Ni, Mo, Pt, W, and the like.
  • source and drain contacts 236 are formed on the source and drain regions 214, body contacts 238 are formed on the body extraction layer 204, and gate contacts 240 are formed on the gate electrodes 232 of the replacement gate stack 500.
  • Figure 6 top view
  • Figure 6A ⁇ ' to view
  • Figure 6 ⁇ BB' to view
  • Figure 6C CC, to view
  • a contact metal material is deposited over the device to fill the contact holes, such as W, to form source and drain contacts 236, body contacts 238, and gate contacts 240.
  • a body contact device structure based on a back gate process and a method of fabricating the same.
  • a body extraction layer is directly formed on a substrate, and a body contact is formed on the body extraction layer, and the structure is reduced.
  • the device area can effectively reduce the parasitic effects of the germanium gate and the germanium gate structure, thereby improving the performance of the body contact device structure.

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  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

一种体接触器件结构及其制造方法
技术领域
本发明通常涉及半导体器件及其制造方法， 具体来说， 涉及一种基于 栅极替代工艺的体接触器件结构及其制造方法。 背景技术
对于 MOSFET器件来说， 体接触对其电学特性影响是一个非常重要的 特征。 首先， 它可以减小由浮体效应导致的转换速度的不确定性， 再者， 可以方便从外部连接到诸如混频器（Mixer )和压控振荡器（ VCO , Voltage Controlled Oscillator ) 等电路设计的体。 目前在绝缘硅（ S0I )技术中常用 的体接触结构主要是 T型栅和 H型栅结构， 但这两种结构都需要形成有源 区的体接触区 （701 )和其上的体接触 （ 702 ) , 并需要隔栅（ 703 ) 来隔离 体接触区 （701 ) 和源漏区 （ 704 ) , 如图 7所示的 T型栅结构为例， 这样 的结构增加了器件的面积， 并导致多余的寄生效应， 比如寄生栅体电容 (parasitic gate-body capacitor)、 哥生体接触电阻 ( arasitic body resistor )等 , 如图 8所示， 寄生栅体电容（ 720 )指隔栅（ 703 ) 与本征体（ 700 )之间的 寄生电容， 寄生体接触电阻（ 730 )指体接触 （ 702 )与本征体（ 700 )之间 的寄生电阻， 这些寄生效应降低了器件的性能， 另外由于这些寄生效应的 存在， 对 SOI短沟道器件的本征电学测试变得困难。
因此，需要提出一种能够有效减少或排除寄生效应的体接触器件结构。 发明内容
本发明提供了一种制造体接触器件结构的方法， 所述方法包括： 提供 半导体衬底， 所述半导体衬底内有隔离区； 在所述半导体衬底和隔离区上 形成伪栅堆叠， 以及在所述伪栅堆叠侧壁形成侧墙， 以及在所述半导体衬 底内形成源极区和漏极区， 并覆盖所述源极区、 漏极区以及隔离区形成绝 缘介电层； 将伪栅堆叠一端去除， 暴露衬底和隔离区以形成开口， 其中伪 栅堆叠未去除部分为体引出堆叠， 所述体引出堆叠包括体引出层， 所述体 引出层直接和衬底接触； 在所述开口内形成替代栅堆叠， 所述替代栅堆叠 包括栅介质层和栅电极； 在所述源极区和漏极区上形成源漏接触， 在所述 体引出堆叠中的体引出层上形成体接触以及在替代栅堆叠的栅电极上形成 与所述衬底不同的材料形成。
本发明还提供了一种体接触器件结构， 所述结构包括： 具有半导体衬 底， 其中所述半导体衬底内有隔离区； 在半导体衬底上形成的源极区和漏 极区； 形成于所述源极区和漏极区之间的半导体衬底和隔离区上的体引出 堆叠和替代栅堆叠； 其中所述体引出堆叠包括体引出层； 所述替代栅堆叠 包括栅介质层和栅电极； 形成于所述体引出堆叠和替代栅堆叠侧壁的侧墙； 形成于所述源极区和漏极区的源漏接触， 以及体引出层上的体接触， 以及 成， 且釆用与所述衬底不同的材料形成。
通过釆用本发明所述的方法形成的体接触器件结构， 有效的减小了寄 生效应， 提高了体接触器件结构的性能。 附图说明
图 1示出了发明实施例的体接触器件结构的俯视图；
图 2示出了本发明实施例的体接触器件结构的制造方法的流程图； 图 3-6示出了本发明实施例的体接触器件结构各个制造阶段的俯视图； 图 3A-6A示出了本发明实施例的体接触器件结构各个制造阶段的 AA'向 视图；
图 3B-6B示出了本发明实施例的体接触器件结构各个制造阶段的 BB'向 视图；
图 4C-6C示出了本发明实施例的体接触器件结构各个制造阶段的 CC'向 视图；
图 7示出了 T型栅结构的俯视图；
图 8示出了图 7中 T型栅结构的 BB'向视图。 具体实施方式
本发明通常涉及半导体器件及其制造方法， 具体来说， 涉及一种基于 栅极替代工艺的体接触器件结构及其制造方法。 下文的公开提供了许多不 同的实施例或例子用来实现本发明的不同结构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且 目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 / 或字母。 这种重复是为了简化和清楚的目的， 其本身不指示所讨论各种实 施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料 的例子， 但是本领域普通技术人员可以意识到其他工艺的可应用于性和 /或 其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可 以包括第一和第二特征形成为直接接触的实施例， 也可以包括另外的特征 形成在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接 接触。
参考图 1 , 图 1示出了根据本发明的实施例的体接触器件结构， 所述器件 结构基于后栅工艺形成，所述替代栅堆叠 500和体引出堆叠 400形成于源极区 和漏极区 214之间的半导体衬底 200和隔离区 202之上， 所述体引出堆叠 400 的体引出层 204直接形成于衬底 200和隔离区 202之上， 且在体引出层 204 上形成体接触 238, 所述器件结构有效的减小了寄生效应和器件面积。
参考图 2,图 2示出了根据本发明的实施例的体接触器件结构的制造方法， 以下将详细描述所述器件结构的制造方法。在步骤 101 ,提供半导体衬底 200, 所述半导体衬底有隔离区 202 , 参考图 3A。 在本实施例中， 衬底 200包括 位于晶体结构中的硅衬底 （例如晶片） ， 还可以包括其他基本半导体或化 合物半导体， 例如 Ge、 GeSi、 GaAs、 InP、 SiC 或金刚石等。 根据现有技 术公知的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 200可以包括各 种掺杂配置。 此外， 衬底 200 可以可选地包括外延层， 可以被应力改变以 增强性能， 以及可以包括绝缘体上硅（ SOI )结构。 所述隔离区 202可以包 括二氧化硅或者其他可以分开器件的有源区的材料。
在步骤 102,在所述半导体衬底 200和隔离区 202上形成伪栅（ Dummy Gate )堆叠 300, 以及在所述伪栅堆叠 300侧壁形成侧墙 210, 以及在所述 半导体衬底内形成源极区和漏极区 214 , 并覆盖所述源极区 214、 漏极区 214以及隔离区 202形成绝缘介电层 216 , 如图 3 (俯视图） 、 图 3A ( AA' 向视图） 及图 3B ( ΒΒ'向视图） 所示。 如图 3所示的器件结构， 可以通过 常规工艺步骤、 材料以及设备来形成， 其对本领域的技术人员来说是显而 易见的。
所述伪栅堆叠 300可以通过在所述衬底 200和隔离区 202上依次沉积 体引出层 204、 第一氧化物帽层 206和第二氮化物帽层 208 , 而后利用干法 或湿法蚀刻技术将所述体引出层 204、 第一氧化物帽层 206和第二氮化物 帽层 208图形化来形成。 所述体引出层 204可以选用与所述衬底 200不同 的半导体或半导体化合物材料形成， 例如 Ge、 GeSi、 GaAs、 InP、 SiC、 多 晶硅或金刚石等， 所述氧化物帽层 206可以为氧化物材料， 如 Si02等， 所 述第二氮化物帽层 208可以为氮化物材料， 如 SiN等。
所述侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅、 氟化物掺 杂硅玻璃、低 k电介质材料及其组合，和 /或其他合适的材料形成。侧墙 210 可以具有多层结构。 侧墙 210可以通过包括原子沉积方法、 等离子增强化 本实施例中， 侧墙为两层结构， 包括第一侧墙 210-1和第二侧墙 210-2, 如 图 3A所示。
在形成第一侧墙 210-1之后， 在所述半导体衬底 200内形成源 /漏浅节 区 212 , 并在形成第二侧墙 210-2之后， 在所述半导体衬底 200内形成源极 区和漏极区 214。 所述源 /漏浅节区 212以及源极区和漏极区 214 , 可以通 过根据期望的晶体管结构， 注入 p型或 n型掺杂物或杂质到所述衬底 200 中而形成， 可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的方法形 成。 所述源 /漏浅节区的形成包括源 /漏延伸和 /或 halo注入。
所述绝缘介电层 216可以通过先在所述器件上沉积 (如 PECVD )绝缘 介电层 216, 而后对所述绝缘介电层 216平坦化处理来形成， 例如可以通 过化学机械抛光（CMP )方法来去除伪栅堆叠 300之上的绝缘介电层 216, 以第二氮化物帽层 208为停止层，形成如图 3A所示的结构。所述绝缘介电 层 216可以是但不限于例如未掺杂的氧化硅（Si02 ) 、 掺杂的氧化硅（如 硼硅玻璃、 硼磷硅玻璃等） 等。
在步骤 103 , 将伪栅堆叠 300—端去除， 暴露衬底 200和隔离区 202 以形成开口 218 , 其中伪栅堆叠 300未去除部分为体引出堆叠 400 , 如图 4
(俯视图） 、 图 4A ( ΑΑ'向视图） 、 图 4Β ( ΒΒ'向视图 ) 所示。 将伪栅堆 叠 300的一端掩膜， 通过 RIE的方法， 分别以第一氧化物帽层 206、 体引 出层 204 以及衬底 200为停止层， 依次去除伪栅堆叠 300未掩膜一端的第 二氮化物帽层 208、第一氧化物帽层 206和体引出层 204 , 以形成开口 218, 并去除掩膜， 伪栅堆叠 300 未去除部分为体引出堆叠 400 , 所述体引出堆 叠 400包括体引出层 204、 第一氧化物帽层 206和第二氮化物帽层 208 , 如 图 4Β ( ΒΒ'向视图 ) 和图 4C ( C 向视图 ) 所示。
在步骤 104 , 在所述开口 218内形成替代栅堆叠 500, 所述替代栅堆叠 500包括栅介质层 230和栅电极 232 , 如图 5 (俯视图） 、 图 5Α ( ΑΑ'向视 图） 、 图 5Β ( ΒΒ，向视图） 所示。 首先， 在所述器件上依次沉积栅介质层 230和栅电极 232 ,所述栅介质层 230可以包括但不限于高 k介质材料， (例 如， 和氧化硅相比， 具有高介电常数的材料） ， 高 k介质材料的例子包括 例如铪基材料，如氧化铪（ Hf02 ),氧化铪硅（ HfSiO ),氮氧化铪硅（ HfSiON ), 氧化铪钽（ HfTaO ) , 氧化铪钛（ HfTiO ) , 氧化铪锆（ HfZrO ) , 其组合 和 /或者其它适当的材料。 所述栅电极 232可以是一层或多层结构， 可以但 不限于从包含下列元素的组中选择一种或多种元素进行沉积： TaN、 Ta2C、 應、 HfC、 TiC、 TiN、 TiAl、 MoN、 MoC、 TaTbN、 TaErN、 TaYbN、 TaSiN、 TaAlN、 TiAlN、 TaHf 、 TiHf 、 HfSiN、 MoSiN、 MoAlN、 Mo、 Ru、 Ru02、 RuTax、 NiTax、 多晶硅和金属硅化物， 及其它们的组合。 栅介质层 230和 栅电极 232的沉积可以釆用常规沉积工艺形成，例如溅射、 PLD、 MOCVD、 ALD、 PEALD或其他合适的方法。 而后， 可以通过化学机械抛光 （ CMP ) 方法， 以第二氮化物帽层 208为停止层， 去除所述体引出堆叠 400和绝缘 介电层 216之上的栅介质层 230和栅电极 232 , 从而在开口 218 内形成包 括栅介质层 230和栅电极 232的替代栅堆叠 500 , 如图 5A ( AA'向视图） 、 图 5B ( BB，向视图）所示。 在此步骤， 体引出堆叠 400未有变化， 如图 5C
( C 向视图） 所示。 特别地， 在形成替代栅堆叠 500之后， 在所述源极区和漏极区 214的 半导体衬底 200 上形成源漏金属硅化物层 234 , 以及在所述体引出层 204 上形成体引出金属硅化物层 235 , 如图 6A ( AA'向视图） 、 图 6B ( ΒΒ'向 视图） 及图 6C ( CC，向视图） 所示。 首先， 在绝缘介电层 216上形成第二 层介质层 217 , 所述第二层介质层 217可以是但不限于例如未掺杂的氧化 硅（Si02 ) 、 掺杂的氧化硅 （如硼硅玻璃、 硼磷硅玻璃等） 等。 而后， 进 行选择性蚀刻， 分别在源极区和漏极区 214、 体引出层 204以及栅电极 232 上形成接触孔， 并进行金属硅化， 以形成源漏金属硅化物层 234和体引出 金属硅化物层 235 , 所述金属硅化的材料可以是， 例如 Co、 Ni、 Mo、 Pt 和 W等。
在步骤 105 , 在所述源极区和漏极区 214上形成源漏接触 236 , 在所述 体引出层 204上形成体接触 238以及在替代栅堆叠 500的栅电极 232上形 成栅极接触 240 , 如图 6 (俯视图） 、 图 6A ( ΑΑ'向视图） 、 图 6Β ( BB' 向视图） 以及图 6C ( CC，向视图） 所示。 在所述器件上沉积接触金属材料 填满接触孔， 如 W, 以形成源漏接触 236、 体接触 238以及栅极接触 240。
以上对基于后栅工艺的体接触器件结构及其制造方法进行了描述， 通 过本发明， 在衬底上直接形成体引出层， 且在体引出层之上形成体接触， 这种结构减小了器件面积， 而且能够有效的减小 Τ型栅和 Η型栅结构存在 的寄生效应， 从而提高体接触器件结构的性能。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的 精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变 化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理解在保持 本发明保护范围内的同时， 工艺步骤的次序可以变化。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机 构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域 的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对 应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进 行应用。 因此， 本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种制造体接触器件结构的方法， 所述方法包括：
A. 提供半导体衬底， 所述半导体衬底内有隔离区；
B. 在所述半导体衬底和隔离区上形成伪栅堆叠， 以及在所述伪栅堆叠 侧壁形成侧墙， 以及在所述半导体衬底内形成源极区和漏极区， 并覆盖所 述源极区、 漏极区以及隔离区形成绝缘介电层；
C. 将伪栅堆叠一端去除， 暴露衬底和隔离区以形成开口， 其中伪栅堆 叠未去除部分为体引出堆叠， 所述体引出堆叠包括体引出层， 所述体引出 层直接和衬底接触；
D. 在所述开口内形成替代栅堆叠， 所述替代栅堆叠包括栅介质层和栅 电极；
E. 在所述源极区和漏极区上形成源漏接触， 在所述体引出堆叠中的体 引出层上形成体接触以及在替代栅堆叠的栅电极上形成栅极接触。
2. 根据权利要求 1所述的方法， 其中所述体引出层由半导体或半导体 化合物材料形成， 且釆用与所述衬底不同的材料形成。
3. 根据权利要求 2所述的方法， 其中所述半导体或半导体化合物材料 包括： Ge、 GeSi、 GaAs、 InP、 SiC、 多晶硅和金刚石。
4. 根据权利要求 1所述的方法， 其中所述体引出堆叠还包括第一氧化 物帽层和第二氮化物帽层。
5. 根据权利要求 1所述的方法， 在步骤 D和步骤 E之间还包括： 在 所述源极区、 漏极区的半导体衬底上形成源漏金属硅化物层， 以及在所述 体引出层上形成体引出金属硅化物层。
6. 一种体接触器件结构， 其中所述结构包括：
具有半导体衬底， 其中所述半导体衬底内有隔离区；
在半导体衬底上形成的源极区和漏极区；
形成于所述源极区和漏极区之间的半导体衬底和隔离区上的体引出堆 叠和替代栅堆叠；
其中所述体引出堆叠包括体引出层； 所述替代栅堆叠包括栅介质层和 栅电极；
形成于所述体引出堆叠和替代栅堆叠侧壁的侧墙；
形成于所述源极区和漏极区的源漏接触， 以及体引出层上的体接触， 以及栅电极上的栅极接触。
7. 根据权利要求 6所述的器件结构， 其中所述体引出层由半导体或半 导体化合物材料形成， 且釆用与所述衬底不同的材料形成。
8. 根据权利要求 7所述的方法， 其中所述半导体或半导体化合物材料 包括： Ge、 GeSi、 GaAs、 InP、 SiC、 多晶硅或金刚石。
9. 根据权利要求 6所述的器件结构， 在所述源漏接触与所述源极区和 漏极区所在衬底之间还包括源漏金属硅化物层。
10. 根据权利要求 6所述的器件结构， 在所述体接触与所述体引出层 之间还包括体引出金属硅化物层。
11. 根据权利要求 6所述的器件结构， 其中所述体引出堆叠还包括第 一氧化物帽层和第二氮化物帽层。
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