Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

• the present invention relates to integrated circuit memory devices and, in particular, to an all-NMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
• NVM non-volatile memory
• Fig. 1 as disclosed in U.S. Patent No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells 100 having floating gate electrodes that are commonly-connected to a storage node P s , for each NVM cell in the array that is to be programmed, all of the electrodes of the cell are grounded.
• An inhibiting voltage V n is then applied to the bulk-connected source electrode V r of the cell's read transistor P r , to the commonly-connected drain, bulk region and source electrodes V e of the cell's erase transistor P e , and to the drain electrode D r of the read transistor P r .
• the source electrode V p and the drain electrode D p of the cell's programming transistor P w are grounded.
• the voltage applied to the bulk region electrode V nw of the programming transistor P w is optional; it can be grounded or it can remain at the inhibiting voltage V n .
• the inhibiting voltage V n is applied to the V r , V e and D r electrodes and is also applied to the V p , D p and V nw electrodes.
• the control voltage V c of the cell's control transistor P c is then swept from 0V to a maximum programming voltage V cmax in a programming time T prog .
• the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of the all-PMOS NVM cell and the drain, source and bulk region electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
• U.S. Patent No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
• the all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells in a cell array without the need for high current power sources, and a simple program sequence.
• the 4-transistor PMOS NVM cell cannot be used in certain integrated circuit fabrication processes wherein n- epitaxial silicon is grown that shorts all N-wells together or where each N-well needs to be surrounded by an individual N+, P+, or trench guard ring and charge will be lost if the floating polysilicon gate crosses the guard ring.
• the present invention provides a method of programming a non-volatile (NVM) memory cell array that includes a plurality of all-NMOS 4-transistor NVM cells.
• Each all-NMOS NVM cell in the NVM cell array includes a first NMOS programming transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to a common storage node, a second NMOS read transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to the common storage node, a third NMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, and a fourth NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the common storage node.
• the programming method comprises: for each NVM cell in the array, setting the source, drain and bulk region electrodes and the gate electrodes of the first, second, third and fourth NMOS transistors to a positive reference voltage; for each NVM cell in the array selected for programming, applying an inhibiting voltage to the source, drain and bulk region electrodes of the second NMOS read transistor while setting the source and drain electrodes of the first NMOS programming transistor to the positive reference voltage and maintaining the bulk region electrode of the first NMOS programming transistor at either the positive reference voltage or at the inhibiting voltage; for each NVM cell in the NVM cell array not selected for programming, setting the source, drain and bulk region electrodes of the second NMOS read transistor and of the first NMOS programming transistor to the inhibiting voltage; for each NVM cell in the array selected for programming, ramping down the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the positive reference voltage to a minimum control voltage for a preselected programming time while ramping down the interconnected source, drain and bulk region electrodes of the third
• Fig. 1 is a schematic diagram illustrating an all-PMOS 4-transistor NVM cell.
• Fig. 2 is a schematic diagram illustrating an embodiment of an all-NMOS 4- transistor NVM cell in accordance with the concepts of the present invention.
• Fig. 3 is a schematic diagram illustrating an embodiment of the Fig. 2 NVM cell adapted for incorporation into an NVM cell array.
• Fig. 3 A is a schematic diagram illustrating an alternate embodiment of the Fig. 2 NVM cell adapted for incorporation into an NVM cell array.
• Fig. 4 is a schematic diagram illustrating an embodiment of an NVM cell array that includes a plurality of adapted NVM cells of the type shown in Figs. 3 and 3 A.
• Fig. 5 is a cross-section drawing illustrating the Fig. 1 all-PMOS 4-transistor NVM cell.
• Fig. 6 is a cross-section drawing illustrating the Fig. 2 embodiment of an all- NMOS NVM cell in accordance with concepts of the present invention.
• Fig. 2 shows an all-NMOS 4-transistor non-volatile memory (NVM) cell 200 that includes four NMOS transistors connected to a common storage node N s . As described in greater detail below, one NMOS transistor is provided for each of the four NVM cell functions: program (or write), read, erase and control.
• NVM non-volatile memory
• the programming function of the NVM cell 200 is controlled by a first NMOS programming transistor N w having a source electrode that receives a source programming voltage V p , a drain electrode that receives a drain programming voltage D p and a bulk region electrode that receives a bulk programming voltage V pwp .
• the gate electrode of programming transistor N w is connected to the common storage node N s .
• the read function of the NVM cell 200 is controlled by a second NMOS read transistor N r having a source electrode that receives a source read voltage V r , a drain electrode that receives a drain read voltage D r and a bulk region electrode that receives a bulk read voltage V pwr .
• the gate electrode of the read transistor N r is connected to the common storage node N s .
• the erase function of the NVM cell 200 is controlled by a third NMOS erase transistor N e having interconnected source, drain and bulk region electrodes to which an erase voltage V e is applied.
• the gate electrode of the erase transistor N e is connected to the common storage node N s .
• the control function of the NVM cell 200 is controlled by a fourth NMOS control transistor N c having interconnected source, drain and bulk region electrodes to which a control voltage V c is applied.
• the gate electrode of the control transistor N c is connected to the common storage node N s .
• the above-referenced '606 patent describes in detail how the reverse Fowler- Nordheim tunneling programming technique works for the all-PMOS 4-transistor NVM cell and the sequences for program, erase and read operations.
• the program, erase and read operations for the all-NMOS 4-transistor NVM cell 200 of the present invention are complimentary to those operations for the all-PMOS cell. That is, the program, erase and read sequences are the same with different polarity for voltages.
• the circuit reference voltage is 0V; for the all-NMOS cell, the reference voltage is positive (VQD)-
• the inhibiting voltage V n is a positive voltage; in the case of the all-NMOS cell, the inhibiting voltage V n is 0V.
• the control voltage V c and the erase voltage V e are positive voltages V cmax and V ema x, respectively; for the all-NMOS cell, the control voltage V c and the erase voltage V e are negative voltages V cm j n and V em in, respectively.
• the source, drain, bulk region and gate electrodes of the first NMOS programming transistor N w , the second NMOS read transistor N r , the third NMOS erase transistor N e and the fourth NMOS control transistor N c are all initially set to the positive reference voltage VDD-
• the inhibiting voltage V N (0V) is applied to the source, drain and bulk region electrodes of the second NMOS read transistor N r while setting the source and drain electrodes of the first NMOS programming transistor N w to the positive reference voltage V DD and maintaining the bulk region electrode of the first NMOS programming transistor N w at the positive reference voltage V DD or the inhibiting voltage V n (0V).
• the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor N c are then ramped down from the positive reference voltage VDD to a minimum negative control voltage V cm j n for a programming time T pro g while ramping down the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor N e from the positive reference voltage VDD to a minimum negative erase voltage V e min for the programming time T prog .
• the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor N c are ramped up from the minimum negative control voltage V cm i n to the positive reference voltage while ramping up the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor N e from the minimum negative erase voltage Vemin to the positive reference voltage VDD-
• the source, drain and bulk region electrodes of the first, third and fourth NMOS transistors are then returned to the positive reference voltage VDD while setting the source, drain and bulk region electrodes of the second NMOS read transistor N r to the inhibiting voltage V render (0V).
• Fig. 3 shows the all-NMOS 4-transistor NMV cell 200 adapted to include additional N-channel pass transistors Nl and N2 for facilitating use of the NVM cell 200 within an NVM cell array.
• N-channel pass transistor Nl is used by placing logic hi on read word line node RWL and sensing current on read bit line node RBL.
• N-channel pass transistor N2 is used by placing logic hi on program word line node PWL and logic hi on program bit line node PBL to get logic hi on the programming transistor source node V p of the cell to be programmed (or by placing logic low on node PBL to get logic low on the source node V p to keep the cell at the erase stage).
• the dashed circles in Fig. 3 show a possible alternate implementation of the programming transistor N p with interconnected source, drain and bulk region electrodes utilizing a programming transistor N p with interconnected source and drain electrodes and a bulk region electrode that can be set to either the positive reference voltage VDD or the inhibiting voltage 0V.
• Fig. 3A shows an alternate embodiment of the Fig. 3 adapted NVM cell. All aspects of the Fig. 3A adapted cell are the same as those of the Fig. 3 adapted cell except for the configuration of the programming transistor N w .
• Fig. 3A shows a programming transistor N w having a source electrode and commonly-connected drain and bulk region electrodes and a gate electrode connected to the common storage node N s .
• the dashed circles in Fig. 3A show another possible alternate embodiment in which the programming transistor N w having independent source, drain and bulk region electrodes and a gate electrode connected to the common storage node N s .
• V P V DD
• D P V DD
• V PWP V DD (Fig. 3)
• V P V DD
• D P V D D
• V PVVP V SS (Fig. 3 alternate)
• V P V DD
• D P floating
• V PWP VDD (Fig. 3A)
• V P VDD
• D p floating
• V PWP V SS (Fig. 3 A alternate)
• V P V D D
• D p floating are equal to V P floating
• D P V DD from a functionality point of view.
• Fig. 4 shows a plurality of NVM cells 200, which may be of the type shown in Figs. 3 and 3A, incorporated into an NVM cell array 400.
• the erase voltage V e and the control voltage V c are applied directly to each NVM cell in the array 500. With no high voltage switches or other supporting circuitry, significantly simplified connection can be made from the array 500 to external or internal voltage and signal sources and to signal destinations.
• the program voltage V p is delivered to each cell individually through N-channel pass transistor N2 (Figs. 3, 3A) to program the cell or to keep it at the erase stage.
• the corresponding program bit line e.g., PBL(0)
• the corresponding program bit line PBL will be at logic high; to keep the remaining cells in the array 500 at the erase state, the corresponding program bit line PBL will be at logic low.
• both the control voltage V c and the erase voltage V e are applied to all cells in the array 400, while the rest of the signal lines are set at the positive reference voltage VDD-
• all program word lines (PWL) in the array 400 are at logic low, one of the read word lines, e.g., RWL(0), will be at logic hi, while the remaining read word lines RWL(0) - RWL(N-1) in the array 400 will be at logic low.
• RWL(0) - RWL(M-l) On each of the read bit lines RBL(0) - RBL(M-l), a high current or voltage will be received for each corresponding cell in the array that had been programmed, while a low current or voltage will be received for each corresponding cell that had been erased.
• VDD positive reference voltage
• Fig. 5 and Fig. 6 show, respectively, cross-sections of the Fig. 1 all-PMOS 4- transistor NVM cell and the Fig. 2 all-NMOS NVM cell.
• the all- NMOS NVM cell utilizes an isolated P-well (PWELL). This results in smaller cell area compared to the all-PMOS cell because the spacing between the separated P-wells (which represent minimum N-well width) is smaller than the spacing between the separated N- wells in a P-substrate.

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• 2010
  • 2010-02-02 US US12/698,318 patent/US8363469B1/en active Active
  • 2010-11-29 WO PCT/US2010/058203 patent/WO2011096977A2/en not_active Ceased
  • 2010-11-29 CN CN201080062922.5A patent/CN102741825B/zh active Active
  • 2010-11-29 JP JP2012551964A patent/JP5649664B2/ja active Active
  • 2010-12-22 TW TW099145116A patent/TWI449047B/zh active

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