WO2011077608A1 - Dispositif semi-conducteur, circuit intégré à haute fréquence, système de communication sans fil à haute fréquence, et processus de production du dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur, circuit intégré à haute fréquence, système de communication sans fil à haute fréquence, et processus de production du dispositif semi-conducteur Download PDF

Info

Publication number
WO2011077608A1
WO2011077608A1 PCT/JP2010/005221 JP2010005221W WO2011077608A1 WO 2011077608 A1 WO2011077608 A1 WO 2011077608A1 JP 2010005221 W JP2010005221 W JP 2010005221W WO 2011077608 A1 WO2011077608 A1 WO 2011077608A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
semiconductor device
plane
sapphire
Prior art date
Application number
PCT/JP2010/005221
Other languages
English (en)
Japanese (ja)
Inventor
隆弘 横山
修 石川
順治 伊藤
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2011077608A1 publication Critical patent/WO2011077608A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H01L29/78657—SOS transistors

Definitions

  • the present invention relates to a semiconductor device using an insulating sapphire substrate, a high-frequency integrated circuit, a high-frequency wireless communication system, and a semiconductor device manufacturing method, and particularly to a silicon (Si) semiconductor device for high-frequency applications.
  • a Si substrate used in many semiconductor devices is generally created by a pulling method (Czochralski method; CZ method).
  • Czochralski method CZ method
  • the resistivity of a commonly used Si substrate is several ⁇ cm, and there are many conductive carriers in the substrate.
  • passive elements such as transistors and capacitors / inductors are created on a substrate with such a low resistivity and used for high-frequency applications, part of the high-frequency input signal moves the carriers in the Si substrate to the substrate. It escapes and input energy loss occurs. Therefore, Si semiconductor devices have been considered unsuitable for high frequency applications.
  • GaAs gallium arsenide
  • MOSFET MOS field effect transistor
  • the resistivity of the Si substrate is required to be 2500 ( ⁇ cm) or more (for example, see Non-Patent Document 1).
  • the resistivity of the Si substrate is required to be 2500 ( ⁇ cm) or more (for example, see Non-Patent Document 1).
  • SOI silicon on insulator
  • Patent Documents 3 and 4 Non-Patent Documents 2 to 4
  • SOS silicon-on-sapphire
  • an insulating substrate instead of Si for example, a sapphire substrate
  • a bonding method of directly bonding substrates together is used (for example, Non-Patent Document 5).
  • the method of increasing the resistance of the Si substrate for example, if a floating zone melting method (FZ method) is used, high-purity Si can be grown, and a high-resistance Si substrate of the order of 10 5 ( ⁇ cm) is obtained.
  • FZ method floating zone melting method
  • oxygen is melted into Si from the quartz crucible to be used, and it is difficult to increase the resistance.
  • Various methods have been proposed for increasing the resistance by reducing the oxygen concentration in the CZ method, but generally there is a limit to reducing oxygen, and the oxygen content is 6 ⁇ 10 17 (atoms / cm 3 ). It is difficult to make it below, the mechanical strength decreases due to low oxygen, slip lines are likely to occur, and further, the resistivity of the Si substrate obtained by these tends to fluctuate due to heat treatment. There are a number of issues.
  • the resistivity at the practical level at present is a level of about 1000 ( ⁇ cm) at the maximum, and a high resistance Si substrate of 2000 ( ⁇ cm) or more has not yet been supplied to the market at a low cost. It is.
  • the SOI technology is an SOI substrate composed of three layers in which a relatively thick silicon oxide (SiO 2 ) layer called a BOX (Buried Oxide Layer) layer and a Si single crystal layer are further stacked on the Si substrate. Is a technology to form
  • the BOX layer is formed by ion implantation of oxygen at a high dose.
  • the BOX layer that is an insulating layer is under the Si layer that is the operation layer, the device on the SOI substrate has improved high-frequency characteristics compared to the device on the normal Si substrate.
  • the thickness of the BOX layer is at most several ⁇ m, and the high frequency input loss in the Si substrate having a low resistivity under the BOX layer cannot be ignored, and the high frequency characteristics equivalent to the SOS substrate by GaAs or SOS technology cannot be obtained. Is real.
  • the SOS technology has been activated starting from a method of growing a Si single crystal on sapphire. Since the resistivity of sapphire has an extremely high resistivity of 10 14 ⁇ ⁇ cm or more, the SOS technique is effective for realizing a high resistance of the substrate.
  • sapphire has a hexagonal crystal structure having aluminum (Al) atoms and oxygen (O) atoms, more precisely, a unit of the trigonal crystal structure (rhombohedral structure) shown in FIG. It has a crystal structure consisting of three cells. Further, as shown by the one-dot chain line in FIG. 10, the hexagonal planes that are diagonally cut diagonally are r planes, and the hexagonal planes are located on the upper and lower planes of the hexagonal crystals as shown by the thick lines in FIG. Is called the c-plane.
  • the r-plane here is based on the notation of the new standard SEMI M65-0306E2 (revised in February 2006) of the international standard (SEMI Standard) for sapphire substrates, and is the R-plane before revision (- 1012) refers to the surface.
  • the c-plane refers to the (0001) plane that is the C-plane before revision.
  • these planes are referred to as r-plane and c-plane according to the revised standard notation.
  • 12A and 12B are diagrams showing the arrangement of an Al lattice on the r plane and an O lattice on the r plane, respectively.
  • the in-wafer uniformity of the MOSFET threshold value (Vt) is excellent. hard.
  • the device formed on the SOS substrate has a limited application range such as an RF switch having a wide tolerance with respect to Vt, and is not applicable to a wider application range such as a power amplifier with a small Vt tolerance. It is in a difficult state.
  • the r-plane of sapphire is more anisotropic than the c-plane, as shown in FIGS. 12A and 12B.
  • Al on the r-plane is arranged in a substantially square lattice pattern and the anisotropy is small.
  • O on the r-plane is an array of O arranged in a zigzag pattern. The lattice pattern appears repeatedly, and the O lattice is clearly highly anisotropic.
  • anisotropy of the O lattice for example, when a device such as a transistor is formed on an SOS substrate using the r-plane of sapphire, anisotropy appears in the thermal expansion coefficient and thermal conductivity coefficient.
  • the thermal expansion coefficient is different between Si and sapphire.
  • the thermal expansion coefficient of Si is 2.55 ⁇ 10 ⁇ 6 (K ⁇ 1 ), and that of sapphire is 7.7 ⁇ 10 ⁇ 6 (K ⁇ 1). ; Parallel to the c-plane), but these physical properties depend on the crystal orientation.
  • This difference causes warpage of the SOS substrate during the wafer process.
  • device characteristics such as a threshold value (Vt) of a transistor formed as a device change due to internal stress generated by warping of the SOS substrate. If anisotropy appears in the thermal expansion coefficient, anisotropy also occurs in the amount of warpage, so that location dependence and direction dependence appear in device characteristics, and uniformity in the wafer surface is impaired. Therefore, in the SOS substrate in which the Si layer is formed on the r-plane of sapphire, as described above, the in-plane uniformity of device characteristics may be reduced due to the anisotropy of the SOS substrate.
  • the present invention has been made in view of the above problems, and an object thereof is to reduce the anisotropy of the SOS substrate and improve the in-plane uniformity of the device characteristics of the semiconductor device.
  • a semiconductor device is a semiconductor device having a Si layer on a main surface of an insulator substrate, wherein the insulator substrate is a sapphire substrate, and the main surface of the insulator substrate. Is the c-plane.
  • the Si layer is formed on the c-plane with little anisotropy in the sapphire substrate, the in-plane uniformity of the device characteristics of the semiconductor device formed on the Si layer can be improved.
  • the sapphire substrate can be obtained at a lower cost than the r-plane, and the optical device and the electronic device can be formed in the same substrate. Therefore, cost reduction of the Si high frequency device can be realized.
  • the Si layer may be directly bonded to the main surface of the insulator substrate.
  • a Si layer (also referred to as a Si substrate in the manufacturing process) is directly bonded to the main surface of the sapphire substrate by a bonding method in which surfaces with high flatness are directly bonded without using an adhesive or the like. Therefore, even if the sapphire substrate and the Si layer have different lattice constants of the crystal lattice, the sapphire substrate and the Si layer can be joined (see Non-Patent Document 5).
  • the main surface of the sapphire substrate on which the Si layer is formed is limited to the r-plane having a lattice constant close to that of Si, but according to this bonding method, it is limited to the r-plane. There is nothing. That is, the Si layer can be formed on the c-plane of the sapphire substrate with little anisotropy. Therefore, a Si layer with improved in-plane uniformity can be formed.
  • the Si layer may have a SiO 2 layer on a joint surface with the insulator substrate.
  • an SiO 2 layer is a buffer layer, lattice between the sapphire substrate and the Si layer Since the difference in constant is buffered, the sapphire substrate and the Si layer are more strongly bonded.
  • the Si layer may have a transistor which is an active element on a surface opposite to the bonding surface with the insulator substrate.
  • the transistor may be a MOS field effect transistor.
  • the transistor may be a bipolar transistor.
  • the Si layer may have at least one of a capacitor and an inductor that are passive elements on a surface opposite to the bonding surface with the insulator substrate.
  • a high-frequency integrated circuit includes the semiconductor device according to any one of claims 4 to 6 and the semiconductor device according to claim 7.
  • the high-frequency integrated circuit is configured using the above-described device, the in-plane uniformity of device characteristics is improved. Therefore, the yield of the integrated circuit can be improved and the cost of the integrated circuit can be reduced.
  • a high-frequency wireless communication system includes the above-described high-frequency integrated circuit at least in a front-end unit that is a transmission / reception end.
  • the high-frequency wireless communication system is configured using the above-described high-frequency integrated circuit in at least a part of the entire system, so that the stability of the high-frequency wireless communication system is improved and the cost of the system is reduced. it can.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a Si layer on a main surface of an insulator substrate.
  • the Si substrate is directly bonded to the main surface of the sapphire substrate by a bonding method in which surfaces having high flatness are directly bonded to each other without using an adhesive or the like, the lattice constants of the crystal lattices are different. Even if it is a sapphire substrate and a Si substrate, a sapphire substrate and a Si substrate can be joined.
  • the main surface of the sapphire substrate on which the Si layer is formed is limited to the r-plane having a lattice constant close to that of Si, but according to this bonding method, it is limited to the r-plane. There is nothing. That is, the Si layer can be formed on the c-plane of the sapphire substrate with little anisotropy. Therefore, the in-plane uniformity of the device characteristics of the semiconductor device formed on the Si layer can be improved.
  • the sapphire substrate can be obtained at a lower cost than the r-plane, and the optical device and the electronic device can be formed in the same substrate. Therefore, cost reduction of the Si high frequency device can be realized.
  • the method further includes forming a SiO 2 layer on a bonding surface of the Si substrate to the insulator substrate before the Si substrate is bonded to the principal surface of the insulator substrate.
  • the SiO 2 layer may be directly bonded to the substrate.
  • the SiO 2 layer is formed on the main surface of the Si substrate, that is, the joint surface with the sapphire substrate, the SiO 2 layer becomes a buffer layer at the joint surface between the sapphire substrate and the Si substrate, and the sapphire substrate Since the difference in lattice constant between the Si substrate and the Si substrate is buffered, the sapphire substrate and the Si substrate are more strongly bonded.
  • the Si substrate after bonding the sapphire substrate and the Si substrate, the Si substrate can be easily made thin.
  • a step of cleaning the main surface of the insulator substrate and the bonding surface of the Si substrate with the insulator substrate may be further included.
  • the anisotropy of the SOS substrate can be reduced and the in-plane uniformity of the device characteristics of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 2A is a cross-sectional view illustrating a manufacturing process of the SOS substrate in the semiconductor device of FIG. 2B is a cross-sectional view illustrating a process for manufacturing the SOS substrate in the semiconductor device of FIG.
  • FIG. 2C is a cross-sectional view illustrating a manufacturing process of the SOS substrate in the semiconductor device of FIG.
  • FIG. 2D is a cross-sectional view illustrating a manufacturing process of the SOS substrate in the semiconductor device of FIG.
  • FIG. 2E is a cross-sectional view illustrating a manufacturing process of the SOS substrate in the semiconductor device of FIG. FIG.
  • 3A is a diagram illustrating the lattice state of Al on the c-plane of sapphire.
  • FIG. 3B is a diagram for explaining the lattice state of O on the c-plane of sapphire.
  • 4A is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a MOSFET according to Embodiment 2.
  • FIG. 4B is a cross-sectional view illustrating a manufacturing process of the semiconductor device having a MOSFET in the second embodiment.
  • FIG. 4C is a cross-sectional view illustrating a manufacturing step of the semiconductor device having a MOSFET in the second embodiment.
  • FIG. 5A is a cross-sectional view illustrating a manufacturing process of a semiconductor device having a bipolar transistor in the third embodiment.
  • FIG. 5B is a cross-sectional view illustrating a manufacturing step of the semiconductor device having the bipolar transistor in the third embodiment.
  • FIG. 5C is a cross-sectional view illustrating a manufacturing step of the semiconductor device having the bipolar transistor in Embodiment 3.
  • FIG. 5D is a cross-sectional view illustrating a manufacturing step of the semiconductor device having the bipolar transistor in the third embodiment.
  • FIG. 5E is a cross-sectional view illustrating a manufacturing step of the semiconductor device having the bipolar transistor in the third embodiment.
  • FIG. 6 is a conceptual diagram of a semiconductor device having a capacitor and an inductor according to the fourth embodiment.
  • FIG. 7 is a conceptual circuit diagram of the high-frequency amplifier according to the fifth embodiment.
  • FIG. 8 is a circuit block diagram of the high-frequency wireless communication front-end unit in the sixth embodiment.
  • FIG. 9 is a schematic diagram of a mobile phone that is a high-frequency wireless communication system according to the sixth embodiment.
  • FIG. 10 is a diagram for explaining the crystal structure of sapphire and its plane orientation.
  • FIG. 11 is a diagram for explaining a rhombohedral structure, which is a unit cell having a sapphire crystal structure, and an arrangement structure of Al and O therein.
  • FIG. 12A is a diagram for explaining the difference in lattice constant between Al on the r-plane of sapphire and the Si (100) lattice.
  • FIG. 12B is a diagram for explaining the lattice state of O on the r-plane of sapphire.
  • Embodiment 1 A configuration of the semiconductor device according to the first embodiment of the present invention will be described.
  • a semiconductor device having a Si layer on a main surface of an insulator substrate, a semiconductor device in which the insulator substrate is a sapphire substrate and the main surface of the insulator substrate is a c-plane will be described.
  • the in-plane uniformity of the device characteristics of the semiconductor device formed on the Si layer can be improved.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 10 according to the present embodiment.
  • the semiconductor device 10 includes a sapphire substrate 101, a SOS substrate 106 composed of a SiO 2 layer 103 and a Si layer 102, and a device 109.
  • the SiO 2 layer 103 and the Si layer 102 correspond to the Si substrate 100 in the present embodiment.
  • the size of the SOS substrate 106 is, for example, the size of a 6-inch wafer having a thickness of about 650 ⁇ m as viewed from above, the thickness of the SiO 2 layer 103 is about 200 nm, and the thickness of the Si layer 102 is 400 nm. It is formed to the extent.
  • passive elements, active elements and the like manufactured in advance in separate processes may be arranged on the SOS substrate 106, or may be formed by processing the Si layer 102 (102c) on the SOS substrate 106. .
  • 2A to 2E are diagrams for explaining the manufacturing process of the SOS substrate 106 in the embodiment of the present invention.
  • 3A and 3B show an aluminum (Al) lattice on the c-plane and an oxygen (O) lattice on the r-plane of the sapphire substrate 101, respectively.
  • the manufacturing process of the SOS substrate 106 is as follows. First, as shown in FIG. 2A (a), the sapphire substrate 101 has a c-plane main surface, and as shown in FIG. 2B, the main surface is (100) and the dopant concentration is 5 ⁇ 10 17 cm ⁇ 3 . A p-type Si substrate 100 is prepared.
  • the crystal structure of the Si substrate 100 is a simple diamond structure and has high crystal symmetry.
  • the crystal structure of the sapphire substrate 101 is composed of two elements of Al and O as described above.
  • the crystal structure of the sapphire substrate 101 is a hexagonal crystal structure in which Al and O are intricately interlaced as shown in FIG. Specifically, it has a rhombohedral structure (corundum structure) as shown in FIG. 11, has low crystal symmetry, and high physical property anisotropy.
  • 3A and 3B show an Al lattice on the c-plane of the sapphire substrate 101 and an O lattice on the c-plane, respectively.
  • Al and O on the c-plane are in a state where the hexagonal crystal structure shown in FIG. 9 is viewed from above, and Al is arranged in a hexagonal shape as shown in FIG. 3A.
  • O on the c-plane is slightly unequal, but is generally arranged in a hexagonal shape, and is less anisotropic than the lattice of O on the r-plane shown in FIG. 12B.
  • the in-plane anisotropy of the thermal expansion coefficient and the thermal conductivity coefficient is small.
  • the sapphire substrate 101 and the Si substrate 100 are, for example, in the shape of a 6-inch wafer having a thickness of about 600 to 700 ⁇ m and are prepared with the same diameter for bonding in a later step.
  • the sizes of the sapphire substrate 101 and the Si substrate 100 are not limited to 6 inches as long as they have the same diameter, and may be, for example, 8 inches or other sizes. Further, the shape may be other than the wafer shape.
  • the Si substrate 100 includes the unoxidized Si layer 102 and the SiO 2 layer 103.
  • hydrogen (H) ions are implanted into the Si layer 102 through the SiO 2 layer 103 at an acceleration voltage of 80 keV and a dose amount of 1 ⁇ 10 17 cm ⁇ 2 , and about 400 nm from the surface of the Si layer 102.
  • a cleavage layer 102b is formed by H ion implantation (600 nm from the surface of the SiO 2 layer 103).
  • the Si layer 102 has a structure including the divided Si layer 102a, the cleaved layer 102b, the divided Si layer 102c, and the SiO 2 layer 103.
  • the main surface of the sapphire substrate 101 by eliminating fouling of the surface of the main surface, that the SiO 2 layer 103 of the Si substrate 100 in order to improve the flatness, surface cleaning of the sapphire substrate 101 and the SiO 2 layer 103 I do.
  • the surface cleaning method is performed by wet processing usually used in the Si wafer process or plasma processing in vacuum. This surface cleaning step may be omitted depending on the surface state of the sapphire substrate 101 or the SiO 2 layer 103.
  • the sapphire substrate 101 and the Si layer 102 are bonded using the SiO 2 layer 103 as a bonding surface.
  • 2C shows the bonded substrate 105 after the Si substrate 100 shown in FIG. 2C is turned upside down and the SiO 2 layer 103 of the Si substrate 100 is bonded to the main surface of the sapphire substrate 101 shown in FIG. 2A. .
  • the sapphire substrate 101 and the Si substrate 100 are bonded by a bonding method in which the substrates are directly bonded to each other.
  • the sapphire substrate 101 and the Si substrate 100 have different lattice constants of crystal lattices, but the main surface of the sapphire substrate 101 and the main surface of the Si substrate 100 are improved in flatness by the above-described surface cleaning, and bonded. Since the surface molecules are activated, the bonding between the bonding surface molecules is strengthened, and the sapphire substrate 101 and the Si substrate 100 are bonded. Therefore, the sapphire substrate 101 and the Si substrate 100 are joined without causing crystal lattice distortion or crystal defects.
  • the bonding surface of the sapphire substrate 101 of Si substrate 100 SiO 2 layer 103 Since the bonding surface of the sapphire substrate 101 of Si substrate 100 SiO 2 layer 103 is formed, the bonding surface of the sapphire substrate 101 and the Si substrate 100, SiO 2 layer 103 serves as a buffer layer, a sapphire substrate Since the difference in lattice constant between 101 and the Si layer 102 is buffered, the sapphire substrate 101 and the Si substrate 100 are more strongly bonded.
  • the bonded substrate 105 is put into a high temperature furnace and heat treatment is performed at 400 ° C. to 600 ° C.
  • heat treatment gas is generated in the cleavage layer 102b by H ions implanted in the cleavage layer 102b.
  • the generated gas is thermally expanded to form microbubbles, and these further grow, whereby the Si—Si interatomic bond between the divided Si layer 102a and the divided Si layer 102c is cut off.
  • the Si layer 102 is cleaved at the cleavage layer 102b, and is divided into the divided Si layer 102a and the divided Si layer 102c.
  • the bonded substrate 105 is divided into a desired SOS substrate 106 and a divided Si layer 102a.
  • the SOS substrate 106 includes the sapphire substrate 101, the SiO 2 layer 103, and the divided Si layer 102c having a thickness of 400 nm.
  • the surface of the divided Si layer 102c of the SOS substrate 106 immediately after the division has considerable unevenness at the atomic level, the surface is smoothed by surface polishing.
  • a MOSFET is formed as the device 109 on the divided Si layer 102c of the SOS substrate 106 by a normal Si wafer process, and the semiconductor device 10 having the device 109 on the SOS substrate 106 shown in FIG. 1 is completed. To do.
  • the divided Si layer 102c on the sapphire substrate 101 is formed by directly bonding to the sapphire substrate 101 not by epitaxial growth but by the bonding method as described above. Therefore, even if there is a large difference in lattice constant between the sapphire substrate 101 and the Si substrate 100, the sapphire substrate 101 and the Si substrate 100 can be bonded.
  • the crystallinity of the original Si layer 102 is maintained.
  • the density of Si crystal defects is much smaller than that of the conventional SOS technology (see Patent Document 2), variations in characteristics of the device 109 formed in the divided Si layer 102c, for example, variations in the threshold value (Vt) of the transistor Can be reduced.
  • the semiconductor device according to the present invention has a thermal resistance higher than that of a device formed on an r-plane sapphire substrate.
  • the anisotropy of the expansion coefficient and thermal conductivity is also reduced, and the warpage of the wafer can be reduced.
  • a sapphire substrate having a c-plane main surface is widely used in optical devices.
  • the specifications of the sapphire substrate and the optical device using the c-plane are common. Therefore, the optical device and the electronic device can be formed in the same substrate.
  • the sapphire substrate can be obtained at a lower cost than in the case of the conventional SOS technology using r-plane sapphire, the cost of the semiconductor device can be reduced. As a result, a semiconductor device using the SOS technology can be realized at a lower cost than in the past.
  • the resistivity of the sapphire substrate has an extremely high resistivity of 10 14 ⁇ ⁇ cm or more, when a high frequency device is formed on the above SOS substrate, excellent high frequency characteristics can be realized.
  • FIGS. 4A to 4C are cross-sectional views illustrating a manufacturing process for forming a MOS field effect transistor (MOSFET) 200 on the SOS substrate 106 in the semiconductor device according to the present embodiment.
  • a method for forming the MOSFET 200 on the SOS substrate 106 is as follows.
  • the surface of the divided Si layer 102c of the SOS substrate 106 manufactured by the method described in Embodiment 1 is oxidized to create a sacrificial oxide film layer 201, and the oxidized Si layer 102
  • the thickness of (102c) is set to about 50 nm.
  • a sacrificial oxide film layer 201 is formed in a predetermined pattern. That is, the sacrificial oxide film layer 201 is removed by, for example, etching while leaving a part where the gate region of the transistor is formed.
  • a 5 nm thick gate oxide film 204 and a polysilicon gate 205 are formed in this order.
  • the channel doping layer 203 is activated by heat treatment at 1000 ° C. for 10 minutes.
  • Ar + ions are implanted at an acceleration voltage of 50 keV and a dose of 2.0 ⁇ 10 14 cm ⁇ 2 . Further, a sidewall 206 of the gate electrode is formed.
  • P ions having an acceleration voltage of 15 keV and a dose of 5.0 ⁇ 10 15 cm ⁇ 2 are ion-implanted to form a source / drain implantation layer 207.
  • These implanted regions are activated by heat treatment at 1000 ° C. for 20 seconds at rapid thermal annealing (RTA).
  • cobalt (Co) is deposited on the drain injection layer 207 and the polysilicon gate 205 by a sputtering method, and then heat treatment is performed to form a cobalt salicide low resistance layer 208. Further, the source electrode 209, the gate electrode 210, and the drain electrode 211 are patterned on the cobalt salicide low resistance layer 208 to complete a semiconductor device having the n-type MOSFET 200.
  • the thickness of the Si layer 102 (102c) is 50 nm. Further, the Si layer 102 (102c) under the gate is completely depleted by the potential of the gate electrode 210 and the potential on the sapphire substrate 101 side, and the number of electrons which are majority carriers is small, so that excellent high frequency characteristics can be secured. ing. Since the thickness of the Si layer 102 (102c) under the gate depends on the thickness of the gate oxide film 204 and the potential condition on the sapphire substrate 101 side, the thickness cannot be generally specified, but is thicker than 50 nm, for example, 100 nm. As a result, the Si layer 102 (102c) is not completely depleted, leaving a neutral region (so-called partially depleted state), and electrons as majority carriers are present in the Si layer 102 (102c).
  • the high-frequency input signal moves to the majority carrier and leaks to the sapphire substrate 101 side, and an input signal loss occurs to impair the high-frequency characteristics.
  • the reason why the thickness of the Si layer 102 (102c) is reduced to about 50 nm is to achieve a completely depleted state.
  • the c-plane of the sapphire substrate 101 is used, and therefore compared with the conventional MOSFET on the r-plane for the same reason as described in the first embodiment.
  • the in-plane uniformity of the device characteristics of the MOSFET 200 is improved. Therefore, similarly to the first embodiment, it is possible to realize cost reduction and excellent high-frequency characteristics as compared with a semiconductor device having a MOSFET formed on the r-plane.
  • FIGS. 5A to 5E are cross-sectional views illustrating a manufacturing process for forming a bipolar transistor (BJT) 300 on the SOS substrate 106 in the semiconductor device according to the present embodiment.
  • a method for forming the BJT 300 on the SOS substrate 106 is as follows.
  • the surface of the Si layer 102 (102c) of the SOS substrate 106 manufactured by the method described in the first embodiment is oxidized to form a sacrificial oxide film layer 201, and the oxidized Si layer
  • the sacrificial oxide film layer 201 and the Si layer 102 (102c) are removed by etching until the SiO 2 layer 103 is reached, leaving a predetermined BJT region 301, leaving the thickness of the layer 102 (102c) at about 200 nm.
  • the Si layer 102 (102c) has an acceleration voltage of 50 keV, a dose amount of 2.0 ⁇ 10 11 cm ⁇ 2, an acceleration voltage of 140 keV, and a dose amount of 4.0 ⁇ 10 12 cm ⁇ 2 .
  • Ions are implanted to form an n-type collector layer 302.
  • BF 2 having an acceleration voltage of 35 keV and a dose of 8.0 ⁇ 10 15 cm ⁇ 2 is ion-implanted as shown in FIG. 5D. Then, the high concentration p-type base contact layer 304 is formed.
  • the polysilicon layer 303 and the Si layer 102 (102c) are etched away from the surface of the polysilicon layer 303 to the middle of the Si layer 102 (102c), leaving only a predetermined region of the high-concentration base contact.
  • B ions having an acceleration voltage of 35 keV and a dose of 8.0 ⁇ 10 13 cm ⁇ 2 are ion-implanted from the oblique direction 309 shown in FIG. 5D to form the base layer 305.
  • n-type emitter layer 307 is formed by As ion implantation with an acceleration voltage of 40 keV and a dose of 1.0 ⁇ 10 15 cm ⁇ 2 , and an acceleration voltage of 90 keV and a dose of 5.0 ⁇ 10 15.
  • the collector layer 308 is formed by cm ⁇ 2 P ion implantation.
  • heat treatment is performed by a rapid thermal annealing method (RTA) at 950 ° C. for 20 seconds to activate these ion implantation regions.
  • RTA rapid thermal annealing method
  • the structure immediately below the BJT is designed to be the SiO 2 layer 103 of the SOS substrate 106, and the Si layer 102 (102c) is not left below the BJT 300. This is because, as described in the second embodiment, if the Si layer 102 (102c) in the neutral region exists under the transistor, a part of the high frequency input leaks to that portion and the high frequency characteristics are impaired. It is.
  • the sapphire substrate 101 uses the c-plane, it is compared with the conventional BJT on the r-plane for the same reason as described in the first embodiment.
  • the in-plane uniformity of the device characteristics of the BJT 300 is improved. Therefore, similarly to the first embodiment, it is possible to realize cost reduction and excellent high-frequency characteristics as compared with a semiconductor device having a BJT formed on the r-plane.
  • FIG. 6 is a conceptual diagram of a semiconductor device 400 in which a capacitor (capacitor) 401 that is a passive element and an inductor 402 are formed on the SOS substrate 106 in the present embodiment.
  • a capacitor (capacitor) 401 that is a passive element and an inductor 402 are formed on the SOS substrate 106 in the present embodiment.
  • the capacitor 401 There are, for example, the following three types of methods for forming the capacitor 401, and they may be made according to the application.
  • the first forming method is an MIM (Metal-Insulator-Metal) capacitor in which an insulator is sandwiched between an upper electrode 403 and a lower electrode 404.
  • the capacitor 401 is formed on the SOS substrate 106, and an upper electrode 403 for applying a voltage to the capacitor 401, a lower electrode 404, and between the upper electrode 403 and the lower electrode 404. It has a thin film stack structure including an intervening dielectric layer 405.
  • the SiO 2 layer is formed on the surface of the SOS substrate 106
  • Al is sputtered on the SiO 2 layer.
  • the sputtered Al is patterned into a predetermined pattern as the lower electrode 404.
  • the dielectric layer 405 SiN is deposited to a thickness of about 100 nm by CVD, for example.
  • Al is sputtered on the dielectric layer 405, and the sputtered Al is patterned into a predetermined pattern as the upper electrode 403.
  • the second formation method of the capacitor 401 is a comb capacitor that uses a capacitance between wirings
  • the third formation method is a MOS capacitor that uses the gate capacitance of the MOSFET described in the second embodiment. It is.
  • the capacitor 401 is not limited to the first formation method described above, and may be formed by the second and third formation methods.
  • the inductor 402 is formed by forming a wiring layer used in a normal semiconductor manufacturing process composed of Al by, for example, a sputtering method.
  • the layers are patterned in a spiral shape to form an inductor 402 having a spiral structure.
  • the capacitor 401 and the inductor 402 are formed on the SOS substrate 106 having the sapphire substrate 101 having insulating properties, the Q value (quality-factor) of the capacitor 401 and the inductor 402 increases. Therefore, leakage of the high-frequency input signal passing through them to the sapphire substrate 101 is suppressed, and input loss can be minimized.
  • the sapphire substrate 101 uses the c-plane, so for the same reason as described in the first embodiment, the conventional capacitance on the r-plane and the inductor In comparison, in-plane uniformity of device characteristics is improved. Therefore, similarly to the first embodiment, it is possible to reduce the cost and realize excellent high frequency characteristics.
  • FIG. 7 shows a conceptual circuit diagram of a high-frequency amplifier 500 as an example of a high-frequency integrated circuit composed of a MOSFET, a capacitor, and an inductor formed on an SOS substrate in the present embodiment.
  • the high-frequency amplifier 500 includes a front-stage MOSFET 501, a rear-stage MOSFET 502, an input matching circuit 503, an inter-stage matching circuit 504, an output matching circuit 505, an input terminal 506, an output terminal 507, and a DC power supply terminal 508. Is a two-stage amplifier. Further, the input matching circuit 503, the interstage matching circuit 504, and the output matching circuit 505 have the same capacitance and inductor as those described in the fourth embodiment, and can obtain desired high frequency characteristics. Each matching circuit is configured as described above.
  • the configurations of the MOSFETs 501 and 502 are the same as those of the MOSFET shown in the second embodiment, and the MOSFETs 501 and 502 are formed on the c-plane of the sapphire substrate. Therefore, for the same reason as described in the second embodiment, in-plane uniformity of the device characteristics of the MOSFET is improved as compared with the conventional MOSFET on the r-plane. Therefore, similarly to the first embodiment, the cost can be reduced as compared with the semiconductor device having the MOSFET formed on the r-plane.
  • the main surface is also formed on the insulating sapphire substrate having the c-plane as the main surface, for the same reason as described in the first embodiment, it is more than the capacitance and the inductor formed on the r-plane. Cost reduction can be realized.
  • the high frequency amplifier 500 can realize excellent high frequency characteristics for the same reason as described in the first embodiment.
  • a MOSFET is described as an example of a transistor.
  • the effect of the invention is the same as that of the above MOSFET for the same reason as described in the third embodiment. is there.
  • the effect of the present invention occurs when a semiconductor device is formed on an SOS substrate using insulating sapphire whose principal surface is c-plane. Therefore, not only the above-described high-frequency amplifier 500 but also a circuit other than the high-frequency amplifier 500, for example, a high-frequency integrated circuit such as a high-frequency switch, a low-noise amplifier, a mixer circuit, or a VCO oscillator, produces the same effect.
  • a high-frequency integrated circuit such as a high-frequency switch, a low-noise amplifier, a mixer circuit, or a VCO oscillator
  • FIG. 8 illustrates a high-frequency wireless communication front-end unit of a mobile phone as an example of the high-frequency wireless communication system according to the present embodiment.
  • the high-frequency amplifier formed on the SOS substrate described in the fifth embodiment. It is a circuit block diagram of a front end part including FIG. 9 is a schematic diagram of a mobile phone having a front end portion in the present embodiment.
  • the mobile phone 700 shown in FIG. 9 includes the front end unit 600 shown in FIG. As shown in FIG. 8, the front end unit 600 includes an antenna switch 601, a high frequency amplifier 602, a low noise amplifier 603, an RF-IC / baseband block 604, and an antenna 605.
  • the high frequency amplifier 602 includes a transmission amplifier as a device.
  • the low noise amplifier 603 includes a reception amplifier as a device.
  • the high-frequency amplifier 602 is formed on an SOS substrate using insulating sapphire whose main surface is c-plane.
  • the front-end unit 600 which is a high-frequency wireless communication system including the high-frequency amplifier 602 is an SOS substrate having a Si substrate on the r-plane of a conventional sapphire substrate. Compared with the high-frequency wireless communication system including the high-frequency amplifier created above, in-plane variations in device characteristics can be suppressed, and at the same time, these can be realized at low cost.
  • the block of the high-frequency amplifier 602 is formed on the SOS substrate.
  • circuits other than the high-frequency amplifier 602 such as a low-noise amplifier 603, a high-frequency switch, a mixer circuit, and a VCO oscillator are provided. Even if the high-frequency wireless communication circuit block including the same is formed on the SOS substrate, the same effect is produced. Further, all devices in the high-frequency wireless communication system may be formed on the SOS substrate, or only a part may be formed on the SOS substrate.
  • the cellular phone 700 that is the high-frequency wireless communication system in this embodiment can realize excellent high-frequency characteristics for the same reason as described in the first embodiment.
  • the device formed on the SOS substrate is not limited to the above-described MOSFET, BJT, capacitor, and inductor, but may be another device or a combination of these devices. In addition to the electronic device described above, it may be combined with an optical device.
  • devices such as transistors, capacitors, and inductors are formed by processing the Si layer on the SOS substrate.
  • devices formed on the SOS substrate are separated from each other in advance, for example.
  • the passive element, the active element, etc. manufactured in (1) may be arranged on the SOS substrate.
  • the sapphire substrate and Si substrate used for forming the SOS substrate are not limited to 6-inch wafers, and may be, for example, 8-inch wafers or other sizes and shapes. Further, the thicknesses of the sapphire substrate and the Si substrate are not limited to the above examples, and may be changed.
  • SiO 2 is formed on the Si substrate before bonding the sapphire substrate and the Si substrate.
  • the SiO 2 layer is not necessarily formed.
  • the sapphire substrate whose main surface is the c-plane is used, but not limited to the c-plane, a sapphire substrate having other surfaces as the main surface may be used. At this time, it is preferable to use a surface with little anisotropy as a main surface. Moreover, you may use not only a sapphire board
  • a p-type Si substrate is used.
  • the present invention is not limited to the p-type, and an n-type Si substrate may be used.
  • the method for manufacturing the semiconductor device is not limited to the above-described method, and the method may be replaced before and after the process, or these methods may be combined or other methods may be used.
  • H ions are implanted into the Si substrate to form a cleavage layer, and after joining the sapphire substrate and the Si substrate, the Si substrate is divided in the cleavage layer to obtain a Si substrate having a desired thickness.
  • the thickness of the SOS substrate is reduced, the thickness of the SOS substrate is not limited to the example described above, and the SOS substrate is polished from the Si substrate side after the sapphire substrate and the Si substrate are bonded together. The thickness may be reduced. In this case, since the SOS substrate is not heated, the thickness of the SOS substrate can be reduced without damaging the SOS substrate by heating.
  • the semiconductor device according to the present invention includes other embodiments realized by combining arbitrary components in the above embodiments, and those skilled in the art without departing from the gist of the present invention with respect to the embodiments.
  • the present invention includes modifications obtained by performing various modifications that can be conceived, various devices including the semiconductor device according to the present invention, and the like.
  • active elements and passive elements formed on an SOS substrate, a high-frequency integrated circuit including these elements, and a high-frequency wireless communication system including these elements and high-frequency integrated circuits are also included in the present invention.
  • the semiconductor device, high-frequency integrated circuit, and high-frequency wireless communication system according to the present invention are useful for application to a high-frequency wireless communication system.
  • it is useful for application to portable high-frequency wireless communication devices and high-frequency wireless communication systems that require excellent high-frequency characteristics and miniaturization / cost reduction at the same time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur dans lequel l'anisotropie d'un substrat SOS est réduite et par conséquent l'uniformité dans le plan des propriétés du dispositif est améliorée. Elle concerne spécifiquement un dispositif semi-conducteur (10) qui comporte une couche de Si (ou un substrat de Si) (100) formé(e) sur la surface principale d'un substrat isolant (101), le substrat isolant (101) étant un substrat de saphir (101) et la surface principale du substrat isolant (101) étant une face (c). Dans le dispositif semi-conducteur (10), la couche de Si (100) est formée sur la face (c) qui présente une faible anisotropie dans le substrat de saphir (101), ce qui permet par conséquent d'améliorer l'uniformité dans le plan des propriétés du dispositif sur la couche de Si (100) du dispositif semi-conducteur (10).
PCT/JP2010/005221 2009-12-25 2010-08-25 Dispositif semi-conducteur, circuit intégré à haute fréquence, système de communication sans fil à haute fréquence, et processus de production du dispositif semi-conducteur WO2011077608A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-296170 2009-12-25
JP2009296170A JP2011138818A (ja) 2009-12-25 2009-12-25 半導体装置、高周波集積回路、高周波無線通信システムおよび半導体装置の製造方法

Publications (1)

Publication Number Publication Date
WO2011077608A1 true WO2011077608A1 (fr) 2011-06-30

Family

ID=44195162

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/005221 WO2011077608A1 (fr) 2009-12-25 2010-08-25 Dispositif semi-conducteur, circuit intégré à haute fréquence, système de communication sans fil à haute fréquence, et processus de production du dispositif semi-conducteur

Country Status (3)

Country Link
JP (1) JP2011138818A (fr)
TW (1) TW201133805A (fr)
WO (1) WO2011077608A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014017368A1 (fr) 2012-07-25 2014-01-30 信越化学工業株式会社 Procédé de production de substrats sos et substrat sos
WO2014017369A1 (fr) * 2012-07-25 2014-01-30 信越化学工業株式会社 Procédé de production de substrats hybrides et substrat hybride

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105634A1 (fr) 2012-01-12 2013-07-18 信越化学工業株式会社 Substrat composite hétérogène oxydé thermiquement et son procédé de fabrication

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124473A (ja) * 2000-10-13 2002-04-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体基板の製造方法
JP2003031781A (ja) * 2001-05-09 2003-01-31 Internatl Business Mach Corp <Ibm> ウエハ接合によるサファイア上シリコンデバイスの製造方法
JP2008192907A (ja) * 2007-02-06 2008-08-21 Oki Electric Ind Co Ltd シリコンエピタキシャル膜を有するｓｏｓ基板の形成法
JP2008277501A (ja) * 2007-04-27 2008-11-13 Shin Etsu Chem Co Ltd 貼り合わせウエーハの製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124473A (ja) * 2000-10-13 2002-04-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体基板の製造方法
JP2003031781A (ja) * 2001-05-09 2003-01-31 Internatl Business Mach Corp <Ibm> ウエハ接合によるサファイア上シリコンデバイスの製造方法
JP2008192907A (ja) * 2007-02-06 2008-08-21 Oki Electric Ind Co Ltd シリコンエピタキシャル膜を有するｓｏｓ基板の形成法
JP2008277501A (ja) * 2007-04-27 2008-11-13 Shin Etsu Chem Co Ltd 貼り合わせウエーハの製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014017368A1 (fr) 2012-07-25 2014-01-30 信越化学工業株式会社 Procédé de production de substrats sos et substrat sos
WO2014017369A1 (fr) * 2012-07-25 2014-01-30 信越化学工業株式会社 Procédé de production de substrats hybrides et substrat hybride
KR20150037896A (ko) 2012-07-25 2015-04-08 신에쓰 가가꾸 고교 가부시끼가이샤 Sos 기판의 제조 방법 및 sos 기판
US20150179506A1 (en) * 2012-07-25 2015-06-25 Shin-Etsu Chemical Co., Ltd. Method for producing sos substrates, and sos substrate
JPWO2014017368A1 (ja) * 2012-07-25 2016-07-11 信越化学工業株式会社 Ｓｏｓ基板の製造方法及びｓｏｓ基板
US9646873B2 (en) 2012-07-25 2017-05-09 Shin-Etsu Chemical Co., Ltd. Method for producing SOS substrates, and SOS substrate
TWI609434B (zh) * 2012-07-25 2017-12-21 信越化學工業股份有限公司 SOS substrate manufacturing method and SOS substrate

Also Published As

Publication number Publication date
TW201133805A (en) 2011-10-01
JP2011138818A (ja) 2011-07-14

Similar Documents

Publication Publication Date Title
US7256473B2 (en) Composite structure with high heat dissipation
US7393732B2 (en) Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US7468538B2 (en) Strained silicon on a SiGe on SOI substrate
US7422956B2 (en) Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
US7579623B2 (en) Stacked transistors and process
US7825470B2 (en) Transistor and in-situ fabrication process
US20080020515A1 (en) Twisted Dual-Substrate Orientation (DSO) Substrates
US9607986B2 (en) Mixed orientation semiconductor device and method
JP2007533137A (ja) ＳＯＩ（ｓｅｍｉｃｏｎｄｕｃｔｏｒｏｎｉｎｓｕｌａｔｏｒ）基板、およびこの基板から形成されるデバイス
JP2020202391A (ja) 異なる歪み状態を有するフィン構造を含む半導体構造を作製するための方法及び関連する半導体構造
US7033869B1 (en) Strained silicon semiconductor on insulator MOSFET
US20090173939A1 (en) Hybrid Wafers
JP2003249641A (ja) 半導体基板、その製造方法及び半導体装置
US7250656B2 (en) Hybrid-orientation technology buried n-well design
WO2011077608A1 (fr) Dispositif semi-conducteur, circuit intégré à haute fréquence, système de communication sans fil à haute fréquence, et processus de production du dispositif semi-conducteur
JP2004128254A (ja) 半導体装置
US7323396B2 (en) Signal and/or ground planes with double buried insulator layers and fabrication process
JP5972917B2 (ja) 空間的に閉じ込められた誘電体領域を含む半導体構造
US11646238B2 (en) Dual crystal orientation for semiconductor devices
CN115863400B (zh) 一种高导热GaN基HEMT器件及其制备方法
JP4792757B2 (ja) 半導体基板の製造方法および半導体装置の製造方法
US20150041824A1 (en) Transistor with bonded gate dielectric
TW202301550A (zh) 半導體器件及其製造方法
TW396629B (en) Manufacturing method of EPI-base BJT
JPH0637099A (ja) 半導体基体及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10838849

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10838849

Country of ref document: EP

Kind code of ref document: A1