WO2011074361A1 - Iii族窒化物結晶基板、エピ層付iii族窒化物結晶基板、ならびに半導体デバイスおよびその製造方法 - Google Patents
Iii族窒化物結晶基板、エピ層付iii族窒化物結晶基板、ならびに半導体デバイスおよびその製造方法 Download PDFInfo
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- WO2011074361A1 WO2011074361A1 PCT/JP2010/070290 JP2010070290W WO2011074361A1 WO 2011074361 A1 WO2011074361 A1 WO 2011074361A1 JP 2010070290 W JP2010070290 W JP 2010070290W WO 2011074361 A1 WO2011074361 A1 WO 2011074361A1
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- Prior art keywords
- crystal substrate
- group iii
- plane
- iii nitride
- main surface
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
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- C30B29/403—AIII-nitrides
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- B82—NANOTECHNOLOGY
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01S5/320275—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures grown on specifically orientated substrates, or using orientation dependent growth semi-polar orientation
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- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
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- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/2004—Confining in the direction perpendicular to the layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
Definitions
- the present invention relates to a group III nitride crystal substrate, a group III nitride crystal substrate with an epi layer, and a semiconductor device and a method for manufacturing the same, and particularly, preferably used as a substrate for epitaxial crystal growth of a semiconductor layer in manufacturing a semiconductor device.
- Group III nitride crystal substrate preferably used as a substrate for epitaxial crystal growth of a semiconductor layer in manufacturing a semiconductor device.
- nitride semiconductor crystals for example, group III nitride semiconductor crystals
- nitride semiconductor light emitting devices for example, Group III nitride semiconductor light-emitting devices
- a plurality of nitride semiconductor layers are epitaxially grown on a substrate.
- the crystal quality of the epitaxially grown nitride semiconductor layer is affected by the state of the surface layer of the substrate used for the epitaxial growth, and affects the performance of the semiconductor device including the nitride semiconductor layer. Therefore, when a nitride semiconductor crystal is used as such a substrate, it is desirable that at least the main surface of the substrate serving as the base for epitaxial growth does not contain distortion and is smooth.
- the main surface of the nitride semiconductor substrate used for epitaxial growth is generally subjected to smoothing processing and distortion removal processing.
- the gallium nitride semiconductor is relatively hard among the compound semiconductors, and the surface smoothing process is not easy, and the distortion removing process after the smoothing process is not easy.
- Patent Document 1 when a substrate is produced from an (AlGaIn) N bulk crystal grown by vapor phase epitaxy on an (AlGaIn) N seed crystal, the surface of the substrate polished mechanically is used. A method of forming a substrate surface having an RMS (root mean square) surface roughness of 1 nm or less by removing surface damage by performing CMP (Chemical Mechanical Polishing), etching or the like on the substrate is disclosed.
- the CMP treating agent includes Al 2 O 3 abrasive grains, SiO 2 abrasive grains, a pH adjuster, and an oxidizing agent.
- a GaN substrate having a substrate surface finished by removing a work-affected layer during mechanical polishing is obtained by mechanically polishing a GaN crystal and then performing CMP treatment or dry etching.
- the CMP process has a low processing speed and has a problem in cost and productivity.
- dry etching there is a problem of surface roughness.
- the finishing method by CMP of the Si substrate and the polishing agent in that method are not suitable for a hard nitride semiconductor substrate, and slow the removal rate of the surface layer.
- GaN is chemically stable and difficult to perform wet etching, so that CMP processing is not easy.
- the surface of the nitride semiconductor can be removed by dry etching, there is no effect of flattening the surface in the horizontal direction, so that surface smoothing cannot be obtained.
- Patent Document 3 a nitride crystal substrate and a semiconductor device using the substrate are subjected to CMP under predetermined conditions after mechanically polishing a GaN crystal or an AlN crystal, Nitride in which at least one of uniform strain, non-uniform strain and plane orientation deviation of crystal surface layer evaluated by X-ray diffraction measurement changing X-ray penetration depth from the surface of the crystal is within a predetermined range It has been proposed that a crystal substrate is suitable for the manufacture of semiconductor devices.
- the substrates exemplified in the above-mentioned US Pat. No. 6,596,079 (Patent Document 1), US Pat. No. 6,488,767 (Patent Document 2) and JP-A-2007-005526 (Patent Document 3) are as follows: These are hexagonal wurtzite group III nitride crystals, and their main surface is the (0001) plane.
- the main surface of the semiconductor layer is also the (0001) plane, and the (0001) plane is Since it is a polar surface whose polarity changes in the normal direction of the surface, the blue confinement of emission due to the increase in current injection amount increases due to the quantum confined Stark effect caused by piezo polarization due to such polarity, and the emission intensity decreases.
- the polarity of the main surface of the substrate used for manufacturing the light emitting device is reduced, that is, the main surface of the substrate is a surface other than the (0001) plane. It is necessary to.
- the substrate suitable for manufacturing a light emitting device in which the blue shift of light emission is suppressed the plane orientation of the main surface, the surface roughness of the main surface, the crystallinity of the surface layer, etc. are completely unknown.
- the present invention provides a group III nitride crystal substrate, a group III nitride crystal substrate with an epi layer, a semiconductor device, and a method for manufacturing the same suitable for manufacturing a light emitting device in which blue shift of light emission is suppressed. Objective.
- the group III nitride crystal substrate according to an aspect of the present invention changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate.
- the plane spacing at the X-ray penetration depth of 0.3 ⁇ m is expressed as d 1 and the plane spacing at the X-ray penetration depth of 5 ⁇ m is expressed as d 2.
- / d 2 is 1.7 ⁇ 10 ⁇ 3 or less, and the plane orientation of the main surface is c It has an inclination angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane including the axis.
- the group III nitride crystal substrate according to another aspect of the present invention has an X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate.
- the half-value width v 1 of the diffraction intensity peak at an X-ray penetration depth of 0.3 ⁇ m and the diffraction intensity peak at an X-ray penetration depth of 5 ⁇ m The non-uniform distortion of the surface layer of the crystal substrate represented by the value of
- the group III nitride crystal substrate according to still another aspect of the present invention changes the X-ray penetration depth from the main surface of the crystal substrate with respect to the X-ray diffraction of any specific parallel crystal lattice plane of the group III nitride crystal substrate.
- is 300 arcsec or less, and the plane orientation of the main surface is [0001] from the plane including the c-axis of the crystal substrate.
- the direction has an inclination angle of ⁇ 10 ° to 10 °.
- the main surface can have a surface roughness Ra of 5 nm or less.
- the plane orientation of the main surface is such that the tilt angle is 0 ° or more and 0.1 ° with respect to any of the ⁇ 10-10 ⁇ , ⁇ 11-20 ⁇ , and ⁇ 21-30 ⁇ planes of the crystal substrate. Less than or substantially parallel.
- the plane orientation of the main surface is such that the tilt angle from any one of the ⁇ 10-10 ⁇ plane, ⁇ 11-20 ⁇ plane and ⁇ 21-30 ⁇ plane of the crystal substrate is 0.1 ° or more and 10 ° or less. It can be.
- the concentration of oxygen present on the main surface can be 2 atomic% or more and 16 atomic% or less.
- the dislocation density on the main surface can be set to 1 ⁇ 10 7 cm ⁇ 2 or less.
- the group III nitride crystal substrate can have a diameter of 40 mm or more and 150 mm or less.
- the group III nitride crystal substrate with an epi layer includes at least one semiconductor layer formed by epitaxial growth on the main surface of the group III nitride crystal substrate.
- a semiconductor device includes the above-described group III nitride crystal substrate with an epi layer.
- the semiconductor layer included in the group III nitride crystal substrate with an epi layer may include a light emitting layer that emits light having a peak wavelength of 430 nm or more and 550 nm or less.
- a method for manufacturing a semiconductor device wherein an X-ray penetration depth from a main surface of a crystal substrate is set while satisfying an X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate.
- the plane spacing at the X-ray penetration depth of 0.3 ⁇ m is represented as d 1
- the plane spacing at the X-ray penetration depth of 5 ⁇ m is represented as d 2 .
- / d 2 is 1.7 ⁇ 10 ⁇ 3 or less, and the plane orientation of the main surface is c of the crystal substrate.
- a method for manufacturing a semiconductor device wherein an X-ray penetration depth from a main surface of a crystal substrate is set while satisfying an X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate.
- the half-value width v 1 of the diffraction intensity peak at an X-ray penetration depth of 0.3 ⁇ m and the diffraction intensity peak at an X-ray penetration depth of 5 ⁇ m The non-uniform strain of the surface layer of the crystal substrate expressed by the value of
- a method for manufacturing a semiconductor device by changing an X-ray penetration depth from a main surface of a crystal substrate with respect to X-ray diffraction of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate.
- the semiconductor layer includes a light emitting layer, and the light emitting layer emits light having a peak wavelength of 430 nm or more and 550 nm or less. Can be formed.
- the group III nitride crystal substrate suitable for manufacture of the light-emitting device with which the blue shift of light was suppressed and emitted light intensity increased the group III nitride crystal substrate with an epi layer, a semiconductor device, and its manufacturing method can be provided.
- FIG. 3B is a schematic diagram showing the spacing between specific parallel crystal lattice planes in the diffraction intensity profile of the X-ray diffraction method related to the uniform strain of the crystal lattice of the group III nitride crystal substrate of FIG. 3A.
- Group III nitride crystal substrate In crystal geometry, crystal axes are set to describe a crystal system. In a hexagonal crystal such as a group III nitride crystal forming a group III nitride crystal substrate, an a 1 axis, an a 2 axis and three axes extending in three directions at an angle of 120 ° from the origin on the same plane a 3 axis, c axis perpendicular to the plane including these three axes is set.
- a plane including at least one of the a 1 axis, a 2 axis, a 3 axis, and c axis or a plane parallel to the plane has no intercept of those axes, and the Miller index corresponding to these axes is 0. It is represented by For example, the plane orientation of the plane including the c axis and the plane parallel to the c axis is represented by (hki0), and examples thereof include (10-10), (11-20), and (21-30).
- This plane (hkil) plane is called (hkil) plane.
- the individual plane orientation is represented by (hkil)
- the generic plane orientation including (hkil) and the plane orientation equivalent to the crystal geometry is represented by ⁇ hkil ⁇ .
- each direction is represented by [hkil], and [hkil] and a direction including a crystal geometrically equivalent direction is represented by ⁇ hkil>.
- Negative indices are generally expressed by adding “-” (bar) on the number representing the index in the crystal geometry, but in this specification, before the number representing the index. Represented with a negative sign (-).
- the group III nitride crystal has polarity in the ⁇ 0001> direction because the group III element atomic plane and the nitrogen atomic plane are alternately arranged in the ⁇ 0001> direction.
- the crystal axes are set so that the group III element atomic plane is the (0001) plane and the nitrogen atomic plane is the (000-1) plane.
- the crystallinity in the surface layer of the group III nitride crystal substrate can be directly evaluated without destroying the crystal.
- the evaluation of crystallinity means evaluating the degree of crystal distortion, and specifically, evaluating the degree of crystal lattice distortion and crystal plane misalignment. That means.
- the crystal lattice distortion includes a uniform strain in which the crystal lattice is uniformly distorted and a non-uniform strain in which the crystal lattice is distorted non-uniformly.
- the crystal orientation deviation of the crystal lattice plane refers to the magnitude of variation in which the plane orientation of the lattice plane of each crystal lattice is deviated from the average orientation of the plane orientation of the crystal plane of the entire crystal lattice.
- a group III nitride crystal substrate 1 is formed by cutting a group III nitride crystal from a main surface 1s of the crystal substrate by processing such as cutting, grinding or polishing from a group III nitride crystal body. At least one of a uniform distortion, a non-uniform distortion and a plane orientation deviation of the crystal lattice occurs (FIG. 1 shows a case where a uniform distortion, a non-uniform distortion and a plane orientation deviation of the crystal lattice occur in the surface layer 1p. ).
- the surface adjacent layer 1q adjacent to the surface layer 1p may have at least one of a uniform distortion of the crystal lattice, a non-uniform distortion of the crystal lattice, and a plane orientation shift of the crystal lattice (FIG. 1 shows the surface adjacent layer 1q). This shows the case where the crystal lattice is misaligned.) Further, the inner layer 1r inside the surface adjacent layer 1q is considered to have the original crystal structure of the crystal. The state and thickness of the surface layer 1p and the surface adjacent layer 1q vary depending on the grinding or polishing method and degree in the surface processing.
- the crystallinity of the surface layer can be directly and reliably evaluated by evaluating the uniform strain, nonuniform strain and / or plane orientation deviation of the crystal lattice in the depth direction from the main surface of the crystal substrate. it can.
- the X-ray diffraction measurement for evaluating the crystallinity of the surface layer of the group III nitride crystal substrate is performed while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate.
- the X-ray penetration depth from the main surface is changed.
- the X-ray penetration depth refers to the distance in the vertical depth direction from the main surface 1s of the crystal substrate when the intensity of the incident X-ray is 1 / e (e is the base of natural logarithm).
- this X-ray penetration depth T corresponds to the X-ray absorption coefficient ⁇ of group III nitride crystal substrate 1, the tilt angle ⁇ of main surface 1s of the crystal substrate, and the main surface 1s of crystal substrate.
- the X-ray incident angle ⁇ and the Bragg angle ⁇ are expressed as in Expression (1).
- the ⁇ axis 21 is in the plane formed by the incident X-ray 11 and the outgoing X-ray 12, and the ⁇ axis 22 (2 ⁇ axis) is perpendicular to the plane formed by the incident X-ray 11 and the outgoing X-ray 12.
- the ⁇ axis 23 is perpendicular to the main surface 1s of the crystal substrate.
- the rotation angle ⁇ indicates the rotation angle within the main surface 1s of the crystal substrate.
- the X-ray penetration depth T can be continuously set. Can be changed.
- the specific parallel crystal lattice plane 1d and the main surface 1s of the crystal substrate are not parallel. It is necessary. If the specific parallel crystal lattice plane and the main surface of the crystal substrate are parallel, the Bragg angle ⁇ , which is an angle between the specific parallel crystal lattice plane 1d and the incident X-ray 11, and the main surface 1s of the crystal substrate and the incident X-ray 11 The X-ray incident angle ⁇ , which is the angle formed by the above, becomes the same, and the X-ray penetration depth cannot be changed in the specific parallel crystal lattice plane 1d.
- the specific parallel crystal lattice plane is not particularly limited except that it is not parallel to the main surface of the crystal substrate, but from the viewpoint of easy evaluation by X-ray diffraction at a desired penetration depth ( 10-10) plane, (10-11) plane, (10-13) plane, (10-15) plane, (11-20) plane, (22-41) plane, (11-21) plane, (11 ⁇ 22), (11-24), (10-1-1), (10-1-3), (10-1-5), (22-4-1), (11 The (2-1) plane, (11-2-2) plane, (11-2-4) plane, etc. are preferably used.
- the X-ray penetration depth is changed to irradiate an arbitrary specific parallel crystal lattice plane of the crystal substrate with X-rays, and the uniform distortion of the crystal lattice is determined from the change in the interplanar spacing in the diffraction intensity profile for the specific parallel crystal lattice plane.
- the crystal lattice non-uniform distortion is evaluated from the change in half-value width of the diffraction intensity peak in the diffraction intensity profile, and the plane orientation shift of the crystal lattice is evaluated from the change in half-value width of the diffraction intensity peak in the rocking curve.
- the plane orientation of main surface 1s is ⁇ 10 ° in the [0001] direction from plane 1v including c-axis 1c of the crystal substrate.
- the inclination angle ⁇ is not less than 10 °.
- the plane orientation of the main surface 1s is inclined from the plane 1v including the c axis toward the [0001] direction, that is, the (0001) plane, and the inclination angle ⁇ is negative.
- the plane orientation of the main surface 1s is inclined from the plane 1v including the c-axis toward the [000-1] direction, that is, the (000-1) plane.
- the plane orientation of the main surface 1s of the group III nitride crystal substrate 1 has an inclination angle of ⁇ 10 ° to 10 ° in the [0001] direction from the surface 1v including the c-axis 1c of the crystal substrate.
- a light-emitting device that is a semiconductor device including at least one semiconductor layer epitaxially grown on the main surface, the piezoelectric polarization of the light-emitting layer in the semiconductor layer is suppressed, and the quantum confined Stark effect is reduced. Since recombination becomes easy and the light emission transition probability increases, the blue shift of the light emitting device is reduced and the integrated intensity of light emission is increased.
- the inclination angle ⁇ of the plane orientation of the main surface 1s from the plane 1v including the c-axis 1c to the [0001] direction in the group III nitride crystal substrate is preferably ⁇ 9 ° to 9 °, and ⁇ 6 ° It is more preferably 6 ° or less and more preferably ⁇ 3 ° or more and 3 ° or less.
- the inclination angle ⁇ of the surface orientation of the main surface can be measured by an X-ray diffraction method or the like.
- a group III nitride crystal substrate 1 is an arbitrary parallel crystal lattice of group III nitride crystal substrate 1.
- the plane spacing of the specific parallel crystal lattice plane 1d obtained from the X-ray diffraction measurement changing the X-ray penetration depth from the main surface 1s the plane spacing at the X-ray penetration depth of 0.3 ⁇ m is d 1 (plane spacing d 1 and so on), and the surface spacing at the X-ray penetration depth of 5 ⁇ m is expressed as d 2 (surface spacing d 2 , the same shall apply hereinafter) as a value of
- the uniform distortion of the surface layer 1p of the crystal substrate to be formed is 1.7 ⁇ 10 ⁇ 3 or less, and the plane orientation of the main surface 1s has an inclination angle ⁇ of ⁇ 10 ° to 10 ° in the [0001] direction from the plane 1v including the c-axis 1c of the crystal substrate.
- the group III nitride crystal substrate 1 of the present embodiment has a uniform distortion of the surface layer 1p of 1.7 ⁇ 10 ⁇ 3 or less and a [0001] direction from the surface 1v including the c-axis 1c of the crystal substrate.
- a light emission which is a semiconductor device including at least one semiconductor layer epitaxially grown on the main surface 1s of the crystal substrate when the inclination angle ⁇ of the surface orientation of the main surface 1s to the substrate is ⁇ 10 ° to 10 ° It is possible to reduce the blue shift of the device and increase the integrated intensity of light emission.
- the uniform strain of the surface layer 1p is preferably 1.2 ⁇ 10 ⁇ 3 or less, more preferably 1.0 ⁇ 10 ⁇ 3 or less, further preferably 0.8 ⁇ 10 ⁇ 3 or less, 0.5 ⁇ 10 ⁇ 3 or less is particularly preferable.
- the uniform distortion of the surface layer 1p is preferably as small as possible, and in this application as well, it is reduced to about 0.1 ⁇ 10 ⁇ 3 by adjusting the processing conditions of the main surface of the crystal substrate, as will be described later. ing.
- the inclination angle ⁇ of the plane orientation of the main surface 1s is preferably ⁇ 8 ° or more and 8 ° or less, more preferably ⁇ 5 ° or more and 5 ° or less, further preferably ⁇ 2 ° or more and 2 ° or less, and ⁇ 1.5 It is particularly preferably from 0 ° to 0.1 ° or from 0.1 ° to 1.5 °.
- the X-ray penetration depth of 0.3 ⁇ m corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 ⁇ m is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r.
- the interplanar spacing d 2 at the X-ray penetration depth of 5 ⁇ m is considered to be the spacing of the specific parallel crystal lattice plane inherent in the group III nitride crystal.
- the interplanar spacing d 1 at 3 ⁇ m is uniform in the crystal lattice of the surface layer 1p due to the influence of the surface processing of the group III nitride crystal substrate 1 (for example, tensile stress 30 in a direction parallel to the specific parallel crystal lattice surface 1d). Reflecting the distortion, it takes a value different from the surface spacing d 2 at the X-ray penetration depth of 5 ⁇ m.
- group III nitride crystal substrate 1 is an arbitrary parallel crystal of group III nitride crystal substrate 1.
- the crystal substrate while satisfying the X-ray diffraction conditions of the lattice plane 1d (referred to as specific parallel crystal lattice planes 1d formed by the specific parallel crystal lattice planes 41d, 42d, and 43d of each crystal lattice; the same applies hereinafter).
- the plane orientation of the surface 1s has a [0001] inclination angle of -10 ° to 10 ° in the direction ⁇ from the plane 1v including c-axis 1c of the crystal substrate.
- the group III nitride crystal substrate 1 of this embodiment has a nonuniform strain of the surface layer 1p of 110 arcsec or less, and the main surface 1s in the [0001] direction from the plane 1v including the c-axis 1c of the crystal substrate.
- the tilt angle ⁇ of the plane orientation is ⁇ 10 ° or more and 10 ° or less
- the blue shift of the light-emitting device which is a semiconductor device including at least one semiconductor layer epitaxially grown on the main surface 1s of the crystal substrate is reduced.
- the integrated intensity of light emission can be increased.
- the nonuniform strain of the surface layer 1p is preferably 70 arcsec or less, more preferably 50 arcsec or less, and further preferably 20 arcsec or less.
- the non-uniform distortion of the surface layer 1p is preferably as small as possible, and in this application as well, it is reduced to 0 arcsec by adjusting the processing conditions of the main surface of the crystal substrate, as will be described later.
- the inclination angle ⁇ of the surface orientation of the main surface 1s is preferably ⁇ 7 ° or more and 7 ° or less, more preferably ⁇ 4 ° or more and 4 ° or less, further preferably ⁇ 1 ° or more and 1 ° or less, and more preferably ⁇ 1 ° or more. -0.1 ° or less or 0.1 ° or more and 1 ° or less is particularly preferable.
- the X-ray penetration depth of 0.3 ⁇ m corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 ⁇ m is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r.
- the half-value width v 2 of the diffraction intensity peak at the X-ray penetration depth of 5 ⁇ m is considered to be the original half-value width of the group III nitride crystal, but at the X-ray penetration depth of 0.3 ⁇ m.
- the half-value width v 1 of the diffraction intensity peak is a non-uniform distortion of the crystal lattice of the surface layer 1p due to the influence of the surface processing of the group III nitride crystal substrate 1 (for example, the spacing between the crystal lattice planes is d 3 , d 4 reflecting the different) and ⁇ d 5, d 6, take half width v 2 different values of the diffraction intensity peak at the X-ray penetration depth of 5 [mu] m.
- the uneven strain of the surface layer 1p can be expressed by the value of
- group III nitride crystal substrate 1 which is another embodiment of the present invention is an arbitrary parallel crystal of group III nitride crystal substrate 1.
- the main surface of the crystal substrate with respect to the X-ray diffraction of the lattice plane 1d (referring to the specific parallel crystal lattice plane 1d formed by the specific parallel crystal lattice planes 51d, 52d, 53d of each crystal lattice; the same applies hereinafter).
- the half-value width w 1 of the diffraction intensity peak at an X-ray penetration depth of 0.3 ⁇ m and the diffraction intensity peak at an X-ray penetration depth of 5 ⁇ m The plane orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p of the crystal substrate expressed by the value of
- the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p is 300 arcsec or less, and from the plane 1v including the c-axis 1c of the crystal substrate [0001]
- the semiconductor device includes at least one semiconductor layer epitaxially grown on the main surface 1s of the crystal substrate when the inclination angle ⁇ of the surface orientation of the main surface 1s in the direction is ⁇ 10 ° to 10 °.
- the blue shift of the light emitting device can be reduced and the integrated intensity of light emission can be increased.
- the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p is preferably 220 arcsec or less, more preferably 140 arcsec or less, and further preferably 70 arcsec or less.
- the specific crystal of the surface layer 1p is preferably as small as possible. Also in the present application, as will be described later, by adjusting the processing conditions of the main surface of the crystal substrate, the specific crystal is reduced to 0 arcsec.
- the inclination angle ⁇ of the plane orientation of the main surface 1s is preferably ⁇ 8 ° or more and 8 ° or less, more preferably ⁇ 5 ° or more and 5 ° or less, further preferably ⁇ 2 ° or more and 2 ° or less, and ⁇ 1.5 It is particularly preferably from 0 ° to 0.1 ° or from 0.1 ° to 1.5 °.
- the X-ray penetration depth of 0.3 ⁇ m corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 ⁇ m is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r.
- the half-value width w 2 of the diffraction intensity peak at the X-ray penetration depth of 5 ⁇ m is considered to be the original half-value width of the group III nitride crystal, but at the X-ray penetration depth of 0.3 ⁇ m.
- the full width at half maximum w 1 of the diffraction intensity peak is the crystal orientation misalignment of the surface layer 1p due to the surface processing of the group III nitride crystal substrate 1 (for example, specific parallel crystal lattice planes 51d, 52d, 53d of each crystal lattice).
- specific parallel crystal lattice planes 51d, 52d, 53d of each crystal lattice are different from the full width at half maximum w 2 at the X-ray penetration depth of 5 ⁇ m.
- the plane orientation deviation of the specific parallel crystal lattice plane of the crystal surface layer can be expressed by the value of
- main surface 1s preferably has a surface roughness Ra of 5 nm or less.
- the surface roughness Ra means the arithmetic average roughness Ra specified in JIS B 0601-1994.
- Such surface roughness Ra can be measured by an AFM (atomic force microscope), an optical interference type roughness meter, or the like.
- AFM atomic force microscope
- an optical interference type roughness meter or the like.
- the surface roughness Ra of the main surface of the group III nitride crystal substrate is more preferably 3 nm or less, and further preferably 1 nm or less.
- the surface roughness Ra of the main surface of the group III nitride crystal substrate is preferably 1 nm or more. Therefore, from the viewpoint of achieving both high quality and high productivity of the group III nitride crystal substrate and the semiconductor device, the surface roughness Ra of the main surface of the group III nitride crystal substrate is preferably 1 nm to 3 nm.
- the main surface 1s preferably has a surface roughness Ry of 50 nm or less.
- the surface roughness Ry means the maximum height Ry defined in JIS B 0601-1994.
- the surface roughness Ry is extracted from the roughness curved surface by a 10 ⁇ m square as a reference area in the direction of the average surface. This is the sum of the height from the average surface of the extracted portion to the highest peak and the depth to the lowest valley bottom.
- Such surface roughness Ry can be measured by an AFM (atomic force microscope), an optical interference roughness meter, or the like.
- the surface roughness Ry of the main surface of the group III nitride crystal substrate is more preferably 30 nm or less, and further preferably 10 nm or less. Moreover, 10 nm or more and 30 nm or less are preferable from a viewpoint of making high quality and high productivity compatible.
- the plane orientation of main surface 1s is the plane 1v including c-axis 1c of the crystal substrate.
- the inclination angle ⁇ from any one of the ⁇ 10-10 ⁇ plane, ⁇ 11-20 ⁇ plane, and ⁇ 21-30 ⁇ plane is preferably 0 ° or more and 10 ° or less.
- the inclination angle ⁇ is 0 ° or more and less than 0.1 ° with respect to any of the ⁇ 10-10 ⁇ , ⁇ 11-20 ⁇ , and ⁇ 21-30 ⁇ planes of the main surface 1s. Is substantially parallel, the In (indium) uptake concentration in the well layer in the light emitting layer included in at least one semiconductor layer epitaxially grown on the main surface 1s can be increased. Growth of a desired composition can be performed without lowering, and the crystallinity of the well layer can be improved. For this reason, the light-emitting device (semiconductor device) obtained has a favorable light emission characteristic.
- the plane orientation of the main surface 1s is such that the tilt angle from any one of the ⁇ 10-10 ⁇ plane, ⁇ 11-20 ⁇ plane and ⁇ 21-30 ⁇ plane of the crystal substrate is 0.1 ° or more and 10 ° or less. Even so, as described above, the tilt angle ⁇ is 0 ° with respect to any of the ⁇ 10-10 ⁇ , ⁇ 11-20 ⁇ , and ⁇ 21-30 ⁇ planes of the main surface 1s. As a result, a semiconductor device having good light-emitting characteristics substantially the same as when it is substantially parallel to less than 0.1 ° can be obtained.
- the plane orientation of the main surface 1s is such that the tilt angle from any one of the ⁇ 10-10 ⁇ plane, ⁇ 11-20 ⁇ plane and ⁇ 21-30 ⁇ plane of the crystal substrate is 0.1 ° or more and 10 ° or less.
- the morphology of the semiconductor layer to be grown is improved, so that the resulting light emitting device (semiconductor device) has good light emitting characteristics.
- the tilt angle of the plane orientation of the main surface 1s from any one of the ⁇ 10-10 ⁇ plane, ⁇ 11-20 ⁇ plane, and ⁇ 21-30 ⁇ plane of the crystal substrate is 0.1 ° or more and 2 ° or less.
- good light emission characteristics can be obtained in a light emitting device which is a semiconductor device by reducing the half width of the light emission peak appearing in the light emission spectrum by improving the crystallinity of the well layer.
- the plane orientation of the main surface 1s is not less than ⁇ 3 ° and not more than 3 ° in the [0001] direction with respect to any one of the ⁇ 10-10 ⁇ plane, the ⁇ 11-20 ⁇ plane, and the ⁇ 21-30 ⁇ plane. It may have an inclination angle.
- the inclination angle in the [0001] direction is preferably ⁇ 2 ° or more and ⁇ 0.1 ° or less or 0.1 ° or more and 2 ° or less.
- the concentration of oxygen present on main surface 1s is 2 atomic% or more and 16 atomic% or less.
- the oxygen existing on the main surface 1s means oxygen taken in by the main surface 1s being oxidized, oxygen attached to the main surface 1s, and the like.
- the concentration of oxygen present on main surface 1s of group III nitride crystal substrate 1 is lower than 2 atomic%, the gap between the crystal substrate in the formed semiconductor device and the semiconductor layer formed by epitaxial growth on the crystal substrate. The interface resistance increases, and the integrated intensity of light emission decreases.
- the concentration of oxygen present on the main surface 1s of the crystal substrate is higher than 16 atomic%, the crystallinity of the semiconductor layer epitaxially grown on the main surface of the crystal substrate is lowered, so that the integrated intensity of light emission is lowered.
- the concentration of oxygen present on the main surface 1s is more preferably 3 atomic percent or more and 10 atomic percent or less.
- the concentration of oxygen present on the main surface is measured by AES (Auger atomic spectroscopy), XPS (X-ray photoelectron spectroscopy), or the like.
- oxygen present on the main surface 1s in the present invention is taken into the main surface 1s by oxygen adhering to the main surface 1s and oxidation of the crystal substrate.
- dislocation density on main surface 1s is 1 ⁇ 10 7 cm ⁇ 2 or less for group III nitride crystal substrates 1 of the above-described first to third embodiments.
- the dislocation density at the main surface of the crystal substrate is higher than 1 ⁇ 10 7 cm ⁇ 2 , the crystallinity of the semiconductor layer epitaxially grown on the main surface of the crystal substrate is lowered, so that the integrated intensity of light emission is lowered.
- the dislocation density on the main surface 1s is more preferably 1 ⁇ 10 6 cm ⁇ 2 or less, and further preferably 1 ⁇ 10 5 cm ⁇ 2 or less. From the viewpoint of increasing cost and efficiency in the production of semiconductor devices, the dislocation density on the main surface 1s is preferably 1 ⁇ 10 2 cm ⁇ 2 or more.
- the diameter of the group III nitride crystal substrate is preferably 40 mm or more, more preferably 50 mm or more, and even more preferably 75 mm or more.
- the diameter of the substrate is large, the number of devices that can be manufactured from one substrate increases.
- the diameter of the base substrate can be increased, a thick crystal can be grown, cut out at a desired angle, and processed.
- a plurality of substrates of group III nitride crystals having a small diameter are arranged so that their side surfaces are adjacent to each other, and a group III nitride crystal is grown on the main surface of each of the plurality of substrates.
- the group III nitride crystals are bonded to each other and grown as a single crystal, and the obtained group III nitride crystal can be processed into a large-diameter group III nitride crystal substrate.
- the diameter of the group III nitride crystal substrate is preferably 150 mm or less, and more preferably 100 mm or less.
- the shape of the main surface of the group III nitride crystal substrate is not limited to a circle as long as it has a size capable of manufacturing a device, and may be a polygon such as a rectangle.
- the length of the shortest side is preferably 5 mm or more and more preferably 10 mm or more from the viewpoint of increasing the cost and efficiency in the production of semiconductor devices. Further, from the viewpoint of improving shape accuracy such as reducing warpage and thickness distribution, the length of the longest side is preferably 150 mm or less, and more preferably 100 mm or less.
- the main surface is, for example, 5 mm ⁇ 15 mm, 10 mm ⁇ 10 mm, 10 mm ⁇ 30 mm, 18 mm ⁇ 18 mm, 30 mm ⁇ 50 mm.
- the impurity (dopant) added to the group III nitride crystal substrate is not particularly limited, but the following are preferably used from the viewpoint of producing a conductive substrate and an insulating substrate.
- the specific resistance is 5 ⁇ 10 ⁇ 5 ⁇ ⁇ cm or more and 0.5 ⁇ ⁇ cm or less (preferably 5 ⁇ 10 ⁇ 4 ⁇ ⁇ cm or more and 0.05 ⁇ ⁇ cm or less), and the carrier concentration is 1 ⁇ 10 16 cm ⁇ 3 or more and 1 In an n-type conductive substrate within the range of ⁇ 10 20 cm ⁇ 3 or less (preferably 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less), the crystallinity is maintained and the desired range is maintained.
- the impurity added to the substrate is preferably O or Si.
- the impurities added to the substrate are preferably C and Fe.
- the specific resistance of the substrate can be measured by a four-probe method, a two-probe method, or the like.
- the carrier concentration of the substrate can be measured by a Hall measurement method, a CV measurement method, or the like.
- the manufacturing method of the group III nitride crystal substrate of the above-described first to third embodiments is not particularly limited.
- a step of growing a group III nitride crystal, a group III nitride crystal, The crystal body is cut from a plane including the c-axis in the [0001] direction by cutting out a plurality of planes parallel to a plane having an inclination angle ⁇ in the [0001] direction from the plane including the c-axis to ⁇ 10 ° to 10 °.
- the production method of the group III nitride crystal is not particularly limited, and includes a vapor phase growth method such as an HVPE (hydride vapor phase growth) method and a sublimation method, a liquid phase growth method such as a flux method and an ammonothermal method.
- a vapor phase growth method such as an HVPE (hydride vapor phase growth) method and a sublimation method
- a liquid phase growth method such as a flux method and an ammonothermal method.
- an HVPE method, a flux, an ammonothermal method, or the like is preferably used for manufacturing a GaN crystal
- an HVPE method, a sublimation method, or the like is preferably used for manufacturing an AlN crystal.
- the HVPE method or the like is preferably used for the production of the AlGaN crystal body and the InGaN crystal body.
- group III nitride crystal In the production of the above group III nitride crystal, there is no particular limitation on the base substrate, but a group III nitride crystal with high crystallinity and small crystal lattice mismatch with the group III nitride crystal is grown. From the point of view, a GaAs substrate, a sapphire substrate, a SiC substrate, or the like is preferably used.
- the group III nitride crystal produced as described above has a plurality of parallel parallel to a plane having an inclination angle ⁇ in the [0001] direction from the plane including the c-axis of the crystal to ⁇ 10 ° to 10 °.
- Various cutting methods such as a wire saw, an inner peripheral blade, an outer peripheral blade, laser processing, electric discharge processing, and a water jet, can be used.
- the main surface processing method for flattening the main surface of the group III nitride crystal substrate formed as described above and reducing the work-affected layer is not particularly limited, but both the surface roughness and the work-affected layer are reduced. From the viewpoint of reduction, it is preferable to perform chemical mechanical polishing (CMP) after mechanical processing of either grinding or mechanical polishing.
- CMP chemical mechanical polishing
- the main surface can be modified by annealing before the semiconductor layer is epitaxially grown. Annealing before the growth of the semiconductor layer rearranges the crystals in the surface layer of the crystal substrate, thereby enabling the epitaxial growth of the semiconductor layer with good crystallinity.
- the relationship between the pH value X and the oxidation-reduction potential value Y (mV) has the following formulas (2) and (3): Y ⁇ ⁇ 50X + 1400 (2) Y ⁇ ⁇ 50X + 1700 (3) Is preferably satisfied.
- Y ⁇ 50X + 1400 the polishing rate becomes low, and the mechanical load during CMP increases, so that the surface quality of the group III nitride crystal substrate decreases.
- Y> ⁇ 50X + 1700 the corrosive action on the polishing pad and the polishing apparatus becomes large, and stable polishing becomes difficult.
- acids such as hydrochloric acid, sulfuric acid, and nitric acid, and alkalis such as KOH and NaOH are added to the CMP slurry, but these acids and / or alkali alone oxidize the surface of chemically stable gallium nitride.
- alkalis such as KOH and NaOH
- the oxidizing agent added to the CMP slurry is not particularly limited, but from the viewpoint of increasing the polishing rate, chlorinated isocyanuric acid such as hypochlorous acid and trichloroisocyanuric acid, and chlorinated isocyanuric acid such as sodium dichloroisocyanurate.
- chlorinated isocyanuric acid such as hypochlorous acid and trichloroisocyanuric acid
- chlorinated isocyanuric acid such as sodium dichloroisocyanurate.
- Salt permanganate such as potassium permanganate, dichromate such as potassium dichromate, bromate such as potassium bromate, thiosulfate such as sodium thiosulfate, nitric acid, sulfuric acid, hydrochloric acid, hydrogen peroxide water Ozone and the like are preferably used.
- these oxidizing agents may be used independently or may use 2 or more together.
- the pH of the CMP slurry is preferably 6 or less or 8 or more.
- the polishing rate can be increased by bringing an acidic slurry having a pH of 6 or less or a basic slurry having a pH of 8 or more into contact with the group III nitride crystal and etching away the work-affected layer of the group III nitride crystal.
- the pH of the slurry is more preferably 4 or less or 10 or more.
- the acid and base used to adjust the pH of the slurry for example, inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, formic acid, acetic acid, oxalic acid, citric acid, malic acid, tartaric acid
- inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, formic acid, acetic acid, oxalic acid, citric acid, malic acid, tartaric acid
- organic acids such as succinic acid, phthalic acid, and fumaric acid
- bases such as KOH, NaOH, NH 4 OH, and amines, salts of the above inorganic acids or organic acids, and salts such as carbonates can be used.
- pH can also be adjusted by addition of the said oxidizing agent.
- the CMP slurry preferably contains abrasive grains from the viewpoint of increasing the polishing rate.
- the polishing rate can be further increased by the abrasive grains.
- the abrasive grains included in the slurry are not particularly limited, and low-hardness abrasive grains having a hardness lower than the hardness of the group III nitride crystal substrate can be used. By using low-hardness abrasive grains, the surface roughness of the main surface of the crystal substrate and the work-affected layer can be reduced.
- the low-hardness abrasive grains are not particularly limited as long as they are abrasive grains having a hardness lower than the hardness of the group III nitride crystal as the object to be polished, but SiO 2 , CeO 2 , TiO 2 , MgO, MnO 2 Fe 2 O 3 , Fe 3 O 4 , NiO, ZnO, CoO, Co 3 O 4 , CuO, Cu 2 O, GeO 2 , CaO, Ga 2 O 3 , In 2 O 3 Abrasive grains containing two materials are preferred.
- the abrasive grains are not limited to oxides containing a single metal element, but are oxides containing two or more metal elements (for example, those having a structure such as ferrite, perovskite, spinel or ilmenite). Also good. Also, nitrides such as AlN, GaN and InN, carbonates such as CaCO 3 and BaCO 3 , metals such as Fe, Cu, Ti and Ni, and carbon (specifically, carbon black, carbon nanotube, C60, etc.) It can also be used.
- the abrasive grains are secondary particles bonded with primary particles. It is preferable.
- the ratio (D 2 / D 1 ratio) of the average particle diameter D 2 of the secondary particles to the average particle diameter D 1 of the primary particles is preferably 1.6 or more, and the average particle diameter D 2 of the secondary particles is It is preferably 200 nm or more, and the shape of the secondary particles is preferably at least one of a saddle shape, a block shape, and a chain shape, and the primary particles are chemically formed of fumed silica or colloidal silica.
- SiO 2 abrasive grains that are bonded secondary particles are preferred.
- the primary particle diameter can be evaluated from the adsorption specific surface area by the gas adsorption method, and the secondary particles can be evaluated by the dynamic light scattering method.
- the CMP slurry does not contain abrasive grains from the viewpoint of reducing uniform distortion, non-uniform distortion and / or plane orientation deviation of the surface layer of the group III nitride crystal substrate and further reducing the surface roughness.
- the pH value X and the oxidation-reduction potential value Y (mV) in the slurry used for CMP are 1.2 ⁇ 10 ⁇ 6 m or more and 1.8 ⁇ 10 ⁇ 6 m or less.
- the contact coefficient C is more preferably 1.4 ⁇ 10 ⁇ 6 m or more and 1.6 ⁇ 10 ⁇ 6 m or less.
- the contact coefficient C is expressed by the following formula using the viscosity of the slurry as ⁇ (unit: mPa ⁇ s), the peripheral speed V (unit: m / s) in CMP, and the pressure P (unit: kPa) in CMP. 5)
- C ⁇ ⁇ V / P (5) It is expressed as
- the contact coefficient C of the slurry is smaller than 1.2 ⁇ 10 ⁇ 6 m, the load on the group III nitride crystal substrate is increased in CMP, so that the surface layer of the group III nitride crystal substrate is uniformly strained and non-uniform. Distortion and / or plane orientation deviation increases.
- the polishing rate decreases, so that the surface roughness of the main surface of the group III nitride crystal substrate, the uniform strain of the surface layer, the nonuniform strain and / Or misorientation increases.
- the viscosity of the slurry can be adjusted by adding a high-viscosity organic compound such as ethylene glycol or an inorganic compound such as boehmite, and can be measured using a B-type viscometer, Ostwald-type viscometer, or the like.
- a group III nitride crystal was further grown on the main surface 1s of the group III nitride crystal substrate 1 of one or more of the first to third embodiments obtained as described above, and was grown.
- a group III nitride crystal substrate is produced by cutting a group III nitride crystal in a plane parallel to the main surface 1s of the crystal substrate, and the main surface of the group III nitride crystal substrate is surface-treated in the same manner as described above. As a result, the Group III nitride crystal substrates of Embodiments 1 to 3 can be further manufactured.
- the group III nitride crystal substrate used as the base substrate for the further growth (repeated growth) of the group III nitride crystal is not necessarily a single crystal substrate, and a plurality of small size crystal substrates may be used. . It can be joined to form a single crystal during repeated growth. A large-diameter group III nitride crystal substrate can be obtained by bonding during repeated growth. Further, a crystal substrate cut out from a group III nitride crystal bonded by repeated growth can be used as a base substrate and can be repeatedly grown again. Thus, the production cost can be reduced by repeatedly using the group III nitride crystal for growth.
- the method for further growing the group III nitride crystal on the main surface 1s of the group III nitride crystal substrate 1 of the first to third embodiments is not particularly limited, and includes an HVPE method, a sublimation method, and the like.
- a liquid phase growth method such as a vapor phase growth method, a flux method, or an ammonothermal method is preferably used.
- an HVPE method, a flux method, an ammonothermal method, or the like is preferably used for manufacturing a GaN crystal
- an HVPE method, a sublimation method, or the like is preferably used for manufacturing an AlN crystal.
- the HVPE method or the like is preferably used for the production of the AlGaN crystal and the InGaN crystal.
- Group III nitride crystal substrate with epi layer Referring to FIG. 10, one embodiment of a group III nitride crystal substrate with an epi layer according to the present invention is formed by epitaxial growth on main surface 1s of group III nitride crystal substrate 1 of embodiments 1 to 3. And at least one semiconductor layer 2.
- the semiconductor layer 2 is epitaxially grown on the main surface 1s of the group III nitride crystal substrate 1, and therefore the plane orientation of the main surface 2s of the semiconductor layer 2 Is the same as the plane orientation of the main surface 1 s of the group III nitride crystal substrate 1.
- the plane orientation of the main surface 1s of the group III nitride crystal substrate 1 of the first to third embodiments has an inclination angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane 1v including the c-axis 1c
- the plane orientation of the main surface 2s of the semiconductor layer 2 has an inclination angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane including the c-axis.
- a physical crystal substrate is obtained.
- vapor phase growth such as MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxy) method, etc.
- MOCVD metal organic chemical vapor deposition
- MBE molecular beam epitaxy
- one embodiment of a semiconductor device according to the present invention includes a group III nitride crystal substrate 3 with an epi layer according to a fourth embodiment.
- the plane orientation of the main surface 1s is ⁇ 10 ° or more and 10 ° or less in the [0001] direction from the plane including the c-axis.
- the characteristics of the semiconductor device of this embodiment are enhanced.
- the piezoelectric polarization is suppressed and the quantum confined Stark effect is suppressed, so that the blue shift of light emission is suppressed and the light emission intensity is improved. Therefore, the light emitting layer 210 that emits light having a peak wavelength of 430 nm or more and 550 nm or less with high efficiency can be formed in the semiconductor layer 2.
- the emission intensity of light in the green region having a wavelength of 500 nm to 550 nm is significantly improved.
- the semiconductor device of the present embodiment includes a group III nitride crystal substrate 3 with an epi layer of the fourth embodiment.
- Epi-layer III-nitride crystal substrate 3 has a tilt angle of ⁇ 10 ° or more and 10 ° or less in the [0001] direction from the plane including the c-axis of the main surface 1s.
- a group nitride crystal substrate 1 is included.
- the epitaxial layer group III nitride crystal substrate 3 is an n-type layer having a thickness of 1000 nm which is sequentially formed as at least one semiconductor layer 2 on one main surface 1s of the group III nitride crystal substrate 1.
- GaN layer 202 n-type In x1 Al y1 Ga 1-x1-y1 N (0 ⁇ x1, 0 ⁇ y1, x1 + y1 ⁇ 1) cladding layer 204 having a thickness of 1200 nm, n-type GaN guide layer 206 having a thickness of 200 nm, thickness 65 nm thick undoped In x2 Ga 1 -x2 N (0 ⁇ x2 ⁇ 1) guide layer 208, 15 nm thick GaN barrier layer and 3 nm thick In x3 Ga 1 -x3 N (0 ⁇ x3 ⁇ 1) well
- a light emitting layer 210 having a three-period MQW (multiple quantum well) structure composed of layers, an undoped In x4 Ga 1-x4 N (0 ⁇ x4 ⁇ 1) guide layer 222 having a thickness of 65 nm, and a p having a thickness of 20 nm -type Al x5 Ga 1-x5 N ( ⁇ X5 ⁇ 1) blocking layer
- a 300 nm thick SiO 2 insulating layer 300 is partially formed on the p-type GaN contact layer 230, and the p-side electrode 400 is formed on the exposed p-type GaN contact layer 230 and a part of the SiO 2 insulating layer 300. Is formed.
- An n-side electrode 500 is formed on the other main surface of group III nitride crystal substrate 1.
- a semiconductor device manufacturing method includes a step of preparing group III nitride crystal substrates of embodiments 1 to 3, and at least a main surface 1s of the crystal. Forming a group III nitride crystal substrate with an epi layer by growing one semiconductor layer 2. With this manufacturing method, a semiconductor device having high characteristics in which the quantum confined Stark effect due to piezoelectric polarization of the semiconductor layer is suppressed can be obtained.
- the inclusion of the light emitting layer 210 in the semiconductor layer 2 suppresses the quantum confined Stark effect due to piezoelectric polarization of the light emitting layer 210, thereby suppressing the blue shift of light emission and light emission (for example, the peak wavelength is 430 nm or more and 550 nm).
- a light emitting device having a high integrated intensity of the following light emission is obtained.
- group III nitride crystal substrate 1 of embodiments 1 to 3 is first prepared. Preparation of group III nitride crystal substrate 1 is as described in [Group III nitride crystal substrate] and [Method of manufacturing group III nitride crystal substrate], and will not be repeated.
- At least one semiconductor layer 2 is grown on the main surface 1s of the prepared group III nitride crystal substrate 1 to form a group III nitride crystal substrate 3 with an epi layer.
- the growth method of the semiconductor layer 2 is not particularly limited, but from the viewpoint of epitaxially growing a semiconductor layer with high crystallinity, vapor phase growth such as MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxy) method, etc. The method is preferably used.
- n-type GaN layer 202 having a thickness of 1000 nm and n-type In x1 having a thickness of 1200 nm are formed by, for example, MOCVD.
- a 300 nm thick SiO 2 insulating layer 300 is formed on the p-type GaN contact layer 230 by vapor deposition.
- a stripe window having a width of 10 ⁇ m is formed by photolithography and wet etching.
- a laser stripe is provided parallel to the direction in which the ⁇ 0001> direction axis (c-axis) is projected onto the main surface of the semiconductor layer.
- a Ni / Au electrode is formed as a p-side electrode 400 on the stripe window and a part of the SiO 2 insulating layer 300 by vapor deposition.
- a Ti / Al / Ti / Au electrode is formed as the n-side electrode 500 on the other main surface of the group III nitride crystal substrate by vapor deposition.
- Example I Production of Group III Nitride Crystal Using a GaAs crystal substrate having a diameter of 50 mm as a base substrate, a GaN crystal (group III nitride crystal) having a thickness of 50 mm was grown by the HVPE method. That is, by heating a boat containing metal Ga to 800 ° C. in an atmospheric pressure HVPE reactor and introducing a mixed gas of HCl gas and carrier gas (H 2 gas) into the boat, Reaction with HCl gas produced GaCl gas. At the same time, by introducing a mixed gas of NH 3 gas and carrier gas (H 2 gas) into the HVPE reactor, GaCl gas and NH 3 gas are reacted to form GaAs installed in the HVPE reactor.
- a mixed gas of HCl gas and carrier gas H 2 gas
- a GaN crystal was grown on a crystal substrate (underlying substrate).
- the growth temperature of the GaN crystal was 1050 ° C.
- the HCl gas partial pressure in the HVPE reactor was 2 kPa
- the NH 3 gas partial pressure was 30 kPa.
- GaN crystal (Group III nitride crystal) obtained above is tilted between ⁇ 10 ° and 10 ° in the [0001] direction with respect to the plane including the c-axis.
- a GaN crystal substrate (group III nitride crystal substrate) having the main surface shown in Table 1 was manufactured by slicing along a plane parallel to the plane having ⁇ .
- the sign is positive
- the inclination angle ⁇ indicates that the plane orientation of the main surface is inclined in the [0001] direction (that is, toward the (0001) plane) from the plane including the c-axis.
- group III nitride crystal substrate The main surface of the GaN crystal substrate (group III nitride crystal substrate) obtained above is lapped (mechanically polished), and then subjected to CMP (chemical mechanical polishing) to produce a semiconductor.
- a GaN crystal substrate for devices was obtained.
- three types of diamond abrasive grains having an abrasive grain size of 2 ⁇ m, 3 ⁇ m, and 9 ⁇ m are prepared, and the grain size of the diamond abrasive grains is gradually reduced using a copper surface plate or a tin surface plate. I went.
- CMP includes colloidal silica (primary particle size is 90 nm, secondary particle size is 210 nm) in which primary particles are chemically bonded as abrasive grains to form secondary particles, tartaric acid as a pH regulator, Using a slurry containing trichloroisocyanuric acid as an oxidizing agent and adjusting the pH and redox potential (ORP) to the values shown in Table 1, the contact coefficient C was adjusted to the values shown in Table 1.
- the X-ray penetration depth was controlled by changing at least one of the X-ray incident angle ⁇ with respect to the crystal surface, the tilt angle ⁇ of the crystal surface, and the rotation angle ⁇ within the crystal surface. From the viewpoint of facilitating the evaluation by X-ray diffraction at the X-ray penetration depth, in Examples I-1 and I-2, the (10-13) plane is used as the specific parallel crystal lattice plane. In 13 to I-15, the (10-11) plane was used as the specific parallel crystal lattice plane.
- the specific resistance of another GaN crystal substrate obtained by the same manufacturing method and surface processing method as in this example was 1 ⁇ 10 ⁇ 2 ⁇ ⁇ cm as measured by the four-probe method, and its carrier The concentration was 2 ⁇ 10 18 cm ⁇ 3 as measured by the Hall measurement method.
- At least one semiconductor layer is formed by MOCVD on one main surface 1s of a GaN crystal substrate (Group III nitride crystal substrate 1) for a semiconductor device obtained above.
- a GaN crystal substrate Group III nitride crystal substrate 1
- a 300 nm thick SiO 2 insulating layer 300 was formed on the p-type GaN contact layer 230 by vapor deposition.
- a stripe window having a width of 10 ⁇ m was formed by photolithography and wet etching.
- a laser stripe is provided parallel to the direction in which the ⁇ 10-10> direction axis (m-axis) is projected onto the main surface of the semiconductor layer, and in other examples, the ⁇ 0001> direction axis ( A laser stripe was provided in parallel to the direction projected on the main surface of the semiconductor layer.
- a Ni / Au electrode was formed as the p-side electrode 400 on the stripe window and a part of the SiO 2 insulating layer 300 by vapor deposition.
- the other main surface of the GaN crystal substrate (Group III nitride crystal substrate 1) was mirror-finished by lapping (mechanical polishing).
- a Ti / Al / Ti / Au electrode was formed as the n-side electrode 500 by vapor deposition on the mirror-finished main surface of the GaN crystal substrate.
- the thickness and thickness of each layer of the wafer were measured using a contact film thickness meter or by observing the wafer cross section including the substrate using an optical microscope or SEM (scanning electron microscope).
- a laser scriber using a YAG laser having a peak wavelength of 355 nm was used for manufacturing the resonator mirror for the laser stripe.
- the conditions for forming the scribe grooves were a laser beam output of 100 mW and a scanning speed of 5 mm / s.
- the formed scribe groove was, for example, a groove having a length of 30 ⁇ m, a width of 10 ⁇ m, and a depth of 40 ⁇ m.
- a scribe groove was formed by directly irradiating the main surface of the semiconductor layer with a laser beam through an insulating film opening portion of the substrate at a pitch of 800 ⁇ m.
- the resonator length was 600 ⁇ m.
- a resonant mirror was prepared by cleaving.
- a laser bar was produced by breaking on the back side of the substrate by pressing.
- a dielectric multilayer film was coated on the end face of the laser bar by vacuum deposition.
- the dielectric multilayer film was formed by alternately laminating SiO 2 and TiO 2 .
- the film thickness was adjusted in the range of 50 nm to 100 nm, respectively, so that the peak wavelength of the reflectance was in the range of 500 nm to 530 nm.
- the reflection surface of one end face was set to 10 periods, the design value of reflectivity was designed to about 95%, the reflection surface of the other end face was set to 6 periods, and the design value of reflectivity was about 80%.
- the semiconductor device obtained as described above was evaluated by energization at room temperature (25 ° C.) as follows.
- a pulse power source having a pulse width of 500 ns and a duty ratio of 0.1% was used to energize the surface electrode by dropping a needle.
- the current density was 100 A / cm 2 .
- the LED mode light was observed by placing an optical fiber on the main surface side of the laser bar and measuring the emission spectrum emitted from the main surface.
- Table 1 shows the integrated intensities of emission peaks in the wavelength range of 500 nm to 550 nm of the emission spectrum of LED mode light.
- Table 1 summarizes the full width at half maximum of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light.
- the laser beam was observed by placing an optical fiber on the end face side of the laser bar and measuring the emission spectrum emitted from the end face.
- the emission peak wavelength of the LED mode light was 500 nm to 550 nm.
- the oscillation peak wavelength of the laser beam was 500 nm to 530 nm.
- the surface layer has a uniform strain of 1.7 ⁇ 10 ⁇ 3 or less, the surface layer has a non-uniform strain of 110 arcsec or less, and / or a specific parallel crystal of the surface layer.
- the plane orientation deviation of the lattice plane is 300 arcsec or less and the plane orientation of the main surface has an inclination angle of ⁇ 10 ° or more and 10 ° or less in the [0001] direction from the plane including the c-axis, such a crystal
- the integrated intensity of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using the substrate was increased.
- Example I-2 the blue shift was evaluated from the measurement of the emission wavelength of LED mode light at current densities of 1 A / cm 2 and 100 A / cm 2 , respectively.
- the blue shift in Example I-2 was 40 nm
- the blue shift in Example I-8 was 10 nm
- the blue shift in Example I-18 was 8 nm.
- the uniform distortion of the surface layer is 1.7 ⁇ 10 ⁇ 3 or less
- the nonuniform distortion of the surface layer is 110 arcsec or less
- / or the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer is 300 arcsec.
- the blue of a semiconductor device using such a crystal substrate is used.
- the shift was very small.
- Example II CMP includes colloidal silica (primary particle diameter is 15 nm, secondary particle diameter is 40 nm) in which primary particles are chemically bonded as abrasive grains as primary particles, and malic acid and oxidation are used as pH regulators. Except for adjusting the contact coefficient C to the value shown in Table 2 using a slurry containing trichloroisocyanuric acid as the agent and adjusting the pH and redox potential (ORP) to the values shown in Table 2.
- Example I which manufactures a GaN crystal substrate (Group III nitride crystal substrate) and a semiconductor device, and the surface layer of the surface processed GaN crystal substrate has uniform strain, nonuniform strain, and crystal lattice plane
- the integrated intensity and half width of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device were measured.
- the (10-11) plane was used as the specific parallel crystal lattice plane. The results are summarized in Table 2.
- the plane orientation of the main surface has a tilt angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane including the c-axis.
- the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate has a wavelength of 500 nm to 550 nm. The integrated intensity of the emission peak in the range increased.
- Example III The surface orientation of the main surface of the GaN crystal substrate (group III nitride crystal substrate) is set to a tilt angle ⁇ from the (21-30) plane, which is one of the planes including the c-axis, of 0.2, and CMP is applied to abrasive grains.
- spherical colloidal silica particle size shown in Table 3 (excluding abrasive grains in Example III-1), sodium tartrate and sodium carbonate as pH adjusters, and sodium dichloroisocyanurate as oxidants.
- Example I except that the contact coefficient C was adjusted to the value shown in Table 3 using the slurry having the pH and redox potential (ORP) adjusted to the values shown in Table 3.
- a GaN crystal substrate group III nitride crystal substrate
- a semiconductor device is manufactured, and the surface layer of the surface-processed GaN crystal substrate has uniform strain, non-uniform strain, and crystal plane misalignment.
- integrated intensities and half-value width of the emission peak in the wavelength range of 500 nm ⁇ 550 nm of the emission spectrum of the LED-mode light from the semiconductor device are summarized in Table 3.
- the uniform distortion of the surface layer is 1.7 ⁇ 10 ⁇ 3 or less
- the nonuniform distortion of the surface layer is 110 arcsec or less
- / or the specific parallel crystal of the surface layer
- the plane orientation deviation of the lattice plane is 300 arcsec or less and the plane orientation of the main surface has an inclination angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane including the c-axis
- the surface roughness Ra, Ry decreases, the integrated intensity of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate increases.
- Example IV The plane orientation of the main surface of the GaN crystal substrate (Group III nitride crystal substrate) is the plane orientation of the main surface, and the tilt angle ⁇ from the (21-30) plane, which is one of the planes including the c-axis, is 0.2. , Including colloidal silica (primary particle diameter is 35 nm, secondary particle diameter is 70 nm) in which primary particles are chemically bonded as secondary particles as abrasive grains, and nitric acid and oxidation are used as pH regulators.
- colloidal silica primary particle diameter is 35 nm
- secondary particle diameter is 70 nm
- Example 4 Using a slurry containing hydrogen peroxide water and trichloroisocyanuric acid as agents and adjusting the pH and redox potential (ORP) to the values shown in Table 4, the contact coefficient C was adjusted to the values shown in Table 4.
- a GaN crystal substrate group III nitride crystal substrate
- a semiconductor device were manufactured and the surface layer of the surface processed GaN crystal substrate was uniformly strained and non-uniform.
- Strain and crystal lattice plane With evaluating the position deviation was measured integrated intensities and half-value width of the emission peak in the wavelength range of 500 nm ⁇ 550 nm of the emission spectrum of the LED-mode light from the semiconductor device.
- the (10-11) plane was used as the specific parallel crystal lattice plane in Examples IV-1 to IV-7. The results are summarized in Table 4.
- the surface layer has a uniform strain of 1.7 ⁇ 10 ⁇ 3 or less, the surface layer has a non-uniform strain of 110 arcsec or less, and / or a specific parallel crystal of the surface layer.
- the plane orientation deviation of the lattice plane is 300 arcsec or less, and the plane orientation of the main surface has an inclination angle of ⁇ 10 ° or more and 10 ° or less in the [0001] direction from the plane including the c-axis.
- the concentration of oxygen present on the main surface was measured by AES (Auger atomic spectroscopy), and when it was 2 atomic% or more and 16 atomic% or less, emission of LED mode light of a semiconductor device using such a crystal substrate The integrated intensity of the peak increased.
- Example V Production of Group III Nitride Crystal and Group III Nitride Crystal Substrate
- the plane orientation of the main surface produced in Example I-4 of Example I as the base substrate was (10-10
- the GaN crystal body was grown by the flux method using the GaN crystal substrate (Group III nitride crystal substrate). That is, a GaN crystal substrate (underlying substrate), metal Ga as a Ga raw material, and metal Na as a flux were accommodated in a crucible so that Ga: Na was 1: 1 in terms of molar ratio. Subsequently, the crucible was heated to obtain an 800 ° C. Ga—Na melt in contact with the (10-10) main surface of the GaN crystal substrate.
- the growth by the HVPE method was carried out by using a GaN crystal substrate (Group III) having a surface orientation of (10-10) of the main surface produced in Example I-4 of Example I as a base substrate.
- a GaN crystal substrate having a thickness of 5 mm was grown by HVPE.
- the growth conditions of the GaN crystal by the HVPE method were the same as in Example I.
- the dislocation density decreased.
- the dislocation density of the main surface of the GaN crystal substrate was adjusted by the difference in the position of the GaN crystal substrate taken from the GaN crystal (see Table 5).
- the contact coefficient C is a value shown in Table 2 using a slurry that contains citric acid as a pH adjuster, potassium permanganate as an oxidizing agent, and adjusted to pH and redox potential (ORP) values shown in the table.
- a GaN crystal substrate for a semiconductor device was obtained by surface-treating a GaN crystal substrate (Group III nitride crystal substrate) in the same manner as in Example I except that the adjustment was performed so that The uniform strain and non-uniform strain of the surface layer of the GaN crystal substrate for semiconductor devices (surface-processed GaN crystal substrate) thus obtained were evaluated in the same manner as in Example I.
- the surface layer has a uniform strain of 1.7 ⁇ 10 ⁇ 3 or less, the surface layer has a non-uniform strain of 110 arcsec or less, and / or a specific parallel crystal of the surface layer.
- the plane orientation deviation of the lattice plane is 300 arcsec or less, and the plane orientation of the main surface has an inclination angle of ⁇ 10 ° or more and 10 ° or less in the [0001] direction from the plane including the c-axis.
- the dislocation density on the main surface of the group III nitride crystal substrate for example, the dislocation density is 1 ⁇ 10 7 cm ⁇ 2 or less, 1 ⁇ 10 6 cm ⁇ 2 or less, and further 1 ⁇ 10 5 cm ⁇ 2.
- the integrated intensity of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate increased. Even when a plurality of GaN crystal substrates were used as the base substrate and a single GaN crystal joined from the base substrate was grown by the flux method or the HVPE method, the same result as above was obtained. .
- Example VI CMP includes spherical colloidal silica (particle size: 30 nm) as abrasive grains, hydrochloric acid as a pH regulator, hydrogen peroxide and hypochlorous acid as oxidizing agents, pH, redox potential (ORP) and viscosity
- slurry was adjusted to the values shown in Table 6 and the CMP peripheral speed, the CMP pressure, and the contact coefficient C were adjusted to the values shown in Table 6.
- a GaN crystal substrate (Group III nitride crystal substrate) was surface processed.
- the pH value X and the redox potential value Y (mV) are ⁇ 50X + 1400 ⁇ Y ⁇ ⁇ 50X + 1700
- CMP is performed so that the contact coefficient C is 1.2 ⁇ 10 ⁇ 6 m or more and 1.8 ⁇ 10 ⁇ 6 m or less, so that the surface orientation of the main surface is Even in a group III nitride crystal substrate having a tilt angle of ⁇ 10 ° to 10 ° in the [0001] direction from the plane including the c-axis, the surface layer has a uniform strain of 1.7 ⁇ 10 ⁇ 3 or less.
- the nonuniform strain of the surface layer may be 110 arcsec or less, and / or the plane orientation deviation of the specific parallel crystal lattice plane ((11-22) plane or (10-11) plane) of the surface layer may be 300 arcsec or less. did it.
- the oxidation-reduction potential ORP
- the action of oxidizing the main surface of the group III nitride crystal substrate becomes weak, so the mechanical action during CMP becomes strong, and the surface of the group III nitride crystal substrate becomes strong.
- the uniform strain, non-uniform strain and plane orientation deviation of the layer increased.
- the oxidation-reduction potential was high, stable polishing became difficult, and uniform distortion, non-uniform distortion, and plane orientation deviation of the surface layer of the group III nitride crystal substrate increased.
- Example VII A GaN crystal substrate (group III nitride crystal substrate) having a tilt angle of 0.2 ° in the [0001] direction from the (21-30) plane of the main surface produced in Example III-4 was cut to 5 mm. A plurality of small piece substrates having a size of ⁇ 20 mm to 5 mm ⁇ 45 mm were obtained. A plurality of such small-piece substrates have their main surfaces (all of which have an inclination angle of 0.2 ° in the [0001] direction from the (21-30) plane).
- a GaN crystal (Group III nitride crystal) is grown by HVPE on each of the main surfaces of the small substrate.
- the group III nitride crystals were joined to each other and the outer peripheral portion was processed to obtain a GaN crystal (group III nitride crystal) of a desired size.
- the obtained GaN crystal was cut out parallel to the main surface of the base substrate, and in the same manner as in Example III-4, a GaN crystal substrate and a semiconductor device of 18 mm ⁇ 18 mm, 30 mm ⁇ 50 mm, diameter 40 mm, diameter 100 mm, diameter 150 mm were manufactured. did.
- Both the GaN crystal substrate and the semiconductor device obtained substrate characteristics and device characteristics equivalent to those in Example III-4. Furthermore, using these GaN crystal substrates (group III nitride crystal substrates) as base substrates, the crystals were repeatedly grown by the HVPE method to obtain GaN crystals of 18 mm ⁇ 18 mm, 30 mm ⁇ 50 mm, 40 mm in diameter, 100 mm in diameter, and 150 mm in diameter ( Group III nitride crystals) were obtained. By processing this GaN crystal in the same manner as described above, a GaN crystal substrate and a semiconductor device having characteristics equivalent to those of Example III-4 were obtained.
- 1 Group III nitride crystal substrate 1c c-axis, 1d, 31d, 32d, 33d, 41d, 42d, 43d, 51d, 52d, 53d
- Specific parallel crystal lattice plane 1p surface layer, 1q surface adjacent layer, 1r inner layer, 1s , 2s main surface, plane including 1v c axis, 2 semiconductor layer, 3 group III nitride crystal substrate with epi layer, 4 semiconductor device, 11 incident X-ray, 12 outgoing X-ray, 21 ⁇ axis, 22 ⁇ axis (2 ⁇ Axis), 23 ⁇ axis, 30 tensile stress, 202 n-type GaN layer, 204 n-type In x1 Al y1 Ga 1-x1-y1 N clad layer, 206 n-type GaN guide layer, 208 In x2 Ga 1-x2 N guide Layer, 210 light emitting layer, 222 In x4 Ga 1-x4 N guide layer, 224 p-type Al x
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Abstract
Description
結晶幾何学においては、結晶系を記述するために結晶軸が設定される。III族窒化物結晶基板を形成するIII族窒化物結晶などの六方晶系の結晶においては、原点から同一平面上に互いに120°の角をなして3方向に広がるa1軸、a2軸およびa3軸、これらの3つの軸を含む平面に垂直なc軸が設定される。かかる結晶軸において、a1軸、a2軸、a3軸およびc軸の切片がそれぞれ1/h、1/k、1/iおよび1/lである結晶面の面方位は、(hkil)の表示(ミラー表示と呼ばれる)で表される。
図1、図2、図3AおよびB、ならびに図6を参照して、本発明の一実施形態であるIII族窒化物結晶基板1は、III族窒化物結晶基板1の任意の特定平行結晶格子面1d(各結晶格子の特定平行結晶格子面31d,32d,33dにより形成される特定平行結晶格子面1dをいう。本実施形態において、以下同じ。)のX線回折条件を満たしながら結晶基板の主表面1sからのX線侵入深さを変化させるX線回折測定から得られる特定平行結晶格子面1dの面間隔において、0.3μmのX線侵入深さにおける面間隔をd1(面間隔d1、以下同じ。)と表わし5μmのX線侵入深さにおける面間隔をd2(面間隔d2、以下同じ。)と表したときに|d1-d2|/d2の値で表される結晶基板の表面層1pの均一歪みが1.7×10-3以下であり、主表面1sの面方位が、結晶基板のc軸1cを含む面1vから[0001]方向に-10°以上10°以下の傾斜角αを有する。
図1、図2、図4AおよびB、ならびに図6を参照して、本発明の他の実施形態であるIII族窒化物結晶基板1は、III族窒化物結晶基板1の任意の特定平行結晶格子面1d(各結晶格子の特定平行結晶格子面41d,42d,43dにより形成される特定平行結晶格子面1dをいう。本実施形態において、以下同じ。)のX線回折条件を満たしながら結晶基板の主表面1sからのX線侵入深さを変化させるX線回折測定から得られる特定平行結晶格子面1dの回折強度プロファイルにおいて、0.3μmのX線侵入深さにおける回折強度ピークの半値幅v1と5μmのX線侵入深さにおける回折強度ピークの半値幅v2とから得られる|v1-v2|の値で表される結晶基板の表面層1pの不均一歪みが110arcsec以下であり、主表面1sの面方位が、結晶基板のc軸1cを含む面1vから[0001]方向に-10°以上10°以下の傾斜角αを有する。
図1、図2、図5AおよびB、ならびに図6を参照して、本発明の他の実施形態であるIII族窒化物結晶基板1は、III族窒化物結晶基板1の任意の特定平行結晶格子面1d(各結晶格子の特定平行結晶格子面51d,52d,53dにより形成される特定平行結晶格子面1dをいう。本実施形態において、以下同じ。)のX線回折に関して結晶基板の主表面1sからのX線侵入深さを変化させて測定されたロッキングカーブにおいて、0.3μmのX線侵入深さにおける回折強度ピークの半値幅w1と5μmのX線侵入深さにおける回折強度ピークの半値幅w2とから得られる|w1-w2|の値で表される結晶基板の表面層1pの特定平行結晶格子面の面方位ずれが300arcsec以下であり、主表面1sの面方位が、結晶基板のc軸1cを含む面1vから[0001]方向に-10°以上10°以下の傾斜角αを有する。
上記の実施形態1~実施形態3のIII族窒化物結晶基板の製造方法は、特に制限はないが、たとえば、III族窒化物結晶体を成長させる工程と、III族窒化物結晶体を、その結晶体のc軸を含む面から[0001]方向への傾斜角αが-10°以上10°以下の面に平行な複数の面で切り出すことにより、c軸を含む面から[0001]方向への傾斜角αが-10°以上10°以下の面の主表面を有するIII族窒化物結晶基板を形成する工程と、III族窒化物結晶基板の主表面を加工する工程と、を備えることができる。
III族窒化物結晶体の製造方法には、特に制限はなく、HVPE(ハイドライド気相成長)法、昇華法などの気相成長法、フラックス法、アモノサーマル法などの液相成長法などが好適に用いられる。たとえば、GaN結晶体の製造には、HVPE法、フラックス、アモノサーマル法などが好適に用いられ、AlN結晶体の製造には、HVPE法、昇華法などが好適に用いられ、InN結晶体、AlGaN結晶体およびInGaN結晶体の製造には、HVPE法などが好適に用いられる。
上記のようにして製造されたIII族窒化物結晶体を、その結晶体のc軸を含む面から[0001]方向への傾斜角αが-10°以上10°以下の面に平行な複数の面で切り出す方法には、特に制限はなく、ワイヤソー、内周刃、外周刃、レーザ加工、放電加工、ウォータージェットなどの各種切断方法を用いることができる。
上記のようにして形成されたIII族窒化物結晶基板の主表面を平坦化し加工変質層を低減するための主表面加工方法は、特に制限はないが、表面粗さおよび加工変質層の両方を低減する観点から、研削および機械的研磨のいずれかの機械的加工の後、CMP(化学機械的研磨)を行うことが好ましい。なお、III族窒化物結晶基板の加工変質層は完全に除去する必要はなく、半導体層をエピタキシャル成長させる前にアニール処理により主表面の改質を行うこともできる。半導体層成長前のアニールにより結晶基板の表面層における結晶の再配列が行なわれ、結晶性のよい半導体層のエピタキシャル成長が可能となる。
Y≧-50X+1400 (2)
Y≦-50X+1700 (3)
を満たしていることが好ましい。Y<-50X+1400であると、研磨速度が低くなり、CMP時の機械的な負荷が増加するために、III族窒化物結晶基板の表面品質が低下する。Y>-50X+1700であると、研磨パッドおよび研磨装置への腐食作用が大きくなり、安定した研磨が困難となる。
Y≧-50X+1500 (4)
の関係をも満たすことが好ましい。
C=η×V/P (5)
と表わされる。スラリーの接触係数Cが1.2×10-6mより小さい場合は、CMPにおいてIII族窒化物結晶基板への負荷が大きくなるため、III族窒化物結晶基板の表面層の均一歪み、不均一歪みおよび/または面方位ずれが大きくなる。スラリーの接触係数Cが1.8×10-6mより大きい場合は、研磨速度が低下するため、III族窒化物結晶基板の主表面の表面粗さ、表面層の均一歪み、不均一歪みおよび/または面方位ずれが大きくなる。なお、スラリーの粘度は、エチレングルコールなどの高粘度の有機化合物、ベーマイトなどの無機化合物の添加により調整することができ、B型粘度計、オストワルド型粘度計などにより測定できる。
(実施形態4)
図10を参照して、本発明にかかるエピ層付III族窒化物結晶基板の一実施形態は、実施形態1~実施形態3のIII族窒化物結晶基板1の主表面1s上にエピタキシャル成長により形成されている少なくとも1層の半導体層2を含む。
(実施形態5)
図11を参照して、本発明にかかる半導体デバイスの一実施形態は、実施形態4のエピ層付III族窒化物結晶基板3を含む。
図11を参照して、本発明にかかる半導体デバイスの製造方法の実施形態としては、実施形態1~実施形態3のIII族窒化物結晶基板を準備する工程と、結晶の主表面1s上に少なくとも1層の半導体層2を成長させることによりエピ層付III族窒化物結晶基板を形成する工程とを含む。かかる製造方法により、半導体層のピエゾ分極による量子閉じ込めシュタルク効果が抑制された特性の高い半導体デバイスが得られる。たとえば、上記半導体層2中に発光層210を含めることにより、発光層210のピエゾ分極による量子閉じ込めシュタルク効果が抑制されることにより発光のブルーシフトが抑制され、発光(たとえばピーク波長が430nm以上550nm以下の発光、特にピーク波長が500nm~550nmの緑色領域の発光)強度の積分強度が高い発光デバイスが得られる。
1.III族窒化物結晶体の製造
下地基板として直径50mmのGaAs結晶基板を用いて、HVPE法により、厚さ50mmのGaN結晶体(III族窒化物結晶体)を成長させた。すなわち、大気圧のHVPE反応炉内で、金属Gaを収容したボートを800℃に加熱し、このボートにHClガスとキャリアガス(H2ガス)との混合ガスを導入することにより、金属GaとHClガスとを反応させて、GaClガスを生成させた。これとともに、HVPE反応炉内にNH3ガスとキャリアガス(H2ガス)との混合ガスを導入することにより、GaClガスとNH3ガスとを反応させて、HVPE反応炉内に設置されたGaAs結晶基板(下地基板)上にGaN結晶体を成長させた。ここで、GaN結晶体の成長温度は1050℃、HVPE反応炉内のHClガス分圧は2kPa、NH3ガス分圧は30kPaとした。
上記で得られたGaN結晶体(III族窒化物結晶体)を、c軸を含む面に対して[0001]方向に-10°~10°の間の傾斜角αを有する面に平行な面でスライスすることにより、表1に示す主表面を有するGaN結晶基板(III族窒化物結晶基板)を製造した。ここで、傾斜角αは、符号が正の場合は主表面の面方位がc軸を含む面から[0001]方向に(すなわち(0001)面に向かって)傾斜していることを示し、符号が負の場合は主表面の面方位がc軸を含む面から[000-1]方向に(すなわち(000-1)面に向かって)傾斜していることを示す。
上記で得られたGaN結晶基板(III族窒化物結晶基板)主表面を、ラッピング(機械的研磨)した後、CMP(化学機械的研磨)することにより、半導体デバイス用GaN結晶基板を得た。ここで、ラッピングは、砥粒径が2μm、3μmおよび9μmの3種類のダイヤモンド砥粒を準備して、銅定盤または錫定盤を用いて、ダイヤモンド砥粒の粒径を段階的に小さくさせて行った。ラッピング圧力は100gf/cm2~500gf/cm2(9.8kPa~49.0kPa)、GaN結晶基板および定盤の回転数は30rpm(回転/min)~60rpmとした。また、CMPは、砥粒として1次粒子が化学的に結合して2次粒子となったコロイダルシリカ(1次粒子径が90nm、2次粒子径が210nm)を含み、pH調節剤として酒石酸、酸化剤としてトリクロロイソシアヌル酸を含み、pHおよび酸化還元電位(ORP)を表1に示す値に調製したスラリーを用いて、接触係数Cを表1に示す値になるように調整して行った。
図11を参照して、上記で得られた半導体デバイス用のGaN結晶基板(III族窒化物結晶基板1)の一方の主表面1s上に、MOCVD法により、少なくとも1層の半導体層2として、厚さ1000nmのn型GaN層202、厚さ1200nmのn型Inx1Aly1Ga1-x1-y1N(x1=0.03、y1=0.14)クラッド層204、厚さ200nmのn型GaNガイド層206、厚さ65nmのアンドープのInx2Ga1-x2N(x2=0.03)ガイド層208、厚さ15nmのGaN障壁層および厚さ3nmのInx3Ga1-x3N(x3=0.2~0.3)井戸層から構成される3周期のMQW(多重量子井戸)構造を有する発光層210、厚さ65nmのアンドープのInx4Ga1-x4N(x4=0.03)ガイド層222、厚さ20nmのp型Alx5Ga1-x5N(x5=0.11)ブロック層224、厚さ200nmのp型GaN層226、厚さ400nmのp型Inx6Aly6Ga1-x6-y6N(x6=0.03、y6=0.14)クラッド層228、および厚さ50nmのp型GaNコンタクト層230を順次成長させた。
CMPを、砥粒として1次粒子が化学的に結合して2次粒子となったコロイダルシリカ(1次粒子径が15nm、2次粒子径が40nm)を含み、pH調節剤としてリンゴ酸、酸化剤としてトリクロロイソシアヌル酸を含み、pHおよび酸化還元電位(ORP)を表2に示す値に調製したスラリーを用いて、接触係数Cを表2に示す値になるように調整して行ったこと以外は、実施例Iと同様にして、GaN結晶基板(III族窒化物結晶基板)および半導体デバイスを製造して、表面加工されたGaN結晶基板の表面層の均一歪み、不均一歪みおよび結晶格子面の面方位ずれを評価するとともに、半導体デバイスのLEDモード光の発光スペクトルの波長500nm~550nmの範囲における発光ピークの積分強度および半値幅を測定した。ここで、X線回折による評価を容易にする観点から、例II-1~II-8においては特定平行結晶格子面として(10-11)面を用いた。結果を表2にまとめた。
GaN結晶基板(III族窒化物結晶基板)の主表面の面方位をc軸を含む面の一つである(21-30)面からの傾斜角αを0.2とし、CMPを、砥粒として球状のコロイダルシリカ(表3に示す粒子径)を含み(ただし、例III-1には砥粒を含めなかった)、pH調節剤として酒石酸ナトリウムおよび炭酸ナトリウム、酸化剤としてジクロロイソシアヌル酸ナトリウムを含み、pHおよび酸化還元電位(ORP)を表3に示す値に調製したスラリーを用いて、接触係数Cを表3に示す値になるように調整して行ったこと以外は、実施例Iと同様にして、GaN結晶基板(III族窒化物結晶基板)および半導体デバイスを製造して、表面加工されたGaN結晶基板の表面層の均一歪み、不均一歪みおよび結晶格子面の面方位ずれを評価するとともに、半導体デバイスのLEDモード光の発光スペクトルの波長500nm~550nmの範囲における発光ピークの積分強度および半値幅を測定した。結果を表3にまとめた。
GaN結晶基板(III族窒化物結晶基板)の主表面の面方位を主表面の面方位をc軸を含む面の一つである(21-30)面からの傾斜角αを0.2とし、CMPを、砥粒として1次粒子が化学的に結合して2次粒子となったコロイダルシリカ(1次粒子径が35nm、2次粒子径が70nm)を含み、pH調節剤として硝酸、酸化剤として過酸化水素水およびトリクロロイソシアヌル酸を含み、pHおよび酸化還元電位(ORP)を表4に示す値に調製したスラリーを用いて、接触係数Cを表4に示す値になるように調整して行ったこと以外は、実施例Iと同様にして、GaN結晶基板(III族窒化物結晶基板)および半導体デバイスを製造して、表面加工されたGaN結晶基板の表面層の均一歪み、不均一歪みおよび結晶格子面の面方位ずれを評価するとともに、半導体デバイスのLEDモード光の発光スペクトルの波長500nm~550nmの範囲における発光ピークの積分強度および半値幅を測定した。ここで、X線回折による評価を容易にする観点から、例IV-1~IV-7において特定平行結晶格子面として(10-11)面を用いた。結果を表4にまとめた。
1.III族窒化物結晶体およびIII族窒化物結晶基板の製造
例V-1およびV-2については、下地基板として実施例Iの例I-4で製造した主表面の面方位が(10-10)のGaN結晶基板(III族窒化物結晶基板)を用いて、フラックス法によりGaN結晶体を成長させた。すなわち、GaN結晶基板(下地基板)と、Ga原料としての金属Gaと、フラックスとしての金属Naとを、モル比でGa:Naが1:1となるように坩堝に収容した。ついで、坩堝を加熱することにより、GaN結晶基板の(10-10)主表面に接触する800℃のGa-Na融液を得た。このGa-Na融液に、N原料として5MPaのN2ガスを溶解させて、GaN結晶基板の(10-10)主表面上に、厚さ2mmのGaN結晶を成長させた。結晶成長が進行するに従って、転位密度が減少した。GaN結晶からのGaN結晶基板の取り位置の違いにより、GaN結晶基板の主表面の転位密度を調整した(表5を参照)。
CMPを、砥粒として1次粒子が鎖状に化学結合して2次粒子となったヒュームドシリカ(1次粒子径が20nm、2次粒子径が150nm)を含み、pH調節剤としてクエン酸、酸化剤として過マンガン酸カリウムを含み、pHおよび酸化還元電位(ORP)を表に示す値に調製したスラリーを用いて、接触係数Cを表2に示す値になるように調整して行ったこと以外は、実施例Iと同様にして、GaN結晶基板(III族窒化物結晶基板)を表面加工して、半導体デバイス用GaN結晶基板を得た。こうして得られた半導体デバイス用GaN結晶基板(表面加工されたGaN結晶基板)の表面層の均一歪み、不均一歪みおよび結晶格子面の面方位ずれを、実施例Iと同様にして、評価した。
上記で得られた半導体デバイス用のGaN結晶基板を用いて、実施例Iと同様にして半導体デバイスを製造して、半導体デバイスのLEDモード光の発光スペクトルの波長500nm~550nmの範囲における発光ピークの積分強度および半値幅を測定した。結果を表5にまとめた。
CMPを、砥粒として球状のコロイダルシリカ(粒子径が30nm)を含み、pH調節剤として塩酸、酸化剤として過酸化水素水および次亜塩素酸を含み、pH、酸化還元電位(ORP)および粘度を表6に示す値に調製したスラリーを用いて、CMP周速度、CMP圧力および接触係数Cを表6に示す値になるように調整して行ったこと以外は、実施例Iと同様にして、GaN結晶基板(III族窒化物結晶基板)を表面加工した。こうして表面加工されたGaN結晶基板の表面層の均一歪み、不均一歪みおよび結晶格子面の面方位ずれを、実施例Iと同様にして、評価した。ここで、X線回折による評価を容易にする観点から、例VI-10~VI-12においては特定平行結晶格子面として(10-11)面を用いた。結果を表6にまとめた。
-50X+1400≦Y≦-50X+1700
の関係を有するスラリーを用いて、接触係数Cが1.2×10-6m以上1.8×10-6m以下となるようにCMPを行うことにより、主表面の面方位が主表面の面方位がc軸を含む面から[0001]方向に-10°以上10°以下の傾斜角を有するIII族窒化物結晶基板においても、その表面層の均一歪みを1.7×10-3以下、その表面層の不均一歪みを110arcsec以下、および/またはその表面層の特定平行結晶格子面((11-22)面または(10-11)面)の面方位ずれを300arcsec以下とすることができた。
例III-4で作製した主表面の面方位が(21-30)面から[0001]方向に0.2°の傾斜角を有するGaN結晶基板(III族窒化物結晶基板)を切断し、5mm×20mm~5mm×45mmのサイズの複数の小片基板を得た。かかる複数の小片基板を、それらの主面(かかる主面は、いずれも、面方位が(21-30)面から[0001]方向に0.2°の傾斜角を有する。)が互いに平行になるように、かつ、それらの側面が互いに隣接するように並べて所望のサイズの下地基板とし、それらの小片基板の主面のそれぞれにHVPE法でGaN結晶(III族窒化物結晶)を成長させて、それらのIII族窒化物結晶を互いに接合し、外周部を加工することにより、所望のサイズのGaN結晶(III族窒化物結晶)を得た。得られたGaN結晶を下地基板の主面に平行に切り出し、例III-4と同様にして、18mm×18mm、30mm×50mm、直径40mm、直径100mm、直径150mmのGaN結晶基板および半導体デバイスを製造した。かかるGaN結晶基板および半導体デバイスは、いずれも例III-4の場合と同等の基板特性およびデバイス特性が得られた。さらに、これらのGaN結晶基板(III族窒化物結晶基板)を下地基板とし、HVPE法により繰り返し結晶成長して、それぞれ18mm×18mm、30mm×50mm、直径40mm、直径100mm、直径150mmのGaN結晶(III族窒化物結晶)を得た。かかるGaN結晶を上記と同様に加工することにより、例III-4と同等の特性を有するGaN結晶基板および半導体デバイスが得られた。
Claims (16)
- III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折条件を満たしながら前記結晶基板の主表面(1s)からのX線侵入深さを変化させるX線回折測定から得られる前記特定平行結晶格子面(1d)の面間隔において、0.3μmの前記X線侵入深さにおける前記面間隔をd1と表わし5μmの前記X線侵入深さにおける前記面間隔をd2と表したときに|d1-d2|/d2の値で表される前記結晶基板の表面層(1p)の均一歪みが1.7×10-3以下であり、
前記主表面(1s)の面方位が、前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有するIII族窒化物結晶基板。 - III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折条件を満たしながら前記結晶基板の主表面(1s)からのX線侵入深さを変化させるX線回折測定から得られる前記特定平行結晶格子面(1d)の回折強度プロファイルにおいて、0.3μmの前記X線侵入深さにおける回折強度ピークの半値幅v1と5μmの前記X線侵入深さにおける回折強度ピークの半値幅v2とから得られる|v1-v2|の値で表される前記結晶基板の表面層(1p)の不均一歪みが110arcsec以下であり、
前記主表面(1s)の面方位が、前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有するIII族窒化物結晶基板。 - III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折に関して前記結晶基板の主表面(1s)からのX線侵入深さを変化させて測定されたロッキングカーブにおいて、0.3μmの前記X線侵入深さにおける回折強度ピークの半値幅w1と5μmの前記X線侵入深さにおける回折強度ピークの半値幅w2とから得られる|w1-w2|の値で表される前記結晶基板の表面層(1p)の前記特定平行結晶格子面(1d)の面方位ずれが300arcsec以下であり、
前記主表面(1s)の面方位が、前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有するIII族窒化物結晶基板。 - 前記主表面(1s)は5nm以下の表面粗さRaを有する請求の範囲第1項に記載のIII族窒化物結晶基板。
- 前記主表面(1s)の面方位は、前記結晶基板の{10-10}面、{11-20}面および{21-30}面のいずれかの面に対して傾斜角が0°以上0.1°未満と実質的に平行である請求の範囲第1項に記載のIII族窒化物結晶基板。
- 前記主表面(1s)の面方位は、前記結晶基板の{10-10}面、{11-20}面および{21-30}面のいずれかの面からの傾斜角が0.1°以上10°以下である請求の範囲第1項に記載のIII族窒化物結晶基板。
- 前記主表面(1s)に存在する酸素の濃度が2原子%以上16原子%以下である請求の範囲第1項に記載のIII族窒化物結晶基板。
- 前記主表面(1s)における転位密度が1×107cm-2以下である請求の範囲第1項に記載のIII族窒化物結晶基板。
- 直径が40mm以上150mm以下である請求の範囲第1項に記載のIII族窒化物結晶基板。
- 請求の範囲第1項に記載のIII族窒化物結晶基板(1)の前記主表面(1s)上にエピタキシャル成長により形成されている少なくとも1層の半導体層(2)を含むエピ層付III族窒化物結晶基板。
- 請求の範囲第10項に記載のエピ層付III族窒化物結晶基板(3)を含む半導体デバイス。
- 前記エピ層付III族窒化物結晶基板(3)に含まれる前記半導体層(2)は、ピーク波長が430nm以上550nm以下の光を発する発光層(210)を含む請求の範囲第11項に記載の半導体デバイス。
- III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折条件を満たしながら前記結晶基板の主表面(1s)からのX線侵入深さを変化させるX線回折測定から得られる前記特定平行結晶格子面(1d)の面間隔において、0.3μmの前記X線侵入深さにおける前記面間隔をd1と表わし5μmの前記X線侵入深さにおける前記面間隔をd2と表したときに|d1-d2|/d2の値で表される前記結晶基板の表面層(1p)の均一歪みが1.7×10-3以下であり、前記主表面(1s)の面方位が前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有する前記結晶基板を準備する工程と、
前記結晶基板の主表面(1s)上に少なくとも1層の半導体層(2)をエピタキシャル成長させることによりエピ層付III族窒化物結晶基板(3)を形成する工程と、を含む半導体デバイスの製造方法。 - III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折条件を満たしながら前記結晶基板の主表面(1s)からのX線侵入深さを変化させるX線回折測定から得られる前記特定平行結晶格子面(1d)の回折強度プロファイルにおいて、0.3μmの前記X線侵入深さにおける回折強度ピークの半値幅v1と5μmの前記X線侵入深さにおける回折強度ピークの半値幅v2とから得られる|v1-v2|の値で表される前記結晶基板の表面層(1p)の不均一歪みが110arcsec以下であり、前記主表面(1s)の面方位が前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有する前記結晶基板を準備する工程と、
前記結晶基板の主表面(1s)上に少なくとも1層の半導体層(2)をエピタキシャル成長させることによりエピ層付III族窒化物結晶基板(3)を形成する工程と、を含む半導体デバイスの製造方法。 - III族窒化物結晶基板(1)の任意の特定平行結晶格子面(1d)のX線回折に関して前記結晶基板の主表面(1s)からのX線侵入深さを変化させて測定されたロッキングカーブにおいて、0.3μmの前記X線侵入深さにおける回折強度ピークの半値幅w1と5μmの前記X線侵入深さにおける回折強度ピークの半値幅w2とから得られる|w1-w2|の値で表される前記結晶基板の表面層(1p)の前記特定平行結晶格子面(1d)の面方位ずれが300arcsec以下であり、前記主表面(1s)の面方位が前記結晶基板のc軸(1c)を含む面(1v)から[0001]方向に-10°以上10°以下の傾斜角を有する前記結晶基板を準備する工程と、
前記結晶基板の主表面(1s)上に少なくとも1層の半導体層(2)をエピタキシャル成長させることによりエピ層付III族窒化物結晶基板(3)を形成する工程と、を含む半導体デバイスの製造方法。 - 前記エピ層付III族窒化物結晶基板(3)を形成する工程において、前記半導体層(2)は、発光層(210)を含み、前記発光層(210)がピーク波長430nm以上550nm以下の光を発するように形成される、請求の範囲第13項に記載の半導体デバイスの製造方法。
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JP2011129752A (ja) | 2011-06-30 |
CN102666945A (zh) | 2012-09-12 |
EP2514858A1 (en) | 2012-10-24 |
EP2514858A4 (en) | 2013-11-13 |
KR20120106803A (ko) | 2012-09-26 |
TWI499082B (zh) | 2015-09-01 |
JP4835749B2 (ja) | 2011-12-14 |
TW201125163A (en) | 2011-07-16 |
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