WO2011074038A1 - 電子放出素子およびこれを備えた撮像装置 - Google Patents
電子放出素子およびこれを備えた撮像装置 Download PDFInfo
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- WO2011074038A1 WO2011074038A1 PCT/JP2009/006958 JP2009006958W WO2011074038A1 WO 2011074038 A1 WO2011074038 A1 WO 2011074038A1 JP 2009006958 W JP2009006958 W JP 2009006958W WO 2011074038 A1 WO2011074038 A1 WO 2011074038A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
- H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
- H01J29/04—Cathodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
- H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
- H01J29/467—Control electrodes for flat display tubes, e.g. of the type covered by group H01J31/123
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
- H01J29/46—Arrangements of electrodes and associated parts for generating or controlling the ray or beam, e.g. electron-optical arrangement
- H01J29/48—Electron guns
- H01J29/481—Electron guns using field-emission, photo-emission, or secondary-emission electron source
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J31/00—Cathode ray tubes; Electron beam tubes
- H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
- H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
- H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
- H01J31/123—Flat display tubes
- H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
- H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2329/00—Electron emission display panels, e.g. field emission display panels
- H01J2329/46—Arrangements of electrodes and associated parts for generating or controlling the electron beams
- H01J2329/4604—Control electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2329/00—Electron emission display panels, e.g. field emission display panels
- H01J2329/46—Arrangements of electrodes and associated parts for generating or controlling the electron beams
- H01J2329/4669—Insulation layers
Definitions
- the present invention relates to an electron-emitting device having a focusing electrode that focuses electrons emitted from a surface emitting portion, and an imaging apparatus including the electron-emitting device.
- the electron-emitting device when being incorporated into an imaging device at the time of mounting, the electron-emitting device is disposed facing the substrate having the anode electrode and the photoelectric conversion layer through a vacuum space, and the emitted electrons are emitted from the holes of the photoelectric conversion layer.
- the combined current is detected as a video signal.
- a focusing electrode layer that focuses the electric field by applying a voltage having a potential different from that of the gate electrode layer. It is conceivable to provide it.
- the gate electrode layer and the focusing electrode layer are electrically connected by the carbon layer formed on the inner peripheral surface of the emission recess at the end of the manufacturing process. As a result, the gate electrode layer and the focusing electrode layer are at the same potential, so that a sufficient potential difference cannot be generated between them, and there is a problem that electrons cannot be focused.
- the present invention provides a surface emission type electron-emitting device in which a gate electrode layer and a focusing electrode layer are not conducted by a carbon layer even when a focusing electrode layer is provided, and an imaging apparatus including the same The task is to do.
- the electron-emitting device of the present invention includes an electron-emitting layer that emits electrons from a surface emitting portion, a focusing electrode layer that is formed on the surface of the electron-emitting layer via a first insulator layer, and focuses the emitted electrons.
- Another electron-emitting device of the present invention includes an electron-emitting layer that emits electrons from a surface-emitting portion, a gate electrode layer formed on the surface of the electron-emitting layer via a first insulator layer, and a second insulator A focusing electrode layer for focusing the emitted electrons formed on the surface of the gate electrode layer through the layer; a third insulator layer formed on the surface of the focusing electrode layer; a third insulator layer; A discharge recess that penetrates through the electrode layer, the second insulator layer, the gate electrode layer, and the first insulator layer and opens in a concave shape on the surface of the surface discharge portion, and an inner periphery of the discharge recess from the surface of the third insulator layer A carbon layer formed over the surface, and a partial insulating portion that insulates the focusing electrode layer and the carbon layer are provided.
- the focusing electrode layer and the gate electrode layer are not electrically connected through the carbon layer by the partial insulating portion that insulates the focusing electrode layer and the carbon layer.
- a voltage having a potential different from that of the layer can be applied, and electrons (electron beams) emitted from the surface emitting portion can be focused efficiently.
- the gate electrode layer and the focusing electrode layer are preferably made of tungsten (W), and other metals such as Si, Al, Ti, TiN, Cu, Ag, Cr, Au, Pt, and C are also used. It may consist of.
- the partial insulating portion includes a sidewall interposed between the carbon layer and the gate electrode layer, a sidewall interposed between the carbon layer and the second insulator layer, and the carbon layer and the focusing electrode layer.
- the sidewalls interposed between the carbon layer and the first insulator layer at least the sidewalls interposed between the carbon layer and the focusing electrode layer. It is preferable.
- the partial insulating portion includes a sidewall interposed between the carbon layer and the third insulator layer, a sidewall interposed between the carbon layer and the focusing electrode layer, the carbon layer and the second insulator layer. At least the carbon layer of the sidewall interposed between the carbon layer and the gate electrode layer, and the sidewall interposed between the carbon layer and the first insulator layer. And a side wall interposed between the focusing electrode layer and the focusing electrode layer.
- the location of the sidewall can be selected according to the shape of the discharge recess and the film formation / etching process.
- the sidewall is formed not only between the carbon layer and the focusing electrode layer but also between the carbon layer and other layers, a complicated film formation / etching process is not required, and the carbon layer and the focusing electrode are not required.
- a partial insulating portion that insulates the layer can be easily formed.
- the thickness (film width) of the sidewall is formed so as to be substantially the same as the insulating performance of the second insulator layer.
- the focusing electrode layer can obtain sufficient insulation from the carbon layer as well as from the gate electrode layer. It can be avoided that the significance of the sidewall is lost due to leakage current (leakage). Thereby, the focusing electrode layer and the gate electrode layer can be appropriately insulated.
- the sidewall and the second insulator layer are made of the same insulating material, it is preferable that the thickness of the sidewall (film width) and the thickness of the second insulator layer are the same. .
- the electron emission layer is preferably made of amorphous silicon, and the partial insulating part is preferably made of oxide or nitride.
- the partial insulation part can promote the oxidation of an electron emission layer, and can improve the electron emission performance of a surface emission part.
- silicon oxide (SiO X ) is particularly effective as the oxide constituting the partial insulating portion.
- WO X , AlO X , TiO X , CuO X , AgO X , CrO X , MgO X, etc. metal oxides may be MgAl2O 4, metal composite oxides such as BaTiO 3.
- the focusing electrode layer can function at a voltage lower than that of the gate electrode layer, an electron-emitting device that emits electrons at a low voltage as a whole can be realized.
- the potential of the focusing electrode layer may be a negative potential.
- the potential difference between the gate electrode layer and the focusing electrode layer can be made large, the focusing effect by the focusing electrode can be sufficiently enhanced even when the applied voltage is low as a whole.
- the emission recess is formed to expand in the electron emission direction.
- each electrode layer and each insulator layer located above the emission recess does not block the trajectory of the emitted electrons (attenuation of the electron beam), and efficiently emits electrons. can do.
- An imaging device of the present invention includes an electron emission substrate portion having the electron emission element and the cathode electrode, a light receiving substrate portion facing the electron emission substrate portion with a vacuum space, and having a photoelectric conversion layer and an anode electrode, , Provided.
- the emitted electrons can be efficiently focused on the surface of the photoelectric conversion layer, and a high-detection power-saving imaging device can be provided.
- FIG. 1 is a schematic cross-sectional view illustrating a configuration of an imaging apparatus according to a first embodiment. It is an expanded sectional view around the emission recess of the electron-emitting device according to the second embodiment. It is the expanded sectional view which showed the 1st modification of the discharge
- This electron-emitting device is a so-called surface-emitting type electron-emitting device having a cold-cathode type electron source, and the imaging device has a vacuum space in an electron-emitting device array in which a plurality of electron-emitting devices are arranged in a matrix.
- the photoelectric conversion film is opposed to each other.
- an electron-emitting device 1 includes a cathode electrode layer 2, an electron-emitting layer 3 stacked on the cathode electrode layer 2 and made of amorphous silicon (a-Si), and an electron-emitting layer 3 And an electrode layer portion 4 composed of a plurality of electrode layers and a plurality of insulator layers.
- the electrode layer portion 4 is formed on the first insulator layer 5 formed on the electron emission layer 3, the focusing electrode layer 6 formed on the first insulator layer 5, and the focusing electrode layer 6.
- the gate electrode layer 8 formed on the second insulator layer 7.
- the electrode layer portion 4 is formed with a concave electron emission recess 10 that penetrates each layer and exposes the electron emission layer 3 at the bottom, and the surface emission portion 9, that is, an exposed portion of the electron emission layer 3, that is, An emission site is configured.
- a carbon layer 11 is formed on the surface of the gate electrode layer 8 and the inner peripheral surface of the electron emission recess 10, and between the carbon layer 11 and the inner peripheral surface of the electron emission recess 10, silicon oxide is formed.
- An insulating side wall 12 made of (SiO x ) is formed.
- an imaging element (pixel) 113 is configured by an array of electron-emitting devices 1 (electron-emitting recesses 10) (see FIG. 7).
- the carbon layer 11 enhances the electron emission performance of the surface emission part 9 in cooperation with the electron emission layer 3 made of amorphous silicon.
- the side wall 12 insulates the focusing electrode layer 6 and the carbon layer 11 and prevents the gate electrode layer 8 and the focusing electrode layer 6 from conducting through the carbon layer 11 (details will be described later).
- the electron emission concave portion 10 includes an upper emission concave portion 10a surrounded by a layer end of the gate electrode layer 8 formed on the uppermost portion, a layer of the first insulator layer 5, the focusing electrode layer 6, and the second insulator layer 7. It has a lower discharge recess 10b surrounded by an end and is formed by two etchings as will be described in detail later.
- the upper emission recess 10a is formed such that the end of the gate electrode layer 8 is set back with respect to the end of the first insulator layer 5, the focusing electrode layer 6 and the second insulator layer 7, and the electron emission recess 10a. 10, the upper part is formed so as to expand with respect to the lower part as a whole. As a result, the layer end of the gate electrode layer 8 is prevented from protruding (obstructing) on the orbit of the electrons emitted from the surface emitting portion 9.
- the sidewalls 12 include an upper sidewall 12a formed on the inner peripheral surface of the upper emission recess 10a (the layer end of the receded gate electrode layer 8), and an inner peripheral surface of the lower emission recess 10b (the first insulator layer 5, A lower side wall 12b formed on the focusing electrode layer 6 and the second insulator layer 7).
- the side wall 12 is thus divided into two because the insulating material (SiO x ) formed on the inner peripheral surface of the electron emission recess 10 is etched back.
- the carbon layer 11 is uniformly formed so as to cover the surface of the gate electrode layer 8 and the upper and lower sidewalls 12a and 12b. In the present embodiment, in order to suppress unwanted leakage current (leakage) and heat generation by the carbon layer 11, the carbon layer 11 is not formed on the surface emission portion 9 which is the bottom of the electron emission recess 10. Yes.
- the gate electrode layer 8 is made of tungsten (W) and has a thickness of 60 nm (600 mm). Similar to the gate electrode layer 8, the focusing electrode layer 6 is made of tungsten, is thinner than the gate electrode layer 8, and is formed to a film thickness of 50 nm (500 mm). The film thicknesses of both the gate electrode layer 8 and the focusing electrode layer 6 are preferably formed within a range of 10 to 200 nm (100 to 2000 mm). In addition to tungsten, the gate electrode layer 8 and the focusing electrode layer 6 may use metals such as Si, Al, Ti, TiN, Cu, Ag, Cr, Au, Pt, and C.
- the first insulator layer 5 and the second insulator layer 7 are preferably made of the same material (SiO X or the like) as that of the sidewalls 12 and are each formed to a thickness of 150 nm (1500 mm). That is, the film thickness that insulates between the gate electrode layer 8 and the focusing electrode layer 6 (the film thickness of the second insulator layer 7) is 150 nm (1500 mm), and the gate electrode layer 8 and the electron emission layer 3 The film thickness that insulates between them (the total film thickness of the first insulator layer 5, the focusing electrode layer 6, and the second insulator layer 7) is 350 nm (3500 mm). It should be noted that the film thicknesses of both the first insulator layer 5 and the second insulator layer 7 are preferably in the range of 50 to 1000 nm (500 to 10000 mm).
- the sidewall 12 is made of silicon oxide (SiO x ) as described above, and is formed to a film thickness (film width) of 150 nm (1500 mm). That is, the sidewall 12 (particularly, the upper sidewall 12a) has the same film thickness as the second insulator layer 7 that insulates between the gate electrode layer 8 and the focusing electrode layer 6. Thereby, the focusing electrode layer 6 is insulated from the carbon layer 11 with the same insulation performance as that insulated from the gate electrode layer 8, and the insulation performance is improved by leakage from the sidewall 12. Prevents the decline.
- SiO x silicon oxide
- the surface emitting portion 9 is heated and oxidized by the generated strong electric field, but the side wall 12 made of oxide SiO X is a surface made of amorphous silicon.
- the oxidation of the emission part 9 is promoted, and the electron emission performance of the surface emission part 9 is improved.
- the sidewall 12 is made of metal oxide such as WO X , AlO X , TiO X , CuO X , AgO X , CrO X , MgO X , metal composite oxide such as MgAl 2 O 4 , BaTiO 3 or the like in addition to silicon oxide.
- Nitride may be used.
- the voltage applied to the focusing electrode layer 6 is set lower than the voltage applied to the gate electrode layer 8 (carbon layer 11), and the potential of the gate electrode layer 8 is set to 20V, It is preferable that the concave space potential difference between them is 0 to 13V. In this way, the voltage is applied so that the focusing electrode layer 6 has a sufficiently lower potential than the gate electrode layer 8, and the applied voltage to the electron-emitting device 1 as a whole can be kept low. In order to enhance the focusing effect, the voltage applied to the focusing electrode layer 6 may be a negative potential.
- FIG. 2 shows a manufacturing process of the upper discharge recess 10a.
- amorphous silicon that becomes an electron emission layer 3 silicon oxide that becomes a first insulator layer 5, tungsten that becomes a focusing electrode layer 6, a second insulator Silicon oxide to be the layer 7 and tungsten to be the gate electrode layer 8 are sequentially formed by a sputtering method and a CVD method (see FIG. 5A).
- Each layer is formed so that it becomes.
- a photoresist layer 20 is applied on the gate electrode layer 8 formed on the uppermost portion by a spin coating method or the like, and after an exposure / development process, the upper emission recess 10a is formed at the position where the electron emission recess 10 is formed.
- a resist pattern 21 having a resist removal portion having the same dimension as the opening dimension is formed (see FIG. 5B). In the actual process, a plurality of resist removal portions are formed in a matrix to form an array of electron-emitting devices 1.
- RIE Reactive Ion Etching
- FIG. 3 shows a manufacturing process of the lower discharge recess 10b.
- FIG. 2A shows a state in which the photoresist layer 20 is removed and an opening 22 is formed in the gate electrode layer 8.
- a photoresist layer 30 is applied on the surface of the gate electrode layer 8 and the exposed second insulator layer 7 by a spin coat method or the like, and after exposure / development steps, the same dimension as the opening dimension of the lower emission recess 10b.
- a resist pattern 31 having a resist removal portion is formed. At this time, the resist pattern 31 is formed so as to be coaxial (concentric) with the upper discharge recess 10a and to have a smaller diameter (see FIG. 5B).
- the first insulator layer 5, the focusing electrode layer 6 and the second insulator layer 7 are etched by the RIE method through the formed resist pattern 31 (anisotropic etching). Thereby, a circular opening 32 from which the first insulator layer 5, the focusing electrode layer 6 and the second insulator layer 7 are removed is formed on the electron emission layer 3. That is, the lower emission concave portion 10b is formed, and the electron emission layer 3 (surface emission portion 9) is exposed at the bottom thereof (see FIG. 10C). Thereafter, only the photoresist layer 30 is removed.
- FIG. 4 shows a manufacturing process of the sidewall 12.
- FIG. 2A shows a state where the photoresist layer 30 is removed and the electron emission recess 10 is formed on the electron emission layer 3.
- silicon oxide serving as the sidewalls 12 is formed on the surface of the gate electrode layer 8, the inner peripheral surface of the electron emission recess 10 and the exposed electron emission layer 3 (surface emission part 9) by a CVD method or the like.
- the silicon oxide is formed to have a film thickness (film width) (150 nm) of the sidewall 12 described above (see FIG. 5B).
- the formed silicon oxide is etched back by RIE until the surface of the gate electrode layer 8 is exposed.
- the silicon oxide is etched with the same thickness in the direction perpendicular to the layer surface, and the surface of the gate electrode layer 8 and the surface emission portion 9 of the electron emission layer 3 are exposed, and the upper emission recess 10a and the lower emission recess 10b
- the upper side wall 12a and the lower side wall 12b having a film thickness (film width) of 150 nm are formed on the inner peripheral surface (see FIG. 4C).
- the carbon layer 11 is formed by sputtering or the like over the surface of the gate electrode layer 8 and the inner peripheral surface of the electron emission recess 10 (see FIG. 1).
- FIG. 5 shows an electron-emitting device 1 according to a first modification of the first embodiment.
- the sidewall 12 according to this modification includes an upper sidewall 12a formed between the carbon layer 11 and the upper emission recess 10a (layer end of the gate electrode layer 8), and the carbon layer 11.
- a lower sidewall 12b formed only between the focusing electrode layer 6 facing only the lower discharge recess 10b.
- the lower sidewall 12b has the same film thickness (film width) as that of the second insulator layer 7, and the first insulator layer 5 and the second insulator layer sandwich the focusing electrode layer 6 from above and below.
- the focusing electrode layer 6 is sufficiently insulated from the carbon layer 11 similarly to the gate electrode layer 8, and the sidewall 12 allows the focusing electrode layer 6 to conduct the gate electrode layer 8 through the carbon layer 11. It is the structure which can fully prevent.
- FIG. 6 shows an electron-emitting device 1 according to a second modification of the first embodiment.
- the sidewall 12 according to the second modification is formed only between the carbon layer 11 and the layer end of the focusing electrode layer 6 facing the lower emission recess 10b.
- This sidewall 12 has the same film thickness (film width) as that of the second insulator layer 7 like the lower sidewall 12b of the first modification, and sandwiches the focusing electrode layer 6 from above and below.
- the first insulator layer 5 and the second insulator layer 7 are formed so as to be aligned with the layer ends and embedded in the inner peripheral surface of the lower discharge recess 10b.
- the side wall 12 is intended to insulate between the focusing electrode layer 6 and the carbon layer 11, this modification forms the side wall 12 only between the focusing electrode layer 6 and the carbon layer 11, and the gate.
- the layer end of the electrode layer 8 and the carbon layer 11 are in a conductive state.
- FIG. 7 is a cross-sectional view schematically showing the imaging device 100.
- the imaging device 100 includes an electron emission substrate 110 in which a plurality of electron emission elements 1 are formed, and an electron emission substrate.
- the light receiving substrate part 120 which is disposed opposite to the part 110 in a vacuum space and serves as a target for the emitted electrons, and is spaced between the electron emitting substrate part 110 and the light receiving substrate part 120, And a mesh electrode 130 for controlling the trajectory.
- the electron emission substrate unit 110 includes a silicon substrate 111, a drive circuit layer 112 formed on the silicon substrate 111, and a plurality of imaging elements 113 formed in a matrix on the drive circuit layer 112.
- Each image sensor 113 functions as one pixel, and is configured by an electron emitter array 114 in which a plurality of electron emitters 1 are arranged in a matrix. That is, the electron-emitting device array 114 constituting one imaging device 113 is driven as a unit.
- the drive circuit layer 112 is formed of a MOS transistor array (switch) for driving the electron-emitting device array 114 (electron-emitting device 1) and a horizontal / vertical scanning circuit for controlling the MOS transistor array on a silicon substrate.
- a circuit (not shown) is built in and configured.
- the plurality of electron-emitting device arrays 114 (imaging devices 113) are dot-sequentially driven (scanned) by a driving circuit.
- the light receiving substrate portion 120 includes a transparent glass substrate 121, an anode electrode layer 122 (transparent electrode) laminated on the back surface of the glass substrate 121, and a photoelectric conversion layer 123 laminated on the back surface of the anode electrode layer 122. is doing.
- a voltage is applied to the anode electrode layer 122, holes generated in the photoelectric conversion layer 123 are accelerated by incident light from the glass substrate 121 side, and a positive light corresponding to an incident light image near the back surface of the photoelectric conversion layer 123 is accelerated.
- a hole pattern (not shown) is formed.
- the mesh electrode 130 is disposed between the electron emission substrate unit 110 and the light receiving substrate unit 120 in order to control the trajectory of the emitted electrons and absorb surplus electrons.
- the light receiving substrate unit 120 includes a circuit for supplying signals and voltages necessary for driving the light receiving substrate unit 120, a circuit for outputting a detected video signal, and the like.
- this imaging device 100 electrons emitted from the electron emission recess 10 of the electron emission substrate portion 110 pass through the holes 131 of the mesh electrode 130 and grow near the surface of the photoelectric conversion layer 123 of the light receiving substrate portion 120.
- the image is picked up by combining with the pattern and detecting the current at the time of combining as a video signal. That is, in the photoelectric conversion layer 123, a different video signal is detected from the difference in the accumulated amount of holes for each image sensor 113 by the hole pattern reflecting the incident light image, and the strength of this video signal is detected as light and dark.
- the focusing electrode layer 6 is formed below the gate electrode layer 8 in the electrode layer portion 4.
- the gate electrode layer 8 is not formed in the electrode layer portion 4.
- a focusing electrode layer 6 is formed above.
- the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
- the electron-emitting device 1 includes a cathode electrode layer 2, an electron-emitting layer 3 stacked on the cathode electrode layer 2, and an electrode formed on the electron-emitting layer 3. And a layer portion 4.
- the electrode layer portion 4 is formed on the first insulator layer 5 formed on the electron emission layer 3, the gate electrode layer 8 formed on the first insulator layer 5, and the gate electrode layer 8.
- a second insulator layer 7 formed, a focusing electrode layer 6 formed on the second insulator layer 7, and a third insulator layer 50 formed on the focusing electrode layer 6. Yes.
- the electrode layer portion 4 is formed with an electron emission recess 10 that penetrates each layer and exposes the surface emission portion 9 at the bottom.
- the carbon layer 11 is formed on the surface of the third insulator layer 50 and the inner peripheral surface of the electron emission recess 10.
- a sidewall 12 is formed between the carbon layer 11 and the inner peripheral surface of the electron emission recess 10.
- the electron emission recess 10 includes the upper emission recess 10a surrounded by the layer edges of the third insulator layer 50, the focusing electrode layer 6 and the second insulator layer 7 formed thereon, the gate electrode layer 8 and the first electrode layer. And a lower discharge recess 10 b surrounded by the layer end of the insulator layer 5.
- the upper emission recess 10 a is formed by retreating the layer ends of the third insulator layer 50, the focusing electrode layer 6 and the second insulator layer 7 with respect to the layer ends of the gate electrode layer 8 and the first insulator layer 5.
- the upper part of the electron emission recess 10 is expanded with respect to the lower part as a whole.
- the layer end of the gate electrode layer 8 is prevented from protruding on the trajectory of electrons emitted from the surface emitting portion 9.
- the upper discharge recess 10a is set back sufficiently larger than the film thickness (film width) of the sidewall 12 with respect to the lower discharge recess 10b, and the carbon layer 11 and the gate electrode layer 8 are in contact with each other ( Conduction part 51). This is to prevent the gate electrode layer 8 from being surrounded by the insulating layer and insulated from the carbon layer 11 by the sidewall 12.
- the sidewall 12 includes an upper sidewall 12a formed on an inner peripheral surface of the upper emission recess 10a (layer ends of the retracted third insulator layer 50, the focusing electrode layer 6 and the second insulator layer 7), and a lower emission. And a lower sidewall 12b formed on the inner peripheral surface of the recess 10b (layer ends of the gate electrode layer 8 and the first insulator layer 5). Further, the carbon layer 11 is uniformly formed so as to cover the surface of the gate electrode layer 8 and the upper and lower sidewalls 12a and 12b. As in the first embodiment, the carbon layer 11 is not formed on the surface emitting portion 9.
- each layer deposited on the electrode layer portion 4 is the same as in the first embodiment, and the third insulator layer 50 included only in the electrode layer portion 4 according to the present embodiment is the first
- the insulating layer 5 and the second insulating layer 7 are made of the same material.
- the thickness of each layer is the same as in the first embodiment, but only the first insulator layer 5 that insulates the electron emission layer 3 and the gate electrode layer 8 is sufficiently insulated from each other.
- the film is formed with a thickness of 350 nm (3500 mm).
- FIG. 9 shows an electron-emitting device 1 according to a first modification of the second embodiment.
- the sidewall 12 according to this modification includes an upper sidewall 12a formed between the carbon layer 11 and only the layer end of the focusing electrode layer 6 facing the upper emission recess 10a, A lower sidewall 12b formed only between the gate electrode layer 8 facing only the lower emission recess 10b.
- the upper sidewall 12a has the same film thickness (film width) as the second insulator layer 7, and the second and third insulator layers 7 and 3 sandwich the focusing electrode layer 6 from above and below. It is embedded in the inner peripheral surface of the upper discharge recess 10a so as to align with the 50 layer ends.
- the focusing electrode layer 6 is sufficiently insulated from the carbon layer 11 similarly to the gate electrode layer 8, and the sidewall 12 allows the focusing electrode layer 6 to conduct the gate electrode layer 8 through the carbon layer 11. It is the structure which can fully prevent.
- FIG. 10 shows an electron-emitting device 1 according to a second modification of the present embodiment.
- the sidewall 12 according to this modification is formed only between the carbon layer 11 and the layer end of the focusing electrode layer 6 facing the upper emission recess 10a.
- This sidewall 12 has the same film thickness (film width) as that of the second insulator layer 7 in the same manner as the upper sidewall 12a of the first modification, and sandwiches the focusing electrode layer 6 from above and below. It is embedded in the inner peripheral surface of the upper discharge recess 10a so as to be aligned with the layer edges of the second insulator layer 7 and the third insulator layer 50. Since the sidewall 12 is intended to insulate between the focusing electrode layer 6 and the carbon layer 11, in this modification, the sidewall 12 is formed only between the focusing electrode layer 6 and the carbon layer 11. .
- the focusing electrode layer 6 and the gate electrode layer 8 are electrically connected via the carbon layer 11 by the sidewall 12 that insulates the focusing electrode layer 6 and the carbon layer 11. Therefore, a voltage having a different potential from that of the gate electrode layer 8 can be applied to the focusing electrode layer 6, and the electron trajectory can be efficiently focused.
- the side wall 12 that insulates the carbon layer 11 and the focusing electrode layer 6 from each other can be easily formed without requiring a complicated film formation / etching process.
- the focusing electrode layer 6 functions at a voltage lower than that of the gate electrode layer 8, electrons can be emitted at a low voltage as a whole.
- the imaging device 100 provided with the electron-emitting device 1 can efficiently focus the emitted electrons on the surface of the photoelectric conversion layer 123, which is a power-saving type and has high detection accuracy.
- Electron emission element 2 Cathode electrode layer 3
- Electron emission layer 5 1st insulator layer 6
- Focusing electrode layer 7 2nd insulator layer 8
- Surface emission part 10 Electron emission recessed part 11 Carbon layer 12
- Side wall 12a Upper side wall 12b
- Lower side wall 50 Third insulator layer 100
- Imaging device 110 Electron emission substrate part 111 Silicon substrate 120 Light receiving substrate part 121 Glass substrate 122 Anode electrode layer 123 Photoelectric conversion layer 130 Mesh electrode
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Abstract
Description
そこで、上記の面放出型電子放出素子において、放出された電子の軌道(電子ビーム)の広がりを抑えるべく、ゲート電極層とは異なる電位の電圧をかけることにより電子を電界集束させる集束電極層を設けることが考えられる。しかし、このようにすると、製造工程の最後に、放出凹部の内周面に成膜された炭素層によって、ゲート電極層と集束電極層とが導通してしまう。これによりゲート電極層と集束電極層とが同電位となり、両者間に十分な電位差を生じさせることができず、電子を集束させることができなくなる問題が想定される。
なお、ゲート電極層および集束電極層は、特に、タングステン(W)で構成されていることが好ましく、その他、Si,Al,Ti,TiN,Cu,Ag,Cr,Au,Pt,C等の金属で構成されていても良い。
図1に示すように、電子放出素子1は、カソード電極層2と、カソード電極層2上に積層され、アモルファスシリコン(a-Si)で構成された電子放出層3と、電子放出層3上に形成され、複数の電極層および複数の絶縁体層から成る電極層部4と、を有している。電極層部4は、電子放出層3上に成膜された第1絶縁体層5と、第1絶縁体層5上に成膜された集束電極層6と、集束電極層6上に成膜された第2絶縁体層7と、第2絶縁体層7上に成膜されたゲート電極層8と、を有している。また、電極層部4には、各層を貫通し、底部に電子放出層3が露出した凹状の電子放出凹部10が形成されており、この電子放出層3の露出部分に面放出部9、すなわちエミッションサイトが構成されている。さらに、ゲート電極層8の表面および電子放出凹部10の内周面には、炭素層11が成膜されており、炭素層11と電子放出凹部10の内周面との間には、酸化シリコン(SiOX)で構成された絶縁性のサイドウォール12が形成されている。なお、詳細は後述するが、電子放出素子1(電子放出凹部10)のアレイにより、撮像素子(画素)113が構成されている(図7参照)。
サイドウォール12は、集束電極層6と炭素層11との間の絶縁が目的であるため、本変形例は、サイドウォール12を集束電極層6と炭素層11の間にのみに形成し、ゲート電極層8の層端と炭素層11との間は導通状態となっている。
以下、図8ないし図10を参照し、本発明の第2実施形態に係る電子放出素子1ついて説明する。上記の第1実施形態では、電極層部4において、ゲート電極層8の下方に集束電極層6が成膜されているが、第2実施形態では、電極層部4において、ゲート電極層8の上方に集束電極層6が成膜されている。なお、以下の説明において、第1実施形態と同様の構成部分は、同様の符号を付し、詳細な説明を省略する。
サイドウォール12は、集束電極層6と炭素層11との間の絶縁が目的であるため、本変形例は、サイドウォール12を集束電極層6と炭素層11の間にのみに形成している。
そして、電子放出素子1を備えた撮像装置100は、放出された電子を効率よく光電変換層123の表面に集束することができ、省電力型且つ検出精度が高いものとなる。
3 電子放出層 5 第1絶縁体層
6 集束電極層 7 第2絶縁体層
8 ゲート電極層 9 面放出部
10 電子放出凹部 11 炭素層
12 サイドウォール 12a 上部サイドウォール
12b 下部サイドウォール 50 第3絶縁体層
100 撮像装置 110 電子放出基板部
111 シリコン基板 120 受光基板部
121 ガラス基板 122 アノード電極層
123 光電変換層 130 メッシュ電極
Claims (10)
- 面放出部から電子を放出する電子放出層と、
第1絶縁体層を介して前記電子放出層の表面に成膜され、放出された電子を集束させる集束電極層と、
第2絶縁体層を介して、前記集束電極層の表面に成膜されたゲート電極層と、
前記ゲート電極層、前記第2絶縁体層、前記集束電極層および前記第1絶縁体層を貫通して、前記面放出部の表面に凹状に開口する放出凹部と、
前記ゲート電極層の表面から前記放出凹部の内周面に亘って成膜された炭素層と、
前記集束電極層と前記炭素層とを絶縁する部分絶縁部と、を備えたことを特徴とする電子放出素子。 - 面放出部から電子を放出する電子放出層と、
第1絶縁体層を介して、前記電子放出層の表面に成膜されたゲート電極層と、
第2絶縁体層を介して前記ゲート電極層の表面に成膜され、放出された電子を集束させる集束電極層と、
前記集束電極層の表面に積層された第3絶縁体層と、
前記第3絶縁体層、前記集束電極層、前記第2絶縁体層、前記ゲート電極層および前記第1絶縁体層を貫通して、前記面放出部の表面に凹状に開口する放出凹部と、
前記第3絶縁体層の表面から前記放出凹部の内周面に亘って成膜された炭素層と、
前記集束電極層と前記炭素層とを絶縁する部分絶縁部と、を備えたことを特徴とする電子放出素子。 - 前記部分絶縁部は、
前記炭素層と前記ゲート電極層との間に介設したサイドウォール、
前記炭素層と前記第2絶縁体層との間に介設したサイドウォール、
前記炭素層と前記集束電極層との間に介設したサイドウォール、
前記炭素層と前記第1絶縁体層との間に介設したサイドウォール、
のうち、少なくとも前記炭素層と前記集束電極層との間に介設したサイドウォールで構成されていることを特徴とする請求項1に記載の電子放出素子。 - 前記部分絶縁部は、
前記炭素層と前記第3絶縁体層との間に介設したサイドウォール、
前記炭素層と前記集束電極層との間に介設したサイドウォール、
前記炭素層と前記第2絶縁体層との間に介設したサイドウォール、
前記炭素層と前記ゲート電極層との間に介設したサイドウォール、
前記炭素層と前記第1絶縁体層との間に介設したサイドウォール、
のうち、少なくとも前記炭素層と前記集束電極層との間に介設したサイドウォールで構成されていることを特徴とする請求項2に記載の電子放出素子。 - 前記サイドウォールの膜厚(膜幅)は、前記第2絶縁体層の絶縁性能と略同一になる厚さに形成されていることを特徴とする請求項3または4に記載の電子放出素子。
- 前記電子放出層は、アモルファスシリコンで構成され、
前記部分絶縁部は、酸化物または窒化物で構成されていることを特徴とする請求項1または2に記載の電子放出素子。 - 前記ゲート電極層の電位に対し、前記集束電極層の電位が低くなるようにそれぞれ電圧が印加されることを特徴とする請求項1または2に記載の電子放出素子。
- 前記集束電極層の電位が、マイナスの電位であることを特徴とする請求項7に記載の電子放出素子。
- 前記放出凹部は、電子放出方向に拡開形成されていることを特徴とする請求項1または2に記載の電子放出素子。
- 請求項1ないし9のいずれかに記載の電子放出素子、およびカソード電極を有する電子放出基板部と、
真空空間を存して前記電子放出基板部に対面し、光電変換層およびアノード電極を有する受光基板部と、を備えたことを特徴とする撮像装置。
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