Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49575—Assemblies of semiconductor devices on lead frames
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
  • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
  • H01L23/4334—Auxiliary members in encapsulations
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49517—Additional leads
  • H01L23/49531—Additional leads the additional leads being a wiring board
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/495—Lead-frames or other flat leads
  • H01L23/49541—Geometry of the lead-frame
  • H01L23/49548—Cross section geometry
  • H01L23/49551—Cross section geometry characterised by bent parts
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/27—Manufacturing methods
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/191—Disposition
  • H01L2924/19101—Disposition of discrete passive components
  • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/191—Disposition
  • H01L2924/19101—Disposition of discrete passive components
  • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding

Definitions

• the present invention relates generally to integrated circuit packages. More particularly, a module design involving an embedded substrate and leadframe is described.
• IC integrated circuit
• Some packaging techniques contemplate the creation of electronic modules that incorporate multiple electronic devices (e.g. integrated circuits, passive components such as inductors, capacitor, resisters or ferromagnetic materials, etc.) into a single package.
• electronic devices e.g. integrated circuits, passive components such as inductors, capacitor, resisters or ferromagnetic materials, etc.
• an integrated circuit package that includes a substrate, a leadframe and an integrated circuit that is sandwiched between the substrate and the leadframe.
• Various implementations involve attaching electrical components (e.g., inductors, resistors, capacitors, integrated circuits, field effect transistors, etc.) to one or both sides of the substrate.
• the active face of the integrated circuit is electrically and physically connected with the substrate.
• the back side of the integrated circuit is mounted on a die attach pad of the leadframe. Multiple leads of the leadframe are physically attached and electrically coupled with the substrate.
• a molding material encapsulates portions of the substrate, the leadframe and the integrated circuit.
• a metal clip is attached to the die attach pad and one or more of the electrical devices. Portions of the metal clip and/or the die attach pad may be left exposed on the exterior of the integrated circuit package to facilitate heat dissipation.
• Some implementations involve a leadframe having one or more ground leads that are physically and electrically coupled to both the substrate and the die attach pad of the leadframe.
• an integrated circuit package in another embodiment, has a leadframe with a die attach pad and multiple leads, wherein the die attach pad is downset relative to the leads.
• An integrated circuit is mounted on the die attach pad and is also physically and electrically connected to a substrate.
• a molding material encapsulates portions of the substrate, the leadframe and the integrated circuit.
• a method of forming the aforementioned integrated circuit package involves attaching electrical components to one or both sides of a substrate panel and singulating the panel to form multiple populated substrates that are each suitable for use in a single integrated circuit package.
• multiple substrates are attached with a leadframe panel, which is later encapsulated in molding material and singulated to form multiple integrated circuit packages.
• FIG. 1 is a diagrammatic side view of an integrated circuit module according to one embodiment of the present invention.
• FIG. 2 is a flow chart that describes a method for fabricating an integrated circuit module according to one embodiment of the present invention.
• FIGS. 3A is a perspective view of a substrate after multiple integrated circuits have been mounted on the substrate according to one embodiment of the present invention.
• FIG. 3B is a diagrammatic perspective view of the substrate of FIG. 3A after multiple electrical components have been mounted on the substrate.
• FIG. 3C is a diagrammatic perspective view of the substrate of FIG. 3B after a leadframe has been attached with the substrate.
• FIG. 3D is a diagrammatic perspective view of the substrate of FIG. 3C after a metal clip has been added.
• FIG. 3E is a diagrammatic perspective view of the substrate of FIG. 3D after encapsulation.
• FIG. 3F is a diagrammatic cross-sectional view of the integrated circuit package of FIG. 3E.
• the present invention relates generally to the packaging of electronic modules that include one or more integrated circuits and other electronic components.
• a common challenge for module package design is finding a balance between package size, internal device density and heat dissipation.
• National Semiconductor Corporation has developed various module designs that address such issues, including some described in Application No. 12/390,349, entitled “Integrated Circuit Micro-Module,” filed February 20, 2009, and its related applications.
• the present invention relates to an integrated circuit package with an embedded leadframe and substrate.
• At least one and possibly many electronic devices e.g., integrated circuits, field effect transistors, inductors, capacitors, resistors, etc.
• electronic devices e.g., integrated circuits, field effect transistors, inductors, capacitors, resistors, etc.
• multiple electronic devices are densely arranged on the substrate and electrically connected through traces on the substrate.
• a metal clip can be attached to the substrate and at least some of the electronic devices. Portions of the metal clip and/or the leadframe may be left exposed on the exterior of the package to help dissipate heat from electronic devices within the package.
• the integrated circuit package 100 includes a substrate 102 and a leadframe 108 that sandwiches an integrated circuit 112.
• one or more electrical components e.g., capacitors, resistors, inductors, integrated circuits, etc.
• the integrated circuit 112 is mounted on a die attach pad 104 of the leadframe 108, which is downset relative to the leads 106.
• the leads 106 of the leadframe 108 are arranged to electrically connect with the substrate 102 via contact pads 101.
• some of the leads are ground leads 107 that are electrically coupled to both the substrate 102 and the die attach pad 104.
• a metal clip 114 is attached to the die attach pad 104 and the top surfaces of some of the electrical components 110.
• a molding material 116 encapsulates portions of the leadframe 108, the substrate 102, the integrated circuit 112 and the electrical components 110.
• the integrated circuit package 100 is arranged to support multiple, embedded electronic devices and to effectively dissipate heat generated by the devices. More particularly, multiple electrical components are mounted on both sides of the substrate 102.
• the electrical components on the top surface of the substrate 102 are passive components (e.g., inductors, capacitors, resisters, etc.) and/or the electrical components on the opposing bottom surface of the substrate 102 are integrated circuits, although this is not a requirement. Signals are routed between the attached electrical components through the substrate 102.
• the metal clip 114 and/or the die attach pad 104 are exposed on the exterior of the integrated circuit package 110 and thus help dissipate heat generated by the integrated circuit 113 and the electrical components 110.
• the metal clip 114 also helps shield the internal electrical components from electromagnetic interference.
• integrated circuits 304 are attached to a substrate 302 (step 202 of FIG. 2).
• the integrated circuits 304 are attached in flip chip arrangement, although any suitable method known in the art may used to electrically connect one or more integrated circuits 304 to the substrate 302 (e.g., wire bonding, etc.)
• any suitable method known in the art may be used to electrically connect one or more integrated circuits 304 to the substrate 302 (e.g., wire bonding, etc.)
• wire bonding e.g., wire bonding, etc.
• the substrate 302 can be arranged in any suitable manner that allows for the routing of electrical signals between components bonded with the substrate 302.
• the substrate 302 may be a laminated electronic board including an inner interconnect layer made of one or more conductive traces and vias and an outer layer made of a suitable dielectric material 305 (e.g., solder mask). Exposed portions of the interconnect form component bonding sites (not shown) and lead contact pads 306 on the exterior surface(s) of the substrate 302.
• the active surfaces of the integrated circuits 304 are mounted on the underlying component bonding sites and are electrically coupled with the lead contact pads 306 via the interconnect layer of the substrate 302.
• one or more electrical components may be attached to the other side of the substrate 302 (step 204) to form the populated substrate component 308 of FIG. 3B.
• step 204 is optional and can be performed before, after or generally at the same time as step 202.
• the electrical components 310 are passive components (e.g., inductors, resistors, capacitors, etc.), although in other implementations the electronic components 310 may include other types of devices (e.g., integrated circuits.)
• Each of the electrical components 310 is mounted on a respective component bonding site on the substrate 302, which is in turn electrically coupled with the integrated circuits 304 via the interconnect layer of the substrate 302.
• the attaching of electrical devices can be performed on a smaller substrate 302 suitable for use in forming a single integrated circuit package, or a larger substrate panel.
• multiple electrical components e.g., integrated circuits, passive components, etc.
• the substrate panel is singulated to form multiple populated substrate components 308 of FIG. 3B.
• the populated substrate component 308 is then connected with a leadframe 312, as shown in FIG. 3C.
• the leadframe 312 and the leads 314 of the leadframe 312 physically support the populated substrate component 308 and electrically connect it with external electrical devices.
• the back sides of the integrated circuits 304 are mounted on the die attach pad 316, which is recessed or downset relative to the leads 314.
• the leads 314 each include an attachment surface 318 that is electrically and physically attached to a lead contact pad 306 on the substrate 302.
• the lead contact pads 306 are electrically coupled with the interconnect layer of the substrate 302 and provide electrical access to the various components that are mounted on the substrate 302.
• each ground lead 311 has a multi- tiered structure and connects to the downset die attach pad 316.
• the electrical and physical connection between the ground lead 311 and the die attach pad 316 may be formed in any appropriate manner.
• the ground lead 311 may be integral to and continuous with the die attach pad 316.
• the ground lead 311 may also be separate from and attached to the die attach pad 316 using a suitable connecting structure (e.g., a solder joint, an electrically conductive adhesive, etc.)
• a suitable connecting structure e.g., a solder joint, an electrically conductive adhesive, etc.
• the back side of each integrated circuit 304 includes a ground pad (not shown) that electrically connects the integrated circuit 304 with the die attach pad 316, although this is not a requirement.
• a common ground connection is accessible to the integrated circuits 304 and the ground leads 311.
• the ground lead 311 includes an attachment surface 318 that is electrically connected to the substrate 302.
• the attachment surface 318 is elevated relative to the die attach pad 316 and is substantially parallel to the die attach pad 316 and the substrate 302.
• the attachment surface 316 comes into electrical and physical contact with the lead contact pads 306 situated at the edge of the substrate 302.
• the electrical connection between the substrate 302 and the ground lead 311 can be arranged in various other ways as well.
• the ground lead 311 may be electrically connected to the substrate 302 via an edge surface or the top surface 313 of the substrate 302 rather than through the bottom surface 315 of the substrate 302.
• a thermally conductive metal clip 318 may optionally be added, as shown in FIG. 3D.
• the metal clip 318 is arranged to help dissipate heat from the interior of the package.
• the metal clip 318 is physically and thermally coupled with the die attach pad 316 and some of the electrical components 310 mounted on the substrate 302. Heat generated by the integrated circuits 304 and the electrical components 310 can be transferred outside of the integrated circuit package through the metal clip 318.
• the metal clip 318 may be arranged in a wide variety of ways, depending on the needs of a particular application. By way of example, the metal clip 318 in FIG.
• 3D has a L-shaped section that includes two connected, substantially perpendicular surfaces.
• One surface 318a which is attached to the substrate 302, extends perpendicular to the die attach pad 316.
• the other surface 318b extends substantially parallel to and overlies the die attach pad 316, the substrate 302 and the active surfaces of the integrated circuits 304.
• a subset of the electrical components 310 extends high enough from the underlying substrate 302 to be thermally and physically coupled with the metal clip 318.
• This L-shaped configuration helps the metal clip 318 be an effective thermal conduit for both the integrated circuits 314 and the attached subset of electrical components 310.
• the metal clip 318 can also help shield covered electrical components from electromagnetic interference.
• the metal clip 318 may be arranged to enclose the substrate 302 to a greater extent e.g., the metal clip 318, together with the die attach pad 316, may form an open ended box around the substrate 302, the electrical components 310 and the integrated circuits 304. Some embodiments involve electrically grounding the metal clip 318 by electrically coupling it with a ground die attach pad 316 and/or ground leads 311.
• portions of the substrate 302, the leadframe 312, the integrated circuits 304 and the electrical components 310 are encapsulated in a molding material.
• the encapsulation is performed in a manner that leaves portions of the die attach pad 316 and/or the metal clip 318 exposed in order to dissipate additional heat from the interior of the package, as shown in FIG. 3F, which is a diagrammatic side view of the integrated circuit package 330 of FIG. 3E.
• a leadframe panel with an array of device areas can be provided.
• Each device area of the leadframe panel includes multiple leads and a downset die attach pad similar to those shown in FIGS. 3C.
• the arrangement of the leadframe panel may have been formed using any appropriate technique known in the art.
• the aforementioned leadframe panel features and/or the downsetting of the die attach pad of each device area relative to the leads of the device area may have been formed by stamping a metal sheet.
• Multiple populated substrates 308 of FIG. 3B and/or metal clips 318 of FIG. 3D can be attached to each device area, as described in steps 206 and 208 of FIG. 2.
• Portions of the leadframe panel may then be encapsulated in molding material and singulated to form multiple integrated circuit packages 330 of FIGS. 3E and 3F.
• FIG. 3E depicts leads that are in a gull-wing configuration and that extend out of only one side of the integrated circuit package 330.
• the present invention also contemplates leads that do not extend at all out of the package or that extend out of almost any number of surfaces of the package (e.g., a leadless leadframe package, a dual inline package, a quad inline package, etc.).
• each method step illustrated in FIG. 2 may be reordered, modified and/or eliminated as appropriate for particular applications. Referring now to FIG.
• the integrated circuits 304 and the lead contact pads 306 are illustrated as being on the same surface of the substrate 302.
• the lead contact pads 306 are positioned at the edges of the substrate 304.
• this arrangement works well for various applications, but other arrangements are also contemplated by the present invention (e.g., the lead contact pads 306 and/or the integrated circuits 304 may be positioned on any side of the substrate 304, etc.) Therefore, the present embodiments should be considered as illustrative and not restrictive and the invention is not limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Geometry (AREA)
• Health & Medical Sciences (AREA)
• Electromagnetism (AREA)
• Toxicology (AREA)
• Lead Frames For Integrated Circuits (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

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• 2009
  • 2009-12-10 US US12/635,624 patent/US8304887B2/en active Active
• 2010
  • 2010-10-25 WO PCT/US2010/053974 patent/WO2011071603A2/en not_active Ceased
  • 2010-10-25 JP JP2012543100A patent/JP2013513942A/ja active Pending
  • 2010-10-25 CN CN201080042885.1A patent/CN102576702B/zh active Active
  • 2010-11-12 TW TW099138958A patent/TWI523157B/zh active

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