WO2011058750A1 - プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 - Google Patents
プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
- G09G3/2932—Addressed by writing selected cells that are in an OFF state
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/025—Reduction of instantaneous peaks of current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
Definitions
- the present invention relates to an AC surface discharge type plasma display device and a method for driving a plasma display panel.
- a plasma display panel (hereinafter abbreviated as “panel”) includes a front substrate on which a plurality of display electrode pairs composed of scan electrodes and sustain electrodes long in the row direction are formed, and a back substrate on which a plurality of data electrodes long in the column direction are formed. Are arranged opposite to each other, and a discharge cell is formed at each of the positions where the display electrode pair and the data electrode cross three-dimensionally (hereinafter simply referred to as “intersection”).
- the plasma display device includes a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit to drive the above-described panel, and displays an image by applying a drive voltage waveform necessary for each electrode. Device.
- a subfield method in which gradation display is performed by dividing one field period into a plurality of subfields and then combining the subfields to emit light is generally used.
- Each subfield has an initialization period, an address period, and a sustain period.
- an initialization discharge is generated, and an initialization operation for forming wall charges necessary for the subsequent address operation is performed.
- an address pulse is applied to each of the data electrodes in accordance with an image to be displayed, and an address operation for selectively generating an address discharge in the discharge cells is performed. Wall charges are formed in the discharge cells that have generated the address discharge.
- a sustain operation is performed in which the number of sustain pulses corresponding to the luminance weight is generated and applied alternately to the scan electrodes and the sustain electrodes. By the sustain operation, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer emits light. Thus, an image is displayed on the panel.
- the plasma display device is provided with an electrode drive circuit for generating a drive voltage waveform applied to the electrode of the panel for each electrode.
- the data electrode drive circuit is a drive circuit that applies an address pulse corresponding to an image signal to each data electrode and generates an address discharge in each discharge cell.
- the transition time of the rising and falling edges of the address pulse generated by the data electrode driving circuit is shorter than that of the sustain pulse, for example. Therefore, when a write pulse is generated, a large current flows instantaneously. This large current is caused by unnecessary radiation (unnecessary electromagnetic waves emitted by electronic devices) such as electromagnetic line radiation (electromagnetic noise emitted through the power line) and housing radiation (electromagnetic noise emitted from the electronic device main body). (Generic name for noise).
- Patent Document 1 has a structure in which a metal back cover in which a portion covering a shield case is cut is attached to a chassis member, and the metal case and the metal back cover are electrically connected via a conductive gasket.
- a plasma display device is disclosed.
- the present invention drives a panel by forming a single field using a panel having a plurality of discharge cells each having a display electrode pair consisting of scan electrodes and sustain electrodes and data electrodes, and a plurality of subfields having an address period.
- a plasma display device including a drive circuit.
- the drive circuit generates image data representing light emission / non-light emission in each subfield of the discharge cell based on the image signal, generates a write pulse based on the image data during the write period, and uses it as a write timing signal.
- a data electrode driving circuit that generates an address pulse at a synchronized timing and applies the data pulse to the data electrode, and a timing generation circuit that generates an address timing signal and supplies the address signal to the data electrode driving circuit.
- the data electrode drive circuit has a delay unit that delays the write timing signal by a predetermined time, calculates the load capacity of the data electrode for each data electrode based on the image data, and calculates the calculated load capacity for each data electrode. Based on this, a write pulse is generated at a timing synchronized with either the write timing signal before being delayed in the delay unit or the write timing signal delayed in the delay unit.
- the generation timing of the write pulse can be distributed according to the load capacity of the data electrode, so the timing of the discharge current flowing through the data electrode is distributed to suppress unnecessary radiation such as line radiation and housing radiation, and stable writing. A discharge can be generated.
- the present invention also provides a panel for driving a panel that includes a plurality of sub-fields having an address period to form a single field and includes a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode and a data electrode.
- This is a driving method.
- image data representing light emission / non-light emission in each subfield of the discharge cell is generated.
- an address pulse is generated based on the image data, and at the timing synchronized with the address timing signal, the address pulse is generated and applied to the data electrode.
- the write timing signal is delayed by a predetermined time.
- the load capacity of the data electrode is calculated for each data electrode based on the image data. Then, for each data electrode, a write pulse is generated at a timing synchronized with either the pre-delayed write timing signal or the delayed write timing signal based on the calculated load capacitance.
- the generation timing of the write pulse can be distributed according to the load capacity of the data electrode. Therefore, the discharge current flows through the data electrode to suppress unnecessary radiation such as line radiation and housing radiation, and stable writing. A discharge can be generated.
- FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 3 is a diagram schematically showing the interelectrode capacitance of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 5 is a circuit block diagram of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 6 is a circuit block diagram of the data driver of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 7A is a circuit diagram of the self-load calculation unit in the load calculation unit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 7B is a circuit diagram of the adjacent load calculation unit in the load calculation unit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 7C is a circuit diagram of a control signal output unit in the load calculation unit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 8 is a diagram schematically showing a load capacitance generated in one data electrode of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 9A is a diagram schematically showing generation of unnecessary radiation when a synchronization signal input to a latch included in a data latch unit in the plasma display device according to the embodiment of the present invention is adaptively delayed according to a display image. It is.
- FIG. 9B is a diagram schematically showing generation of unnecessary radiation when the synchronization signals input to the latches included in the data latch unit in the plasma display device in accordance with the exemplary embodiment of the present invention are all set at the same timing.
- FIG. 10 is a circuit block diagram of a data driver of a plasma display apparatus in another embodiment of the present invention.
- FIG. 11 schematically shows the generation of unnecessary radiation when the synchronization signal input to the latch included in the data latch unit in the plasma display apparatus according to another embodiment of the present invention is adaptively delayed according to the display image.
- FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed.
- a dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15.
- a plurality of data electrodes 22 are formed on the back substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon.
- a phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.
- the front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 cross each other across a minute discharge space, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. It is worn.
- the discharge space is filled with, for example, a mixed gas of neon and xenon as a discharge gas.
- the discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light, whereby an image is displayed on the panel 10.
- the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
- FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to the embodiment of the present invention.
- the panel 10 includes n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) that are long in the row direction (line direction). Are arranged, and m data electrodes D1 to Dm (data electrodes 22 in FIG. 1) that are long in the column direction are arranged.
- M ⁇ n are formed.
- capacitor capacitance generated between the electrodes, hereinafter also simply referred to as “capacitance”.
- FIG. 3 is a diagram schematically showing the interelectrode capacitance of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 3 shows five scan electrodes SCi-2 to SCi + 2, five sustain electrodes SUi-2 to sustain electrode SUi + 2, and six data electrodes Dj-2 to data electrode Dj + 3.
- the scan electrode 12 and the sustain electrode 12 are not shown as separate lines but as one pair of display electrodes 14 as one thick line.
- the interelectrode capacitance related to the data electrode D1 to the data electrode Dm is shown as a capacitance Cc and a capacitance Cs.
- a capacitance Cs exists in each of the portions where the display electrode pair 14 and the data electrode 22 intersect.
- a capacitance Cc exists between the adjacent data electrode 22 and the data electrode 22.
- one data electrode Dj intersects n scan electrodes SC1 through SCn and n sustain electrodes SU1 through SUn. Therefore, in the panel 10, there is a capacitance (n ⁇ Cs) between the data electrode Dj and all the display electrode pairs 14 (n display electrode pairs 14).
- this capacity (n ⁇ Cs) is expressed as a capacity Cg.
- one data electrode 22 includes a capacitance Cg generated between all the display electrode pairs 14, a capacitance Cc generated between the data electrode 22 adjacent to the right side, and a data electrode adjacent to the left side. 22 and the capacitance Cc generated between the two. That is, the total load capacitance generated in one data electrode 22 is capacitance Cg + 2Cc, and this capacitance is generated in each data electrode 22.
- the subfield method is a method of performing gradation display by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield.
- Each subfield has an initialization period, an address period, and a sustain period.
- one field is composed of eight subfields (SF1, SF2,..., SF8), and each subfield has (1, 2, 4, 8, 16, 32, 64, 128) luminance weights are set.
- this subfield configuration is merely an example, and the present invention is not limited to the subfield configuration shown here.
- FIG. 4 is a diagram showing drive voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 4 shows drive voltage waveforms in two subfields of subfield SF1 and subfield SF2.
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn are moved from voltage Vi1 to voltage Vi2. Apply a ramp voltage that rises slowly.
- Voltage Vi1 is a voltage equal to or lower than the discharge start voltage for sustain electrode SU1 through sustain electrode SUn
- voltage Vi2 is a voltage that exceeds the discharge start voltage for sustain electrode SU1 through sustain electrode SUn.
- weak initializing discharges are generated between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through SCn and data electrode D1 through data electrode Dm.
- voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and a ramp voltage that gradually decreases from voltage Vi3 to voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn.
- Voltage Vi3 is a voltage that is equal to or lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn
- voltage Vi4 is a voltage that exceeds the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
- voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn
- voltage Vc is applied to scan electrode SC1 through scan electrode SCn
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm.
- a scan pulse of voltage Va is applied to scan electrode SC1 in the first line
- An address discharge is generated in the discharge cells in the first line to which the scan pulse and the address pulse are simultaneously applied, and an address operation for accumulating wall charges in the scan electrode SC1 and the sustain electrode SU1 is performed.
- no address discharge occurs, and the wall voltage after the end of the initialization period is maintained.
- the same address operation is sequentially performed for each line from the discharge cell of the second line to the discharge cell of the n-th line, and an address discharge is selectively generated for the discharge cells to emit light.
- a wall charge is formed in the discharge cell.
- the data electrode 22 viewed from the data electrode driving circuit is a capacitive load as shown in FIG.
- the write pulse has a shorter transition time at the rising edge and a transition time at the falling edge than, for example, a sustain pulse generated using the power recovery circuit. Therefore, in order to generate such an address pulse, when applying the address pulse to each of the data electrodes 22 from the data electrode driving circuit, a large current is instantaneously passed, and the load capacitance of the data electrode 22 is changed shortly. It is necessary to charge in time (hereinafter, the maximum value of the current that flows instantaneously is referred to as “peak current”).
- the plasma display device in the present embodiment has a configuration for suppressing such unnecessary radiation.
- voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of voltage Vs is applied to scan electrode SC1 through scan electrode SCn.
- a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer 25 emits light by the ultraviolet rays generated at this time.
- voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn.
- the sustain discharge occurs again in the discharge cell that has generated the sustain discharge immediately before, and the discharge cell emits light.
- the number of sustain pulses corresponding to the luminance weight is generated and applied alternately to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, so that the discharge cells that have caused the address discharge are applied according to the luminance weight. It emits light with a high brightness.
- the maintenance period ends.
- the voltage Vr is set to the same voltage as the voltage Vs in the present embodiment, the voltage Vr may be a voltage different from the voltage Vs.
- the discharge cell is caused to emit light with a luminance corresponding to the luminance weight.
- FIG. 5 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention.
- the plasma display device 30 includes a panel 10 in which a plurality of discharge cells having scan electrodes 12, sustain electrodes 13, and data electrodes 22 are arranged, and a drive circuit that drives the panel 10.
- the drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.
- the image signal processing circuit 31 assigns a gradation value to each discharge cell based on the input image signal. Each gradation value is converted into image data and output.
- the image data is data in which light emission / non-light emission in each subfield of the discharge cell is associated with “1” and “0” of each bit of the digital signal.
- the data electrode drive circuit 32 converts the image data output from the image signal processing circuit 31 into address pulses corresponding to the data electrodes D1 to Dm, and applies the data pulses to the data electrodes D1 to Dm.
- the data electrode drive circuit 32 is divided into a plurality of circuits, and one circuit is configured to drive a predetermined number of data electrodes 22.
- Each circuit is integrated in one semiconductor integrated circuit (monolithic IC). This monolithic IC is hereinafter referred to as a “data driver”. That is, the data electrode drive circuit 32 is configured using a plurality of data drivers 40.
- the predetermined number is 384, and circuits for driving 384 data electrodes 22 are integrated as one data driver 40.
- the data electrode driving circuit 32 is configured using eight data drivers 40.
- the timing generation circuit 35 generates various timing signals for controlling the operation of each circuit based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit.
- Scan electrode driving circuit 33 drives each of scan electrode SC1 through scan electrode SCn based on the timing signal supplied from timing generation circuit 35.
- Sustain electrode drive circuit 34 drives sustain electrode SU1 through sustain electrode SUn based on the timing signal supplied from timing generation circuit 35.
- FIG. 6 is a circuit block diagram of the data driver 40 of the plasma display device 30 according to the embodiment of the present invention.
- the data driver 40 includes a shift register unit 141, a data latch unit 142, a write pulse output unit 143, a write timing control unit 144, and a write timing generation unit 145.
- the shift register unit 141 has a plurality of latches 41.
- the latch 41 outputs an input signal triggered by a change in the synchronization signal.
- a clock signal Dck is input to the latch 41 as a synchronization signal.
- the input signal is output in synchronization with the timing at which the clock signal Dck changes from Lo to Hi.
- the clock signal Dck is a signal (clock signal) that repeats Lo and Hi at a predetermined cycle. Therefore, the latch 41 operates as a delay circuit that outputs an input signal with a delay of one clock cycle of the clock signal Dck.
- a plurality of latches 41 are connected in series so that the output of the latch 41j is input to the latch 41j + 1 at the next stage.
- the input signal is gradually delayed by a delay time corresponding to the cycle of the clock signal Dck in synchronization with the clock signal Dck.
- the shift register unit 141 has at least the same number of latches 41 as the data electrodes 22 driven by the data driver 40. Then, the bit Q (hereinafter simply referred to as “image data Q”) corresponding to the subfield of the serially transferred image data is gradually delayed in synchronization with the clock signal Dck.
- Serial transfer is one of data transfer methods, and is a data transfer method for transferring data consisting of a plurality of bits bit by bit. For example, in the case of 8-bit data, 8 continuous digital signals (“1” or “0”) are transferred as 1-bit signals.
- serially transferred image data Q is sequentially passed through the plurality of latches 41 connected in series, thereby being delayed by one clock cycle of the clock signal Dck (hereinafter referred to as serial data).
- the transferred data is also simply referred to as “serial data”).
- the operation of the data driver 40 is described on the assumption that one data driver 40 drives the three data electrodes 22 of the data electrode Dj ⁇ 1, the data electrode Dj, and the data electrode Dj + 1. To do.
- the image data Q is obtained by converting a bit signal indicating lighting / non-lighting corresponding to each data electrode 22 in each subfield into a serial signal. Therefore, in this example, the image data Q includes data indicating lighting / non-lighting corresponding to each of the data electrode Dj ⁇ 1, the data electrode Dj, and the data electrode Dj + 1.
- the image data Q includes data “1, 0, 1” that is continuous in time.
- the image data Q includes data corresponding to each data electrode 22 in a temporally continuous state.
- an address pulse must be applied simultaneously to each data electrode 22.
- data “1, 0, 1” must be assigned to the data electrode Dj ⁇ 1, the data electrode Dj, and the data electrode Dj + 1 at the same time.
- the shift register unit 141 has a function of taking out a plurality of pieces of continuous data at the same timing.
- the shift register unit 141 sequentially delays the image data Q in synchronization with the clock signal Dck using a plurality of latches 41 connected in series. Therefore, at a certain moment, the image data Qj-1 corresponding to the data electrode Dj-1 is output from the latch 41j-1, the image data Qj corresponding to the data electrode Dj is output from the latch 41j, and the data electrode Dj + 1 is output from the latch 41j + 1.
- the correct image data Q corresponding to the data electrode 22 ahead of the latch 41 is output from each latch 41.
- the signal output from the latch 41 changes at the next timing when the clock signal Dck changes.
- image data Qj-2 corresponding to the data electrode Dj-2 is output from the latch 41j-1
- image data Qj-1 corresponding to the data electrode Dj-1 is output from the latch 41j.
- the image data Qj corresponding to the data electrode Dj is output from the latch 41j + 1.
- the image data Q not corresponding to each data electrode 22 is output from each latch 41.
- the data driver 40 needs to hold the image data Q when the correct image data Q corresponding to the data electrode 22 ahead of the latch 41 is output from each latch 41.
- the data latch unit 142 performs this operation.
- the data latch unit 142 has the same number of latches 42 as the latches 41 in the shift register unit 141.
- the latch 42 corresponds to each of the data electrodes 22 driven by the data driver 40, and is connected to the corresponding latch 41.
- the latch 42j-1 corresponding to the data electrode Dj-1 receives the output of the latch 41j-1
- the latch 42j corresponding to the data electrode Dj receives the output of the latch 41j
- the output of the latch 41j + 1 is input to the latch 42j + 1.
- Each latch 42 is supplied with a write timing signal Le obtained by adjusting the delay time of the write timing signal Le0 generated by the timing generation circuit 35 in the write timing generation unit 145 as a synchronization signal. For example, an input signal is output using a change from Lo to Hi as a trigger.
- the write timing signal Le0 is, for example, a positive pulse waveform that periodically becomes Hi for one clock of the clock signal Dck and then becomes Lo.
- the period in which the write timing signal Le0 becomes Hi is equal to the period in which the write pulse is generated.
- the write timing signal Le0 is generated in the timing generation circuit 35 so that each latch 41 changes from Lo to Hi at the timing when correct data corresponding to the data electrode 22 ahead of the latch 41 is output.
- the latch 42 holds the output signal while the write timing signal Le is Lo. Therefore, each latch 42 operates to output a signal output from each latch 41 at a correct timing based on the write timing signal Le and hold the output signal. As a result, the signal output from the latch 42 becomes the image data DQ corresponding to the data electrode 22 ahead of the latch 42. For example, when the image data Qj is output from the latch 41j, the latch 42j takes in the image data Qj and outputs the image data DQj corresponding to the data electrode Dj.
- the write timing signal Le input as a synchronization signal to each latch 42 is applied to the panel 10 in the write timing generator 145 with respect to the write timing signal Le0 generated by the timing generator 35.
- This signal is obtained by adjusting the delay time according to the displayed image. Details of this will be described later.
- the write pulse output unit 143 has the same number of write pulse generation units 43 as the latches 41 in the shift register unit 141, and each write pulse generation unit 43 corresponds to each of the data electrodes 22 driven by the data driver 40. .
- the write pulse generator 43 generates a write pulse to be applied to each data electrode 22 driven by the data driver 40. For example, an address pulse output from the address pulse generator 43j is applied to the data electrode 22Dj, and an address pulse output from the address pulse generator 43j + 1 is applied to the data electrode 22Dj + 1.
- the write pulse generator 43 has an output buffer.
- the output buffer includes a switching element Tr1 that outputs a voltage Vd on the high voltage side of the write pulse and a switching element Tr2 that outputs a voltage 0 (V) on the low voltage side of the write pulse.
- a switching element Tr1 that outputs a voltage Vd on the high voltage side of the write pulse
- Tr2 that outputs a voltage 0 (V) on the low voltage side of the write pulse.
- an address pulse of voltage Vd is generated. That is, the output buffer applies the write pulse to the data electrode 22 by connecting the data electrode 22 to the voltage Vd or the voltage 0 (V) based on the image data DQ.
- this switching element is represented by a symbol representing an FET (Field Effect Transistor).
- the write pulse generator 43 generates a write pulse according to the image data DQ output from the latch 42. If the image data DQ is “1” (Hi), the switching element Tr1 that outputs the high-voltage side voltage Vd is turned on to apply the voltage Vd to the data electrode 22, and the image data DQ is “0” (Lo). For example, the switching element Tr ⁇ b> 2 that outputs the low voltage 0 (V) is turned on to apply the voltage 0 (V) to the data electrode 22.
- the image data DQ changes in synchronization with the write timing signal Le output from the write timing generator 145. Therefore, the timing at which the write pulse is output from the write pulse generator 43 is synchronized with the write timing signal Le.
- the output buffer included in the write pulse generator 43 has a current capacity (current) that can drive a capacitive load having a capacity (Cg + 4Cc) that is a capacity when the driving load of the data electrode 22 becomes maximum. Supply capability). Therefore, when the driving load on the data electrode 22 is reduced, the amount of current (peak current) that instantaneously flows from the data driver 40 to the data electrode 22 when an address pulse is generated increases, and unnecessary radiation increases. Therefore, in this embodiment, for the purpose of reducing unnecessary radiation, a write timing signal obtained by adjusting the delay time to the write timing signal Le0 in the write timing generation unit 145 based on the calculation result in the write timing control unit 144. Le is used as a synchronization signal. Details of this will be described later.
- the write timing control unit 144 has the same number of load calculation units 44 as the latches 41 in the shift register unit 141.
- the load calculation unit 44 corresponds to each of the data electrodes 22 driven by the data driver 40, and the control signal C that is an output signal of the load calculation unit 44 is input to the corresponding write timing selection unit 45.
- the load calculation unit 44 includes a self-load calculation unit 50, an adjacent load calculation unit 60, and a control signal output unit 70.
- the size of the load capacitance in each of the data electrodes 22 driven by the data driver 40 is expressed as an image Calculate based on data Q.
- the load calculation unit 44j has a self-load calculation unit 50j, an adjacent load calculation unit 60j, and a control signal output unit 70j, and calculates the size of the load capacitance of the data electrode Dj based on the image data Qj.
- the control signal Cj based on the result is output.
- the write timing generation unit 145 includes a plurality of delay units and the same number of write timing selection units 45 as the latches 41 in the shift register unit 141.
- the delay unit includes three delay units, that is, a delay unit 46a, a delay unit 46b, and a delay unit 46c.
- the delay unit 46a delays the write timing signal Le0 generated by the timing generation circuit 35 by “first time T1” and outputs it as “first write timing signal Le1”.
- the delay unit 46b delays the write timing signal Le0 by “second time T2” and outputs it as “second write timing signal Le2”.
- the delay unit 46c delays the write timing signal Le0 by “third time T3” and outputs it as “third write timing signal Le3”.
- the second time T2 is set to 50 nsec
- the third time T3 is set. Is set to 100 nsec, which is approximately twice the second time T2.
- the third write timing signal Le3 may be generated by setting the delay unit 46c to the same delay time as the delay unit 46b and passing the output of the delay unit 46b through the delay unit 46c.
- the write timing selection unit 45 corresponds to each of the data electrodes 22 driven by the data driver 40, and the output signal of the write timing selection unit 45 is input to the corresponding latch 42 as a synchronization signal.
- the write timing selection unit 45j-1 corresponds to the data electrode Dj-1, and the output signal of the write timing selection unit 45j-1 is input to the latch 42j-1 as a synchronization signal.
- a write timing selection unit 45j corresponds to the data electrode Dj, and an output signal of the write timing selection unit 45j is input to the latch 42j as a synchronization signal.
- the write timing selector 45j + 1 corresponds to the data electrode Dj + 1, and the output signal of the write timing selector 45j + 1 is input to the latch 42j + 1 as a synchronization signal.
- Each write timing selection unit 45 is composed of a selection circuit that selects and outputs one of two input signals based on the control signal C.
- the write timing signal Le0 supplied from the timing generation circuit 35 is input to one input terminal of the write timing selection unit 45 (for example, the input terminal selected when the control signal C is “1”).
- the other input terminal of the write timing selection unit 45 receives the first write timing signal Le1 output from the delay unit 46a.
- One of the three signals of the second write timing signal Le2 output from the delay unit 46b and the third write timing signal Le3 output from the delay unit 46c is input.
- three consecutive write timing selection units 45 (for example, write timing selection unit 45j-1, write timing selection unit 45j, write timing selection unit 45j + 1) are set as one set.
- Each of the timing selectors 45 receives a write timing signal Le having a different delay time from the other input terminal.
- the first write timing signal Le1 is input to the other input terminal of the write timing selection unit 45j-1
- the second write timing signal Le2 is input to the other input terminal of the write timing selection unit 45j.
- the third write timing signal Le3 is input to the other input terminal of the selector 45j + 1.
- write timing signals Le having different delay times are input to the other input terminals in each of the other set of write timing selection units 45.
- the write timing signal Le output from the write timing generation unit 145 is all It becomes equal to the write timing signal Le0. If all the control signals C output from the write timing controller 144 are “0”, one third of the write timing signal Le output from the write timing generator 145 becomes the first write timing signal Le1. One third is the second write timing signal Le2, and one third is the third write timing signal Le3.
- the write timing selection unit 45 outputs the write timing signal Le having a different delay time in accordance with the control signal C output from the write timing control unit 144.
- the image data DQ is output from the latch 42 at a timing corresponding to the write timing signal Le
- the write pulse is output from the write pulse generator 43 at a timing corresponding to the image data DQ.
- the generation timing of the write pulse output from the write pulse generator 43 is controlled based on the result calculated by the load calculator 44.
- the number of latches 42, write pulse generation unit 43, load calculation unit 44, and write timing selection unit 45 is the same as the number of latches 41 in the shift register unit 141.
- the number of latches 42, write pulse generators 43, load calculators 44, and write timing selectors 45 may be equal to or greater than the number of data electrodes driven by the data driver 40.
- FIG. 7A is a circuit diagram of self-load calculation unit 50 in load calculation unit 44 of plasma display device 30 in the exemplary embodiment of the present invention.
- FIG. 7B is a circuit diagram of the adjacent load calculation unit 60 in the load calculation unit 44 of the plasma display device 30 according to the embodiment of the present invention.
- FIG. 7C is a circuit diagram of control signal output unit 70 in load calculation unit 44 of plasma display device 30 in the exemplary embodiment of the present invention.
- the self-load calculation unit 50j, the adjacent load calculation unit 60j, and the control signal output unit 70j included in the load calculation unit 44j corresponding to the data electrode Dj will be described. The same applies to the other load calculation units 44. It is the composition.
- the self-load calculation unit 50j includes a logic gate 51j, a logic gate 52j, and a logic gate 53j.
- Image data Qj and image data DQj which are image data for the data electrode Dj, are input to each logic gate.
- the output of logic gate 51j is output HLj
- the output of logic gate 52j is output LHj
- the output of logic gate 53j is output Xj.
- the self-load calculating unit 50j detects an address operation in the discharge cell one line (one horizontal synchronization period) before the target discharge cell with respect to the address operation in the target discharge cell.
- the discharge cell one line before is, for example, a discharge cell immediately above the discharge cell of interest when each discharge cell of the panel 10 is sequentially addressed from the upper line to the lower line.
- the discharge cell immediately below the target discharge cell becomes the discharge cell one line before.
- the discharge cell of interest A discharge cell immediately above or directly below it with one discharge cell in between becomes the discharge cell one line before.
- the “discharge cell before one line” in the present embodiment is a discharge cell before one line (one horizontal synchronization period) in the address operation, and the data electrode 22 with respect to the discharge cell of interest.
- it is not limited to discharge cells adjacent in the extending direction (discharge cells adjacent immediately above or immediately below in panel 10).
- the self-load calculation unit 50j an address operation in a discharge cell of interest (for example, a discharge cell in a region where the data electrode Dj, the scan electrode SCi, and the sustain electrode SUi intersect) and a discharge cell one line before (for example, data
- the address operation in the discharge cell in the region where the electrode Dj intersects with the scan electrode SCi-1 and the sustain electrode SUi-1 will be compared. That is, the self-load calculation unit 50j includes an address pulse applied to the target discharge cell on the data electrode Dj and an address pulse applied to the discharge cell one line before the target discharge cell on the data electrode Dj. Detect relative changes.
- the self-load calculating unit 50j needs to compare the image data DQj (i) for the target discharge cell with the image data DQj (i-1) for the discharge cell one line before the target discharge cell. .
- the image data Qj is serial data as described above, and includes image data Qj (i) corresponding to the image data DQj (i) for the discharge cell of interest. Therefore, by appropriately delaying the image data DQj output from the latch 42j and input to the self-load calculation unit 50j, the self-load calculation unit 50j allows the discharge cell one line before the target discharge cell. A moment occurs when the timing of the image data DQj (i-1) and the image data Qj (i) corresponding to the image data DQj (i) of the discharge cell of interest are aligned. In the drawing, a circuit for this delay is omitted.
- the self-load calculation unit 50j obtains the calculation result of the image data DQj (i-1) and the image data DQj-1 (i), the image data DQj (i-1) and the image data. Unnecessary computation results such as computation results with the data DQj + 1 (i) are output.
- the load calculation unit 44j requires an operation for holding a calculation result at an appropriate timing when a required logical operation is performed in the self-load calculation unit 50j.
- the control signal output unit 70j in the subsequent stage performs this operation. That is, in the present embodiment, the control signal output unit 70j is operated so as to hold data at an appropriate timing at which a required logical operation is performed.
- the image data DQj input to the self-load calculating unit 50j is the image data DQj (i-1) relating to the discharge cell one line before the target discharge cell, and the image data Qj is The description will be made assuming that the image data is DQj (i) regarding the discharge cell of interest.
- the logic gate 51j and the logic gate 52j are logical gates that perform an AND operation, and output “1 (Hi)” only when the signals input to the two input terminals are both “1 (Hi)”. Then, “0 (Lo)” is output.
- one of the input terminals of the logic gate 51j and the logic gate 52j is circled. However, this represents an inverter, and an operation of inverting logic (“1” becomes “0”, “ “0” becomes “1”). Therefore, the image data Qj is logically inverted and input to the logic gate 51j, and the image data DQj is logically inverted and input to the logic gate 52j.
- the logic gate 51j outputs “1” when the image data DQj is “1” and the image data Qj is “0”, and outputs “0” otherwise.
- the logic gate 52j outputs “1” when the image data DQj is “0” and the image data Qj is “1”, and outputs “0” otherwise.
- the logic gate 53j is a logic gate that performs an exclusive OR operation.
- the operation result is “1” only when one of the signals input to the two input terminals is “0” and the other is “1”.
- the calculation result is “0”.
- the output terminal of the logic gate 53j since the output terminal of the logic gate 53j is circled, the operation result of the logic gate 53j is logically inverted and output. Therefore, the logic gate 53j outputs “1” only when both the image data DQj and the image data Qj are “0” or both “1”, and outputs “0” otherwise.
- the self-load calculating unit 50j when the discharge cell one line before the target discharge cell is turned on and the target discharge cell is not turned on, that is, the image data DQj (i ⁇ 1) is “1”. Yes, when the image data Qj (i) is “0”, the output HLj of the logic gate 51j is “1”, and the outputs LHj and Xj are “0”.
- the discharge cell one line before the target discharge cell is not lit and the target discharge cell is lit, that is, the image data DQj (i ⁇ 1) is “0”, and the image data DQj (i ) Is “1”, the output LHj of the logic gate 52j is “1”, and the output HLj and the output Xj are “0”.
- the image data DQj (i ⁇ 1) when the discharge cell one line before the target discharge cell is not lit and the target discharge cell is also not lit, that is, the image data DQj (i ⁇ 1) is “0”, and the image data DQj When (i) is also “0”, and when the discharge cell one line before the target discharge cell is turned on and the target discharge cell is also turned on, that is, the image data DQj (i ⁇ 1) is “1”. And the image data DQj (i) is also “1”, the output Xj of the logic gate 53j is “1”, and the outputs HLj and LHj are “0”.
- the adjacent load calculation unit 60j includes a logic gate 61j, a logic gate 62j, a logic gate 63j, a logic gate 64j, a logic gate 65j, a logic gate 66j, a logic gate 67j, a logic gate 68j, and a logic gate 69j.
- a logic gate 61j a logic gate 62j, a logic gate 63j, a logic gate 64j, a logic gate 65j, a logic gate 66j, a logic gate 67j, a logic gate 68j, and a logic gate 69j.
- the output of the self-load calculating unit 50j corresponding to the data electrode Dj, the output of the self-load calculating unit 50j-1 corresponding to the data electrode Dj-1 adjacent to the data electrode Dj, and the data electrode adjacent to the data electrode Dj Based on the output of the self-load calculation unit 50j + 1 corresponding to Dj + 1, the magnitude of the load on the capacitance Cc between the data electrode Dj and the data electrode Dj-1 and between the data electrode Dj and the data electrode Dj + 1 is calculated. That is, the load generated in the data electrode 22 belonging to the target discharge cell by comparing the image data for the target discharge cell with the image data for the discharge cell adjacent to the target discharge cell in the direction in which the display electrode pair 14 extends. Calculate capacity.
- the logic gate 61j, the logic gate 62j, the logic gate 64j, the logic gate 66j, the logic gate 67j, and the logic gate 69j are logic gates that perform an AND operation.
- the logic gate 63j, the logic gate 65j, and the logic gate 68j are logic gates that perform an OR operation, and output “0” only when both signals input to the two input terminals are “0”. Then, “1” is output.
- the logic gate 61j receives the output HLj-1 that is the output of the self-load calculation unit 50j-1 and the output LHj that is the output of the self-load calculation unit 50j, and only when each input is “1”. "1" is output, otherwise "0" is output.
- the logic gate 62j receives the output LHj-1 that is the output of the self-load calculation unit 50j-1 and the output HLj that is the output of the self-load calculation unit 50j, and only when each input is “1”. "1" is output, otherwise "0" is output.
- the logic gate 66j receives the output HLj + 1 that is the output of the self-load calculation unit 50j + 1 and the output LHj that is the output of the self-load calculation unit 50j, and outputs “1” only when both inputs are “1”. Otherwise, “0” is output.
- the logic gate 67j receives the output LHj + 1 that is the output of the self-load calculation unit 50j + 1 and the output HLj that is the output of the self-load calculation unit 50j, and outputs “1” only when both inputs are “1”. Otherwise, “0” is output.
- the logic gate 65j receives the output HLj and the output LHj which are the outputs of the self-load calculation unit 50j, outputs “0” only when both inputs are “0”, and outputs “1” otherwise. To do.
- the output of the logic gate 61j and the output of the logic gate 62j are input to the logic gate 63j, and “0” is output only when both inputs are “0”, and “1” is output otherwise.
- the output of the logic gate 66j and the output of the logic gate 67j are input to the logic gate 68j, and “0” is output only when both inputs are “0”, and “1” is output otherwise.
- the logic gate 64j receives the output Xj-1 that is the output of the self-load calculation unit 50j-1 and the output of the logic gate 65j, and outputs "1" only when both inputs are “1". Otherwise, “0” is output.
- the logic gate 69j receives the output Xj + 1, which is the output of the self-load calculation unit 50j + 1, and the output of the logic gate 65j, and outputs “1” only when both inputs are “1”. 0 "is output.
- the output of the logic gate 63j is the output L2j
- the output of the logic gate 64j is the output L1j
- the output of the logic gate 68j is the output R2j
- the output of the logic gate 69j is the output R1j.
- the adjacent load calculation unit 60j changes between the lines of the image data Qj-1 of the data electrode Dj-1 adjacent to the left side of the data electrode Dj (from the image data DQj-1 (i-1) to the image data DQj- 1 (i) changes in phase with the change (change from image data DQj (i ⁇ 1) to image data DQj (i)) between the lines of image data Qj of data electrode Dj.
- the output of the logic gate 61j or the logic gate 62j is “1”, and the output L2j of the logic gate 63j is “1”.
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data adjacent to the left side of the data electrode Dj.
- the logic gate The output L1j of 64j becomes “1”.
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data adjacent to the right side of the data electrode Dj.
- the output R1j of the logic gate 69j is “1”. It becomes.
- the control signal output unit 70j has a logic gate 71j, a logic gate 72j, and a latch 73j, and outputs a control signal Cj for controlling the write timing selection unit 45j.
- the control signal Cj controls the selection operation of the write timing selection unit 45j.
- the number of latches in the control signal output unit 70j is set according to the number of output buffers included in the write pulse generation unit 43j.
- the logic gate 71j is a logic gate that performs an OR operation
- the logic gate 72j is a logic gate that performs an AND operation.
- the logic gate 72j receives the output L1j and the output R1j output from the adjacent load calculation unit 60j, outputs “1” only when both inputs are “1”, and outputs “0” otherwise. To do.
- the logic gate 71j receives the output L2j, the output R2j, and the output signal of the logic gate 72j output from the adjacent load calculation unit 60j, and outputs “0” only when each input is “0”. Otherwise, “1” is output.
- a timing signal LE generated in the timing generation circuit 35 is input to the latch 73j as a synchronization signal, and an input signal is output using a change in the synchronization signal (for example, a change from Lo to Hi) as a trigger. .
- the timing signal LE is omitted.
- the output signal of the latch 73j is supplied as a control signal Cj to the write timing selection unit 45j.
- the timing signal LE is, for example, a positive pulse waveform that periodically becomes Hi for one clock cycle of the clock signal Dck and then becomes Lo.
- the period in which the timing signal LE becomes Hi is equal to the period in which the write pulse is generated.
- the timing signal LE is used for each calculation described above at the moment when the timing of the image data DQj (i ⁇ 1) and the image data Qj (i) corresponding to the image data DQj (i) is aligned.
- the result is generated in the timing generation circuit 35 so as to be held in the latch 73j.
- the output signal is appropriately adjusted so that control signal Cj is updated in synchronization with the timing at which the write pulse is output from write pulse generator 43j. .
- control signal Cj output from the control signal output unit 70j becomes “0” when the pattern A and the pattern B are described later.
- the control signal Cj is “1”.
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i-1) and the image data DQj (i) have different values), and the left side of the data electrode Dj
- Both the change between the lines of the image data Qj-1 of the data electrode Dj-1 adjacent to the line and the change between the lines of the image data Qj + 1 of the data electrode Dj + 1 adjacent to the right side of the data electrode Dj are both lines of the image data Qj.
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data electrode Dj ⁇ adjacent to the data electrode Dj ⁇ 1 and the change between the lines of the image data of one of the data electrodes Dj + 1 are in phase with the change between the lines of the image data Qj (for example, the image data DQj-1 (i-1) and the image data DQj (I-1) has the same value, and the image data DQj-1 (i) and the image data DQj (i) have the same value), and the image data of the other data electrode does not change between lines ( For example, when the image data DQj + 1 (i ⁇ 1) and the image data DQj + 1 (i) have the same value), the output L1j and the output R1j of the adjacent load calculation unit 60j Re or the other only becomes “1", and the other output L1j and output R1j, and output L2j, becomes "0" and the output R2j
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data electrode Dj ⁇ adjacent to the data electrode Dj ⁇ 1 image data Qj ⁇ 1 and image data Qj + 1 of the data electrode Dj + 1 do not change between lines (the image data DQj ⁇ 1 (i ⁇ 1) and the image data DQj ⁇ 1 (i) have the same value, When the image data DQj + 1 (i ⁇ 1) and the image data DQj + 1 (i) have the same value), or the image data Qj changes between lines, and one of the data electrode Dj ⁇ 1 and the data electrode Dj + 1
- the change between the lines of the image data of the data electrode of the image data is opposite to the change between the lines of the image data Qj (for example, the image data DQj-1 (i-1) and the image Data DQj (i-1) is different from each other, and image data DQj-1 (i) and image data DQj (i) are
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data electrode Dj ⁇ adjacent to the data electrode Dj ⁇ 1, the change between the lines of the image data of one of the data electrodes Dj + 1 is out of phase with the change between the lines of the image data Qj (for example, the image data DQj-1 (i-1) and the image data DQj (I-1) becomes a different value, and the image data DQj-1 (i) and the image data DQj (i) have different values), and the image data of the other data electrode does not change between lines ( For example, when the image data DQj + 1 (i ⁇ 1) and the image data DQj + 1 (i) have the same value), either the output L2j or the output R2j of the adjacent load calculation unit 60j One is "1" or, becomes “1” output R1j is if the output L2j becomes "1", if the output R2j becomes "1
- the image data Qj of the data electrode Dj changes between lines (the image data DQj (i ⁇ 1) and the image data DQj (i) have different values), and the data electrode Dj ⁇ adjacent to the data electrode Dj ⁇
- the change between the lines of the image data Qj-1 of the image data Qj-1 and the image data Qj + 1 of the data electrode Dj + 1 is in reverse phase to the change between the lines of the image data Qj (image data DQj-1 (i-1) and image data DQj + 1 (I-1) is different from the image data DQj (i-1), and the image data DQj-1 (i) and the image data DQj + 1 (i) are different from the image data DQj (i). ),
- the output L2j and the output R2j of the adjacent load calculation unit 60j are both “1”. Therefore, the control signal Cj is “1”. This is a pattern F described later.
- the load capacity of the data electrode Dj is the capacity Cg in the pattern A and the capacity (Cg + Cc) in the pattern B. Therefore, when the load capacitance of the data electrode Dj is equal to or less than the capacitance (Cg + Cc), the control signal Cj is “0”.
- the load capacitance of the data electrode Dj is the capacitance (Cg + 2Cc) in the pattern C and the pattern D, the capacitance (Cg + 3Cc) in the pattern E, and the capacitance (Cg + 4Cc) in the pattern F. Therefore, when the load capacitance of the data electrode Dj is greater than or equal to the capacitance (Cg + 2Cc), the control signal Cj is “1”.
- the “write timing signal Le0” and the “first write timing signal Le1” obtained by delaying the write timing signal Le0 by the “first time T1”.
- Any of “second write timing signal Le2” in which write timing signal Le0 is delayed by “second time T2” and “third write timing signal Le3” in which write timing signal Le0 is delayed by “third time T3” Is output as the write timing signal Le.
- the control signal C is “1”
- the write timing signal Le0 is output as the write timing signal Le.
- any one of the first write timing signal Le1, the second write timing signal Le2, and the third write timing signal Le3 is output as the write timing signal Le.
- the write timing signal Le is input to the latch 42 of the data latch unit 142 as a synchronization signal.
- the latch 42 outputs the image data DQ in synchronization with the write timing signal Le input as a synchronization signal, and the write pulse generator 43 generates a write pulse in synchronization with the image data DQ.
- the write pulse generator 43 outputs a write pulse synchronized with the write timing signal Le0.
- the control signal C is “0”, that is, when the load capacitance of the data electrode 22 is equal to or less than the capacity (Cg + Cc)
- the write pulse generator 43 sends the first write timing signal Le1 or the second write timing signal.
- a write pulse synchronized with Le2 or the third write timing signal Le3 is output.
- the write pulse output from the write pulse generation unit 43 is one third.
- One third is synchronized with the first write timing signal Le1
- one third is synchronized with the second write timing signal Le2
- one third is synchronized with the third write timing signal Le3. Accordingly, in one write operation, write pulses having different rising timings are applied from the data driver 40 to the data electrode 22.
- the output buffer of the write pulse generator 43 has a current capacity (current supply capability) that can drive a capacitive load having a capacity (Cg + 4Cc) when the driving load of the data electrode 22 is maximized. ing. Therefore, when the driving load of the data electrode 22 is reduced, the amount of current (peak current) that instantaneously flows from the write pulse generator 43 to the data electrode 22 when the write pulse is generated increases. At this time, if the rising timings of the write pulses output from the data driver 40 are aligned, the timing at which the peak current flows is aligned. Therefore, a very large current instantaneously flows from the data driver 40 to the data electrode 22 and is large. Unnecessary radiation may occur.
- the control signal C becomes “0”, and the write pulse generator 43 outputs the first write timing signal Le1 or the second A write pulse synchronized with the write timing signal Le2 or the third write timing signal Le3 is output. That is, in one write operation, the data driver 40 writes a write pulse synchronized with the first write timing signal Le1, a write pulse synchronized with the second write timing signal Le2, and a write synchronized with the third write timing signal Le3. A pulse is mixed and output.
- the rising timing of the write pulse applied to the data electrode 22 is dispersed and the timing at which the peak current flows is dispersed, and the maximum value of the current that instantaneously flows from the data driver 40 to the data electrode 22 is reduced. Radiation can be reduced.
- the amount of current (peak current) that instantaneously flows from the address pulse generator 43 to the data electrode 22 when the address pulse is generated is also suppressed. Even when the rising timings of the output write pulses are aligned, there is little possibility that large unnecessary radiation will occur.
- the timing at which the address pulse is generated can be appropriately dispersed according to the display image, the address discharge can be stably generated, and unnecessary radiation can be suppressed. The reason will be described below.
- the latch 73 is set. Can be omitted.
- FIG. 8 is a diagram schematically showing a load capacitance generated in one data electrode Dj of the plasma display device 30 in the embodiment of the present invention.
- FIG. 8 shows the change between the lines of the image data Qj of the data electrode Dj, the change between the lines of the image data Qj ⁇ 1 of the data electrode Dj ⁇ 1, and the line of the image data Qj + 1 of the data electrode Dj + 1. The change is shown schematically.
- the data electrode Dj has the capacitance Cg between the entire display electrode pair 14 and the capacitance Cc (hereinafter referred to as “capacitance”) between the data electrode Dj-1 adjacent to the left side of the data electrode Dj. Ccl ”) and a capacitor Cc (hereinafter referred to as“ capacitor Ccr ”) exists between the data electrode Dj + 1 adjacent to the right side of the data electrode Dj.
- the write pulse generator 43j When the image data Qj of the data electrode Dj changes from “0” to “1” between lines, the write pulse generator 43j must charge the capacitor Cg. At this time, if the change between the lines of the image data Qj-1 of the data electrode Dj-1 is in phase with the change between the lines of the image data Qj and changes from “0” to “1”, it is necessary to charge the capacitor Ccl. There is no. Therefore, the capacitance Ccl is substantially zero. Further, when the change between the lines of the image data Qj + 1 of the data electrode Dj + 1 is in phase with the change between the lines of the image data Qj and changes from “0” to “1”, it is not necessary to charge the capacitor Ccr. Therefore, the capacitance Ccr is also substantially zero. Therefore, the load capacitance (equivalent capacitance) generated at the data electrode Dj at this time is the capacitance Cg. This is the “pattern A” shown in FIG.
- the write pulse generator 43j must charge the capacitor Ccl in addition to the capacitor Cg.
- Cg + Cc capacitance Cc
- the change between the lines of the image data Qj + 1 of the data electrode Dj + 1 is in phase with the change between the lines of the image data Qj.
- the capacitance Ccr is substantially 0, but writing The pulse generator 43j has to charge the capacitor Ccl against the reverse phase image data Qj-1, and the current required for charging the data electrode Dj is 2 when the image data Qj-1 does not change between lines. Double.
- the load of the data electrode Dj changes in five stages.
- FIGS. 9A and 9B are diagrams for comparing the generation conditions of unnecessary radiation in the plasma display device.
- FIG. 9A schematically shows generation of unnecessary radiation when the synchronization signal input to the latch 42 included in the data latch unit 142 in the plasma display device 30 according to the embodiment of the present invention is adaptively delayed according to the display image.
- FIG. 9B is a diagram schematically showing the generation of unnecessary radiation when the synchronization signals input to the latches 42 included in the data latch unit 142 in the plasma display device 30 according to the embodiment of the present invention are all set at the same timing.
- 9A and 9B schematically show the load capacitance (equivalent capacitance), the waveform shape of the write pulse, and unnecessary radiation generated in the data electrode 22, respectively.
- the output buffer of the address pulse generator 43 is set so that it rises appropriately at the transition time and the address discharge is generated stably.
- the current supply capability of the output buffer included in the write pulse generator 43 is set in accordance with the maximum driving load of the data electrode 22, and therefore, as shown in FIG. 9B, the data electrode 22 As the driving load of the output electrode decreases, the capacity (Cg + 3Cc), the capacity (Cg + 2Cc), the capacity (Cg + Cc), and the capacity Cg become smaller.
- the rise of the pulse gradually becomes steeper, the current (peak current) that flows instantaneously increases, and unnecessary radiation also increases.
- the driving load is reduced.
- the rising timing of the write pulse output from the write pulse output unit 143 can be dispersed.
- the timing at which the peak current flows from the write pulse output unit 143 to the data electrode 22 can be dispersed to reduce the maximum value of the current flowing from the data driver 40 to the data electrode 22, thereby preventing an increase in unnecessary radiation. Can do.
- the synchronization signal input to the latch 42 provided in the data latch unit 142 is adaptively delayed in accordance with the drive load capacity generated in the data electrode 22. That is, when the driving load generated in the data electrode 22 exceeds the capacity (Cg + 2Cc), the timing signal Le input to the latch 42 is the timing signal Le0. When the driving load of the data electrode 22 is equal to or less than the capacity (Cg + Cc), the timing signal Le input to the latch 42 is the first write timing signal Le1, the second write timing signal Le2, and the third write timing signal Le3. And either. Thus, an excessive current is prevented from being supplied to the data electrode 22 when an address pulse is generated.
- the timing at which the pulse rises can be distributed (in this embodiment, distributed to three), and the timing at which the address discharge occurs can be distributed.
- the timing at which the discharge current flows from the address pulse output unit 143 to the data electrode 22 is dispersed (the timing at which the peak current flows is divided into three), The maximum value of the current flowing through the data electrode 22 can be suppressed, and the address discharge can be stably generated while suppressing the generation of unnecessary radiation.
- the present invention is not limited to this configuration. It is not a thing.
- the capacity at which the drive load of the data electrode 22 is distributed determines the timing of generating the write pulse according to the magnitude of unnecessary radiation generated, the characteristics of the panel 10, the specifications of the plasma display device 30, and the like. Good.
- the present embodiment a configuration in which a time interval of 100 nsec is provided between the first write timing signal Le1 and the third write timing signal Le3 has been described.
- the write timing signal Le that occurs earliest and the latest that occurs latest. It is desirable that the time interval provided between the write timing signal Le and the write timing signal Le is optimally set within a range where one write operation can be stably performed.
- the present invention is not limited to this configuration.
- the timing for generating the write pulse is divided into three by the first write timing signal Le1, the second write timing signal Le2, and the third write timing signal Le3 each having a time interval of 50 nsec.
- the configuration has been described, how many timings to generate the write pulse are distributed, and at what time interval the write pulse is generated, whether one write operation can be performed stably, It is desirable to set according to the magnitude of unnecessary radiation, the characteristics of the panel 10, the specifications of the plasma display device 30, and the like. For example, the structure which distributes the timing which generate
- two timings for generating the write pulse for example, the first write timing signal Le1 and the second write timing signal. It is also possible to configure the data driver with Le2) by distributing the timing of generating the write pulse into two and simplifying the circuit configuration.
- FIG. 10 is a circuit block diagram of the data driver 49 of the plasma display device according to another embodiment of the present invention.
- the data driver 49 includes a shift register unit 141, a data latch unit 142, a write pulse output unit 143, a write timing control unit 144, and a write timing generation unit 148.
- circuit blocks that operate in the same manner as the data driver 40 shown in FIG.
- the write timing generation unit 148 has the same number of delay units 48 and write timing selection units 45 as the latches 41 in the shift register unit 141.
- the delay unit 48 is connected in series and sequentially delays the write timing signal Le0.
- the delay time in one delay unit 48 is set to 0.3 nsec. Accordingly, the write timing signal Le0j output from the j-th delay unit 48j among the plurality of delay units 48 connected in series is a signal obtained by delaying the write timing signal Le0 by (0.3 ⁇ j) nsec.
- the write timing signal Le0 supplied from the timing generation circuit 35 is input to one input terminal of the write timing selection unit 45 (for example, the input terminal selected when the control signal C is “1”).
- the signal output from the delay unit 48 is input to the other input terminal of the write timing selection unit 45 (for example, the input terminal selected when the control signal C is “0”).
- the write timing signal Le0j-1 output from the delay unit 48j-1 is input to the other input terminal of the write timing selection unit 45j-1, and the delay unit 48j is input to the other input terminal of the write timing selection unit 45j. Is input with a write timing signal Le0j.
- the operation of the write timing selection unit 45 is the same as that of the write timing selection unit 45 shown in FIG.
- FIG. 11 schematically shows generation of unnecessary radiation when the synchronization signal input to the latch 42 included in the data latch unit 142 is adaptively delayed in accordance with the display image in the plasma display apparatus according to another embodiment of the present invention.
- FIG. FIG. 11 schematically shows a load capacitance (equivalent capacitance), a waveform shape of an address pulse, and unnecessary radiation generated in the data electrode 22.
- the control signal C is “1” when the load capacitance of the data electrode 22 is greater than or equal to the capacitance (Cg + 2Cc), and the control signal C when the load capacitance of the data electrode 22 is less than or equal to the capacitance (Cg + Cc).
- 11 is set to “0”, as shown in FIG. 11, when the load capacitance of the data electrode 22 is equal to or less than the capacitance (Cg + Cc), the rising edge of the write pulse is dispersed. For example, if all the control signals C are “0”, the rising timing of the write pulse output from the data driver 49 differs for each data electrode 22.
- the shift register unit 141 has one shift register and one serial image data Q is input to the shift register unit 141 in this embodiment, the present invention is not limited to this. It is not something.
- the shift register unit includes three shift registers so as to correspond to the image data Qr, image data Qg, and image data Qb of the primary color signal of red, the primary color signal of green, and the primary color signal of blue.
- the data Qr, the image data Qg, and the image data Qb may be rearranged as the image data Q according to the order of the arrangement of the data electrodes 22.
- the specific circuit configuration shown in the present embodiment is shown as an example of the circuit configuration, and the present invention is not limited to these circuit configurations. Other circuit configurations may be used as long as the functions described above can be realized.
- the latch described in this embodiment may be configured to operate with a negative synchronization signal, and the synchronization signal input to each latch may be a negative pulse signal.
- the present invention can generate a stable address discharge while suppressing unnecessary radiation such as line radiation and housing radiation, it is useful as a driving method for a plasma display device and a panel.
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Abstract
Description
図1は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネル10の構造を示す分解斜視図である。ガラス製の前面基板11上には、走査電極12と維持電極13とからなる表示電極対14が複数形成されている。そして、走査電極12と維持電極13とを覆うように誘電体層15が形成され、その誘電体層15上に保護層16が形成されている。背面基板21上にはデータ電極22が複数形成され、データ電極22を覆うように誘電体層23が形成され、さらにその上に井桁状の隔壁24が形成されている。そして、隔壁24の側面および誘電体層23上には赤色、緑色および青色の各色に発光する蛍光体層25が設けられている。
11 前面基板
12 走査電極
13 維持電極
14 表示電極対
15,23 誘電体層
16 保護層
21 背面基板
22 データ電極
24 隔壁
25 蛍光体層
30 プラズマディスプレイ装置
31 画像信号処理回路
32 データ電極駆動回路
33 走査電極駆動回路
34 維持電極駆動回路
35 タイミング発生回路
40,49 データドライバ
41,42,73 ラッチ
43 書込みパルス発生部
44 負荷算出部
45 書込みタイミング選択部
46,46a,46b,46c,48 遅延部
50 自己負荷算出部
51,52,53,61,62,63,64,65,66,67,68,69,71,72 論理ゲート
60 隣接負荷算出部
70 制御信号出力部
141 シフトレジスタ部
142 データラッチ部
143 書込みパルス出力部
144 書込みタイミング制御部
145,148 書込みタイミング発生部
Cg,Cc,Cs,Ccl,Ccr 容量
Claims (8)
- 走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたプラズマディスプレイパネルと、
書込み期間を有するサブフィールドを複数用いて1つのフィールドを構成して前記プラズマディスプレイパネルを駆動する駆動回路とを備えたプラズマディスプレイ装置であって、
前記駆動回路は、
画像信号にもとづき、前記放電セルの各サブフィールドにおける発光・非発光を表す画像データを発生する画像信号処理回路と、
前記書込み期間に、前記画像データにもとづき書込みパルスを発生するとともに書込みタイミング信号に同期したタイミングで前記書込みパルスを発生して前記データ電極に印加するデータ電極駆動回路と、
前記書込みタイミング信号を発生して前記データ電極駆動回路に供給するタイミング発生回路とを備え、
前記データ電極駆動回路は、
前記書込みタイミング信号をあらかじめ定められた時間だけ遅延する遅延部を有し、
前記画像データにもとづき前記データ電極の負荷容量を前記データ電極毎に算出し、
前記データ電極毎に、前記負荷容量にもとづき、前記書込みタイミング信号および前記遅延部において遅延された書込みタイミング信号のいずれかに同期したタイミングで前記書込みパルスを発生することを特徴とするプラズマディスプレイ装置。 - 前記データ電極駆動回路は、
一方の入力端子には前記書込みタイミング信号が入力され、他方の入力端子には前記遅延部において遅延された書込みタイミング信号が入力され、前記負荷容量が大きいときには前記一方の入力端子に入力された書込みタイミング信号を出力し、前記負荷容量が小さいときには前記他方の入力端子に入力された書込みタイミング信号を出力する書込みタイミング選択部を複数有し、
前記書込みタイミング選択部から出力される書込みタイミング信号に同期したタイミングで前記書込みパルスを発生することを特徴とする請求項1に記載のプラズマディスプレイ装置。 - 前記データ電極駆動回路は、
着目する放電セルに対する画像データと、前記着目する放電セルの1水平同期期間前に書込み動作が行われた放電セルに対する画像データとの比較によって前記負荷容量を算出することを特徴とする請求項1に記載のプラズマディスプレイ装置。 - 前記データ電極駆動回路は、
前記着目する放電セルに対する画像データと、前記着目する放電セルに前記表示電極対が延伸する方向に隣接する放電セルに対する画像データとの比較によって前記負荷容量を算出することを特徴とする請求項3に記載のプラズマディスプレイ装置。 - 書込み期間を有するサブフィールドを複数用いて1つのフィールドを構成し、走査電極および維持電極からなる表示電極対とデータ電極とを有する放電セルを複数備えたプラズマディスプレイパネルを駆動するプラズマディスプレイパネルの駆動方法であって、
画像信号にもとづき、前記放電セルの各サブフィールドにおける発光・非発光を表す画像データを発生し、
前記書込み期間に、前記画像データにもとづき書込みパルスを発生するとともに書込みタイミング信号に同期したタイミングで前記書込みパルスを発生して前記データ電極に印加し、
前記書込みタイミング信号をあらかじめ定められた時間だけ遅延するとともに、前記画像データにもとづき前記データ電極の負荷容量を前記データ電極毎に算出し、
前記データ電極毎に、前記負荷容量にもとづき、遅延される前の書込みタイミング信号および前記遅延された書込みタイミング信号のいずれかに同期したタイミングで前記書込みパルスを発生することを特徴とするプラズマディスプレイパネルの駆動方法。 - 前記負荷容量が大きいときには遅延される前の書込みタイミング信号に同期したタイミングで前記書込みパルスを発生し、前記負荷容量が小さいときには前記遅延された書込みタイミング信号に同期したタイミングで前記書込みパルスを発生することを特徴とする請求項5に記載のプラズマディスプレイパネルの駆動方法。
- 着目する放電セルに対する画像データと、前記着目する放電セルの1水平同期期間前に書込み動作が行われた放電セルに対する画像データとの比較によって前記負荷容量を算出することを特徴とする請求項5に記載のプラズマディスプレイパネルの駆動方法。
- 前記着目する放電セルに対する画像データと、前記着目する放電セルに前記表示電極対が延伸する方向に隣接する放電セルに対する画像データとの比較によって前記負荷容量を算出することを特徴とする請求項7に記載のプラズマディスプレイパネルの駆動方法。
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