WO2011055984A2 - Grille de connexion et son procédé de fabrication - Google Patents

Grille de connexion et son procédé de fabrication Download PDF

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Publication number
WO2011055984A2
WO2011055984A2 PCT/KR2010/007730 KR2010007730W WO2011055984A2 WO 2011055984 A2 WO2011055984 A2 WO 2011055984A2 KR 2010007730 W KR2010007730 W KR 2010007730W WO 2011055984 A2 WO2011055984 A2 WO 2011055984A2
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WO
WIPO (PCT)
Prior art keywords
unit
lead
die pad
leadframe
support unit
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Application number
PCT/KR2010/007730
Other languages
English (en)
Other versions
WO2011055984A3 (fr
Inventor
Hyun A Chun
Chung Sik Park
Sai Ran Eom
Hyung Eui Lee
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020090106142A external-priority patent/KR101095527B1/ko
Priority claimed from KR1020090108386A external-priority patent/KR101168890B1/ko
Priority claimed from KR1020090114287A external-priority patent/KR101168412B1/ko
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2011055984A2 publication Critical patent/WO2011055984A2/fr
Publication of WO2011055984A3 publication Critical patent/WO2011055984A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a leadframe and a method for manufacturing the same.
  • Semiconductor packaging is a process that electrically connects individual chips made by a wafer process to be used as electronic components and seals and packages the connected chips to protect them from external impacts.
  • a chip includes a very fine circuit pattern, the chip is easily damaged by humidity, dust, and external impacts. That is, a chip formed on a surface of a wafer is not a complete product until the chip is mounted on a printed circuit board (PCB) as an electronic component. Therefore, a semiconductor packaging process enables chips on a wafer to operate as an individual electronic component by forming an electric wire on the chips. Further, the semiconductor packaging process protects the chips from external impact by sealing and packaging the chips with the electric wires. By the packaging process, the chips on the wafer are finalized as a product.
  • PCB printed circuit board
  • a leadframe plays as an important role in mounting a chip and in providing an input/output means for transferring a signal.
  • Various types of leadframes have been introduced for transferring highly integrated signals.
  • an etching method or a stamping method is used to form a die pad unit and a lead unit.
  • a two-step etching method has been introduced to form a leadframe.
  • the number of lead pins is limited because the two-step etching method has a limitation to reduce an inner lead pitch.
  • a support unit for sustaining a gap between a die pad unit and a lead unit and supporting a leadframe is made of a thin polyimide layer. Accordingly, a supporting force thereof is disadvantageously weak.
  • a leadframe In addition to the weak supporting force, a leadframe has a durability problem because the leadframe does not have a structure for fixing a solder ball adhering to an outer lead in a solder ball process.
  • an electroplating process is performed due to a fast plating speed thereof.
  • copper is generally used as a raw material of a circuit pattern of a lead frame.
  • the copper is easily expanded by environmental variations such as temperature and humidity. Such an expansion of copper may cause a significant defect in a semiconductor package having such a fine structure because the expansion of copper may electrically connect a lead unit to a die pad unit or to another lead unit, which are supposed to be electrically disconnected.
  • the inventors of the present application intend to solve the related art problems in a leadframe and a method for manufacturing the same.
  • An object of the present invention is to provide a leadframe and a manufacturing method thereof for forming a further fine circuit pattern, improving adhesive to a solder ball, and enhancing physical strength of the leadframe.
  • Another object of the present invention is to provide a leadframe and a method for manufacturing the same for preventing a lead from expansion caused by environmental variation and for embodying fine pattern plating with a small plating deviation and a superior plating layer structure.
  • Still another object of the present invention is to provide a leadframe having enhanced physical strength and a method for manufacturing the same.
  • An object of the present invention is to a leadframe including a lead unit having a vertical part and a horizontal part, a die pad unit separated from the lead unit by an support unit formed of insulating material, an inner lead formed adjacent to the die pad unit and on a top surface of the horizontal part of the lead unit, and an outer lead formed on a bottom surface of the vertical part of the lead unit.
  • a bottom surface of the support unit may protrude more than bottom surfaces of the outer lead and the die pad unit.
  • the leadframe may further include an upper metal layer formed on a top surface or a bottom surface of the die pad unit, wherein the inner lead may extend to surround a side of the horizontal part toward the die pad unit or may be separated from a side of the horizontal part with a predetermined gap.
  • the leadframe may further include a support unit, wherein the support unit may include an upper support unit surrounding a top surface of the horizontal part of the lead unit, and a lower support unit surrounding a lower part of the horizontal part of the lead unit.
  • the leadframe may further include a support unit, wherein the support unit may include an upper support unit formed to filling a separation space between the die pad unit and the lead unit, and a lower support unit formed to support a lower part of the horizontal part of the lead unit.
  • the leadframe may further include an insulating layer formed on the horizontal part of the lead unit or on a top surface of the support unit.
  • the leadframe may further include a die pad metal layer formed on a top surface of the die pad unit.
  • the upper metal layer formed on the top surface of the die pad unit may extend to surround a side of the die pad unit toward the lead unit or may be separated from a side of the die pad unit with a predetermined gap.
  • the die pad unit includes a step
  • the upper metal layer of the die pad unit may be formed on an upper part of the step, and the lead frame may further include a lower metal layer formed on a lower part of the step of the die pad unit.
  • the leadframe may further include a metal layer formed on the step to connect the upper metal layer of the step upper part and the lower metal layer of the step lower part.
  • the lower support unit may extend to a bottom surface of the vertical part of the adjacent lead unit.
  • Another object of the present invention is to provide a method for manufacturing a leadframe.
  • an support unit groove, a die pad unit, and a lead unit are formed by etching one side of a metal substrate.
  • a support unit is formed by filling the insulting unit groove with insulating material, and the lead unit is separated from the die pad unit and an inner lead, an outer lead, and a die pad metal layer are formed by plating both sides of the metal substrate.
  • the support unit may be formed to protrude more than a vertical part of the lead unit.
  • the outer lead may be formed to be dented than peripheral area.
  • the inner lead, the outer lead, and the die pad metal layer may be formed by a electroless plating process.
  • an upper support unit may be formed by filling the support unit groove with insulating material
  • a lower support unit may be formed by filling a separation space between the lead unit and the die pad unit with insulating material.
  • an insulating layer may be formed on a support unit of the lead unit.
  • the inner lead may be plated to surround a side of the lead unit forward the die pad unit or may be plated to be separated from the side with a predetermined gap.
  • the lower support unit may extend to a surface of a vertical part of the lead unit.
  • FIG. 1 and FIG. 2 are flowcharts of a method for semiconductor chip packaging using a leadframe in accordance with a first embodiment of the present invention.
  • FIG. 3 and FIG. 4 are flowcharts of a method for packaging a semiconductor chip using a leadframe in accordance with a second embodiment of the present invention.
  • FIG. 5 shows various structures of the inner leads 290a and the die pad metal units 295a and 295b.
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing a leadframe in accordance with a third embodiment of the present invention.
  • FIG. 7 shows a structure that the lower support unit 330b extending to the bottom surface of the vertical part of the lead unit 390.
  • An object of the present invention is to provide a leadframe and a manufacturing method thereof for forming a further fine circuit pattern, improving adhesive to a solder ball, and enhancing physical strength of the leadframe.
  • Another object of the present invention is to provide a leadframe and a method for manufacturing the same for preventing a lead from expansion caused by environmental variation and for embodying fine pattern plating with a small plating deviation and a superior plating layer structure.
  • FIG. 1 and FIG. 2 are flowcharts of a method for semiconductor chip packaging using a leadframe in accordance with a first embodiment of the present invention.
  • a metal substrate 110 for circuit is prepared.
  • the metal substrate 110 may be made of copper (Cu). Further, the metal substrate 110 may be made of conductive metal material such as copper alloy, iron (Fe), or iron alloy.
  • photo resists 120 are formed on top and bottom surfaces of the metal substrate 110.
  • the photo resists 120 may be formed as liquid photo resists (LPR) or dray film resists (DFR). A photolithography process using a photo mask is carried out to expose and develop the photo resists 120 formed on the top and bottom surfaces of the metal substrate 110.
  • the photo resists 120 may be formed only on the bottom surface of the metal substrate 110. However, the photo resists 120 are exemplary formed on the both surfaces of the metal substrate 110 to protect an element of the top surface.
  • step S2 half etching is carried out to form support unit grooves 130, a die pad unit 140, and lead units 150. As shown, the support unit grooves 130, the die pad unit 140, and the lead units 150 are not separated yet.
  • the metal substrate may be exemplary etched more than about 2/3 thickness of the metal substrate.
  • an insulator is coated in the support unit grooves.
  • solder resist (SR) ink may be used as the insulator.
  • CFSR dry film solder resist
  • epoxy may be used as the insulator.
  • support units 170 is formed to have a bottom surface downwardly protruding more than protruding bottom surfaces of the lead unit 150 and the die pad unit 140 through exposing and developing the coated insulator.
  • the support units 170 may be formed to have a bottom surface downwardly protruding more than one of the protruding bottom surfaces of the lead unit 150 and the die pad unit 140.
  • photo resists 120 are coated on top and bottom surfaces (or only on the top surface) and a photolithography process using a photo mask (exposing and developing) is carried out to form a circuit on the top surface of the metal substrate 110. Accordingly, a photo resist pattern corresponding to a desired circuit pattern is formed.
  • a fine circuit pattern is formed by carrying out half etching. Also, the lead units 150 and the die pad unit 140 are separated by the support units 170 through the half etching. Herein, “being separated” may be referred as “being shorted.” In a top view, a shape of the lead units forms a circuit pattern. At step S7, the top surfaces of the lead units, that is, the circuit pattern, are exposed by peeling off the photo resists 120.
  • insulating layers 180 are formed on predetermined parts of the exposed top surfaces of the lead units 150 and the exposed top surface of the support unit.
  • the insulating layers enhance physical strength of the lead frame and prevent molding from delaminating.
  • inner leads 190a and outer leads 190b are formed by plating the top and bottom surfaces of the lead units.
  • die pad metal units 195 are formed by plating the top surface of the die pad unit with metal.
  • gold (Au) may be plated thereon after nickel (Ni) is plated. Further, nickel (Ni), lead (Pb), and gold (Au) may be sequentially plated thereon. One of metals Ni, Pb, and Au may be replaced with silver (Ag).
  • An electroplating process may be generally carried out as the metal plating process. However, the electroplating process and an electroless plating process may be used together.
  • a bottom surface of the support unit 170 downwardly protrudes than a bottom surface of the outer lead 190b.
  • a swell structure is formed by forming the outer leads 190b inner than an adjacent support unit. Such a swell structure improves the stability of a soldering process because the swell structure enhances adhesive during the soldering process.
  • a solder boll is inserted into a space formed inside the insulating layer when a semiconductor package is attached on a PCB substrate.
  • the solder ball closely contacts the outer lead 190b and is fixed by the adjacent support unit. Accordingly, the solder ball may be further firmly adhered.
  • a semiconductor chip 20 is mounted after forming the inner leads 190a, the outer leads 190b, and the die pad metal units 195, and the semiconductor chip 20 is connected to the inner leads 190a and the die pad metal units 195 through a wire 10.
  • the semiconductor chip 20 is electrically connected to a PCB substrate where the leadframe is attached.
  • the semiconductor chip is electrically connected to a plating unit formed on the bottom surface of the lead unit through a plating unit formed on the top surface of the lead unit, which forms a circuit pattern.
  • a length of the semiconductor chip and the lead unit may be reduced due to the fine circuit pattern. Accordingly, a manufacturing cost thereof is reduced by reducing a length of wire.
  • a groove may be formed at the die pad unit where the semiconductor chip is mounted. Since the semiconductor chip is inserted in the groove, a size of the semiconductor package is reduced and durability thereof is enhanced.
  • the leadframe and the semiconductor chip are integrally packaged using encapsulant such as mold resin or epoxy mold compound (EMC).
  • FIG. 3 and FIG. 4 are flowcharts of a method for packaging a semiconductor chip using a leadframe in accordance with a second embodiment of the present invention.
  • a metal substrate 210 for circuit is prepared.
  • the metal substrate 210 may be exemplary made of Copper (Cu).
  • the metal substrate 210 may be made of conductive metal material such as copper alloy, iron (Fe), and iron alloy. Thickness of the metal substrate 210 is exemplary thinner than about 10mil where 1mil is equal to 1/1,000 inch. The thickness of the metal substrate 210 may be thinner than about 5mil.
  • Photo resists 220 are formed on top and bottom surfaces of the metal substrate 210.
  • the photo resists 220 may be formed as liquid photo resist (LPR) or dry film resist (DFR).
  • LPR liquid photo resist
  • DFR dry film resist
  • a photolithography process using photo mask is carried out to expose and develop the photo resists 220 formed on the top and bottom surfaces of the metal substrate 210.
  • the photo resists 220 may be formed only on the bottom surface of the metal substrate 210. However, the photo resists 220 may be formed on the both surfaces of the metal substrate 210 in order to protect elements of the top surface thereof.
  • support unit grooves 230, a die pad unit 240, and lead units 250 are formed by a half-etching process. As shown, the support unit grooves 230, the die pad unit 240, and the lead units 250 are not separated yet.
  • the metal substrate may be exemplary etched more than about 2/3 thickness of the metal substrate.
  • an insulator 260 such as RCC and PSR is coated on the support unit grooves.
  • support units 270 are formed by pressing and grinding the coated RCC or exposing and developing the coated PSR.
  • step S5 the both sides of the metal substrate 210 are etched by reducing the thickness of the metal substrate 210. As described above, a fine circuit pattern is formed by reducing the thickness of the metal substrate 210.
  • a photo resist 220 pattern is formed corresponding to a desired circuit pattern by coating photo resists 220 on the top and bottom surfaces (or only the top surface) of the metal substrate 210 and performing a photo lithography process (exposing and developing) using photo mask in order to form a circuit pattern on the top surface of the metal substrate 210.
  • a circuit pattern is formed by performing etching and peeling off the photo resists 220, and a groove is formed at the die pad unit at a predetermined depth.
  • the lead units 250 are also separated from the die pad unit 240 by the support unit 270 through the etching process.
  • “being separated” may be referred as “being shorted.”
  • a shape of the lead units forms a circuit pattern.
  • each one of the lead units 250 includes a horizontal part 250a and a vertical part 250b. Since the groove forms a step in the die pad unit 240, the die pad unit 240 includes a step upper part 240a and a step lower part 240b.
  • a semiconductor chip 220 is mounted in the groove of the die pad unit 240, that is, on the step lower part 240b. Accordingly, the size of the semiconductor package is reduced, and the durability is improved.
  • an insulating layer 280 is formed by coating exposed parts of the horizontal units 250a of the lead units 250, the die pad unit 240, and the support unit 270 with PSR.
  • the insulating layer 280 enhances the physical strength of the leadframe and prevents molding from delaminating.
  • a plating mask is formed by exposing and developing the insulating layer 280 through a lithography process.
  • inner leads 290a, outer leads 290b, and die pad metal units 295a, 295b, and 295c are formed by plating top and bottom surfaces of the lead units 250 and the die pad unit 240 through an electroless plating process.
  • the lead units 250 and the die pad unit 240 are separated by the etching, it is impossible to perform an electroplating process but the electroless plating process. Therefore, a rectifier is not required for plating due to the electroless plating. Since the electroless plating process is advantageous for forming a fine pattern planting due to its properties.
  • a planting layer structure is superior and a planting deviation is reduced.
  • gold (Au) is planted after nickel (Ni) is planted.
  • palladium (Pd) and gold (Au) are sequentially planted on a nickel (Ni) planting layer. Further, at least one of nickel (Ni), palladium (Pd), and gold (Au) may be replaced with silver (Ag).
  • FIG. 5 shows various structures of the inner leads 290a and the die pad metal units 295a and 295b.
  • a structure (a) shows the inner lead 290a surrounding a side of one end of the horizontal part 250a of the lead unit 250.
  • the structure (a) also shows the die pad metal part 295a formed on the step upper part 240a of the die pad unit to surround one end or both ends (not shown) of the die pad unit 240.
  • the one end of the horizontal part 250a of the lead unit 250 is one end toward the die pad unit 240.
  • the one end of the die pad unit 240 is one end toward the lead unit 250.
  • the die pad metal unit 295a is formed to surround the both ends of the die pad unit 240.
  • Such a structure may be formed by exposing one end of the horizontal part 250a and one end or both ends of the die pad unit 240 in the step S9 and planting the exposed sides through electroless planting in the step S10.
  • the reliability of the leadframe can be improved.
  • Copper is generally used as a material of the metal substrate 210.
  • Such a copper substrate is thermally expanded by environmental variations such as temperature and humidity.
  • Such a thermal expansion of the metal substrate 210 electrically connects the lead unit 250 to the die pad unit 240 or the lead unit 250 to another lead unit, thereby causing defect. Therefore, such a defect may be prevented by fixing the sides of the copper substrate with a plating layer.
  • a structure (b) shows that the inner lead 290a and the die pad metal unit 295a are formed with a predetermined gap from the side.
  • Such a structure may be formed by controlling a pattern structure of a plating mask in the step S9 and performing electroless plating in the step S10.
  • a structure (c) shows that the die pad metal unit 295b is formed on the step lower part 240b of the die pad unit 240.
  • a structure (d) shows that the die pad metal unit 295a is connected to the die pad metal unit 295b by forming the die pad metal unit 295d on the step of the die pad unit 240.
  • Such structures may be formed by controlling a pattern structure of a plating mask in the step S9 and performing electroless plating in the step S10.
  • the thermal conduction may be improved by forming the metal units 295a, 295b, and 295d at the die pad unit 240 as shown above.
  • a semiconductor chip 20 is mounted and the semiconductor chip 220 is connected to the inner leads 290a and the die pad metal units 295a through wires 10 at step S11.
  • the semiconductor chip 20 is electrically connected to a PCB substrate where the leadframe is attached.
  • the semiconductor chip 20 is electrically connected to the outer lead 290b, which is a plating part formed on the bottom surface of the vertical part 250b of the lead unit 250, through the inner lead 290a which is a plating part formed on the top surface of the horizontal part 250a of the lead unit 250.
  • input/output signals may be transmitted and received through the fine circuit pattern in accordance with an embodiment of the present invention.
  • a length of the semiconductor chip and the lead unit is reduced by the fine circuit patter, and a length of the wire is also reduced. Accordingly, a manufacturing cost thereof is reduced.
  • the leadframe and the semiconductor chip are integrally packaged using encapsulant such as mold resin or epoxy mold compound 30 (EMC).
  • encapsulant such as mold resin or epoxy mold compound 30 (EMC).
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing a leadframe in accordance with a third embodiment of the present invention.
  • a metal substrate 310 is prepared at step S1.
  • the metal substrate 310 may be made of copper (Cu).
  • conductive metal material such as copper alloy, iron (Fe), and iron alloy may be used.
  • photo resists 320 are formed on top and bottom surfaces of the metal substrate 310.
  • the photo resists 320 may be formed as liquid photo resist (LPR) or dray film resist (DFR).
  • LPR liquid photo resist
  • DFR dray film resist
  • a photolithography process using a photo mask is carried out to expose and develop the photo resists 320 on the top and bottom surface of the metal substrate 310.
  • etching masks are formed through exposing and developing in order to form grooves for a circuit pattern and a die pad unit.
  • the metal substrate 310 is etched to be routable and the photo resists, which are etching masks, are peeled off.
  • “routable” means a property that connects an inner lead and an outer lead in order to electrically connect a semiconductor chip mounted in the die pad unit to a PCB substrate where a semiconductor package is mounted.
  • plating resists are formed for forming inner leads 350 and an outer lead 360.
  • solder resists SR
  • the solder resists support the leadframe during etching which will be performed later.
  • the solder resists also support a top surface of a completely manufactured leadframe as an upper support unit. Accordingly, the solder resists are referred as upper support units 330a, hereinafter.
  • Dry film resists 340 are formed on the bottom surface of the metal substrate 310, and a predetermined part to plat the outer lead 360 in the bottom surface of the metal substrate 310 is exposed.
  • a predetermined part to plat the outer lead 360 in the bottom surface of the metal substrate 310 is exposed.
  • parts to plat metal layers 370 and 380 in the top and bottom surfaces of the die pattern are exposed as well as the parts for the inner lead 350 and the outer lead 360.
  • the inner leads 350, the outer lead 360, the die pad upper metal layer 370, and the die pad lower metal layer 380 are formed by selectively etching the top and bottom surfaces of the metal substrate 310.
  • the inner leads 350 formed on the step upper part of the die pad unit may be separated from the die pad upper metal part 370 formed on the step lower part in order to reduce a plating area.
  • thermal conduction is improved by forming the die pad upper and lower metal layers 370 and 380 on top and bottom surfaces of the die pad unit.
  • the bottom DFR is peeled off.
  • the lead unit 390 and the die pad unit 400 are formed to be separated by etching a lower part of the metal substrate.
  • a space separating the lead unit 390 from the die pad unit 400 is filled by the upper support unit 330a. Accordingly, the upper support unit 330b maintains a shape of the overall leadframe although the lower part of the metal substrate is etched.
  • the thickness of the package may be reduced by etching the top surface of the metal substrate 310 first and etching the bottom surface of the metal pattern 310 later as described.
  • the lead unit 390 has a horizontal part and a vertical part by etching the lower part of the metal substrate.
  • the horizontal part has a shape of the above described circuit pattern in a top view of the leadframe.
  • etching resists are formed as dry film resists (DFR), and etching is performed using the DFRs as the etching mask.
  • DFR dry film resists
  • a predetermined part of the outer lead 360 may be etched in order to form insulating material extending from a support unit 330b at the same time of forming the outer lead 360 on the bottom surface of the vertical part of the lead unit 390.
  • a lower support unit 330b is formed by printing, exposing, and developing a solder resist on the bottom surface of the metal substrate 310 and hardening the result thereof.
  • the top and bottom surfaces of the leadframe according to the present invention are surrounded by the lower support unit 330b and the upper support unit 330a. Accordingly, the durability thereof may be improved and it prevents the leadframe from tilting.
  • the lower support unit 330b may be printed to be extended to a bottom surface of the vertical part of the lead unit 390 exposed through etching when the predetermined part of the outer lead 360 is etched as described in the step S6.
  • FIG. 7 shows a structure that the lower support unit 330b extending to the bottom surface of the vertical part of the lead unit 390.
  • the structure of FIG. 7 prevents an empty space from being formed between the lower support 210 and the vertical part of the lead unit. Accordingly, a defective proportion thereof can be reduced.
  • a semiconductor chip 20 is mounted, and wires 10 are formed to electrically connect the semiconductor chip 20 and the inner lead 350. Since the lead unit 390 is routable, an input/output distance of a circuit is shortened. Such a structure allows a flip chip structure and shortens the length of the wires 10, thereby reducing a manufacturing cost.
  • a semiconductor chip package is formed by packing the semiconductor chip and the leadframe using encapsulant such as mold resin or epoxy mold compound (EMC).
  • the find circuit pattern according to the present invention shortens a wire and allows flip-chip bonding due to routability which is a property connecting an inner lead and an outer lead for electrically connecting a semiconductor chip mounted in a die pad to a PCB substrate where a semiconductor package is mounted.
  • the swell structure of the leadframe according to the present invention improves adhesive during a soldering process.
  • the physical strength thereof is enhanced by improving the support force of insulator.
  • the described structure of the leadframe according to the present invention prevents the lead unit made of copper from being electrically connected to another element due to environmental variations. Further, the thickness of the semiconductor package is reduced by etching the both sides of the leadframe. Moreover, the insulating layer formed between the lead unit and molding material prevents warpage and improves durability thereof. Furthermore, a rectifier is not required because of using an electroless plating process instead of an electroplating process. Due to the electroless plating process, it is possible to form a fine plating pattern with a small plating deviation and a superior structure thereof.
  • the support units of the leadframe according to the present invention surround the upper and lower parts of the lead unit. Accordingly, the leadframe according to the present invention has excellent durability. Since the top and bottom surfaces of the die pad unit are entirely plated, thermal conduction is improved.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

La présente invention porte sur une grille de connexion et sur son procédé de fabrication. La grille de connexion comprend une unité de connexion comportant des parties verticales et horizontales, une unité de zone de puces séparée de l'unité de connexion par une unité de support formée en un matériau isolant, une connexion interne formée au voisinage de l'unité de zone de puces et sur la partie horizontale de l'unité de connexion, et une connexion externe formée sur une surface inférieure de la partie verticale de l'unité de connexion. Cette structure de la grille de connexion raccourcit une longueur de fil, permet un soudage par puces à protubérances, et améliore une adhérence de soudure. La structure de la grille de connexion renforce la résistance physique de celle-ci par renforcement d'une force de support d'un isolateur. De plus, la grille de connexion comprend un motif de placage fin ayant un faible écart de placage et une excellente structure, et a une excellente durée de vie et une conduction thermique améliorée par des surfaces entièrement placées de la zone de puces.
PCT/KR2010/007730 2009-11-04 2010-11-04 Grille de connexion et son procédé de fabrication WO2011055984A2 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2009-0106142 2009-11-04
KR1020090106142A KR101095527B1 (ko) 2009-11-04 2009-11-04 리드 프레임 및 그 제조 방법
KR1020090108386A KR101168890B1 (ko) 2009-11-11 2009-11-11 리드 프레임 및 그 제조 방법
KR10-2009-0108386 2009-11-11
KR10-2009-0114287 2009-11-25
KR1020090114287A KR101168412B1 (ko) 2009-11-25 2009-11-25 리드 프레임 및 그 제조 방법

Publications (2)

Publication Number Publication Date
WO2011055984A2 true WO2011055984A2 (fr) 2011-05-12
WO2011055984A3 WO2011055984A3 (fr) 2011-09-22

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WO (1) WO2011055984A2 (fr)

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CN103715100A (zh) * 2012-10-07 2014-04-09 英特赛尔美国有限公司 引线框架上的焊料阻流塞
DE102014114520A1 (de) * 2014-10-07 2016-04-07 Infineon Technologies Austria Ag Ein elektronisches Modul mit mehreren Einkapselungsschichten und ein Verfahren zu dessen Herstellung
TWI669801B (zh) * 2018-09-04 2019-08-21 頎邦科技股份有限公司 撓性基板

Families Citing this family (1)

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TWI645523B (zh) * 2017-07-14 2018-12-21 矽品精密工業股份有限公司 封裝結構及其製法

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JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
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KR20060052560A (ko) * 2004-11-12 2006-05-19 페어차일드코리아반도체 주식회사 향상된 신뢰성 및 높은 열방출능력을 갖는 몰디드 리드리스패키지 및 소잉형 몰디드 리드리스 패키지 및 그 제조방법
KR20070025566A (ko) * 2005-09-02 2007-03-08 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지

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JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
JP2001094026A (ja) * 1999-09-22 2001-04-06 Toshiba Corp リードフレーム及びその製造方法
KR20060052560A (ko) * 2004-11-12 2006-05-19 페어차일드코리아반도체 주식회사 향상된 신뢰성 및 높은 열방출능력을 갖는 몰디드 리드리스패키지 및 소잉형 몰디드 리드리스 패키지 및 그 제조방법
KR20070025566A (ko) * 2005-09-02 2007-03-08 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715100A (zh) * 2012-10-07 2014-04-09 英特赛尔美国有限公司 引线框架上的焊料阻流塞
DE102014114520A1 (de) * 2014-10-07 2016-04-07 Infineon Technologies Austria Ag Ein elektronisches Modul mit mehreren Einkapselungsschichten und ein Verfahren zu dessen Herstellung
US10418313B2 (en) 2014-10-07 2019-09-17 Infineon Technologies Austria Ag Electronic module comprising a plurality of encapsulation layers and a method for producing it
DE102014114520B4 (de) * 2014-10-07 2020-03-05 Infineon Technologies Austria Ag Ein elektronisches Modul mit mehreren Einkapselungsschichten und ein Verfahren zu dessen Herstellung
TWI669801B (zh) * 2018-09-04 2019-08-21 頎邦科技股份有限公司 撓性基板

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TW201126677A (en) 2011-08-01
WO2011055984A3 (fr) 2011-09-22
TWI430418B (zh) 2014-03-11

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