WO2017135624A1 - Boîtier de capteur et son procédé de préparation - Google Patents

Boîtier de capteur et son procédé de préparation Download PDF

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Publication number
WO2017135624A1
WO2017135624A1 PCT/KR2017/000802 KR2017000802W WO2017135624A1 WO 2017135624 A1 WO2017135624 A1 WO 2017135624A1 KR 2017000802 W KR2017000802 W KR 2017000802W WO 2017135624 A1 WO2017135624 A1 WO 2017135624A1
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Prior art keywords
wiring
substrate
semiconductor chip
insulating layer
pad
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PCT/KR2017/000802
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English (en)
Korean (ko)
Inventor
이응주
임시우
오동훈
Original Assignee
주식회사 네패스
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Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to CN201790000502.1U priority Critical patent/CN208767298U/zh
Publication of WO2017135624A1 publication Critical patent/WO2017135624A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts

Definitions

  • the present invention relates to a sensor package and a method of manufacturing the same, and more particularly, to reduce the thickness of the sensor package and improve the sensitivity of the sensor, the sensor package is provided with a conductive passage for electrically connecting the upper and lower parts of the sensor package; It relates to a production method thereof.
  • the size of the semiconductor chip has also been continuously reduced.
  • the size of the semiconductor chip is greatly reduced, so that it is necessary to increase the package size for the electrical connection when forming the semiconductor package.
  • One of the semiconductor package technologies proposed in this development process is a fan-out package.
  • a semiconductor chip is attached to an PCB substrate or a lead frame through an adhesive, and the semiconductor chip and the metal frame on the side of the PCB substrate or the lead frame are electrically connected through wire bonding. And a package structure in which the semiconductor chip and the wire are protected through molding.
  • Korean Patent Publication No. 10-2015-0090705 discloses a sensor package in which a sensing unit is exposed on a surface of a package and a method of manufacturing the same.
  • Embodiments of the present invention can be manufactured in a thin, to provide a sensor package with improved sensitivity of the sensor.
  • embodiments of the present invention is to provide a method of manufacturing a sensor package that can be stacked wiring layer without inserting a separate metal pad or the like between the through wiring through the substrate and the wiring layer.
  • a sensor package includes a semiconductor chip including a sensor pattern exposed to the outside, a substrate including an accommodating part in which the semiconductor chip is accommodated, an encapsulant molding the semiconductor chip and the substrate to be integrated;
  • the through wiring penetrating the substrate in the vertical direction, the semiconductor chip and the through wiring are electrically connected to each other, the wiring portion for exposing the sensor pattern of the semiconductor chip and the other side of the through wiring and electrically connected An external connection electrically connectable thereto.
  • the semiconductor chip, the substrate and the encapsulant may be provided on the same plane, and the wiring part may be stacked on the semiconductor chip, the substrate and the encapsulant.
  • the wiring portion may include a first insulating layer exposing the signal pad and the through wiring of the semiconductor chip and the first insulating layer to connect the signal pad and the through wiring.
  • the semiconductor device may include a wiring layer electrically connected to each other, and a second insulating layer provided on the first insulating layer and the wiring layer to cover the wiring layer and to expose the sensor pattern of the semiconductor chip.
  • the first insulating layer includes an opening that exposes the signal pad and the through wiring, respectively, and the wiring layer fills the opening of the first insulating layer to fill the signal pad and It may be connected to the through wiring.
  • the substrate may have a via hole penetrating in the vertical direction, and the through wiring may be formed of a conductive material filled in the via hole.
  • the through wiring may be provided with a conductive paste.
  • one side may be attached to the through wiring, the other side is attached to the external connection portion, and may further include a pad portion made of a conductive material.
  • an end portion of the through wire to which the pad part is attached may be provided to protrude from the substrate and to extend outward.
  • a metal layer may be interposed between the substrate and the end of the through wiring.
  • the substrate has a via hole penetrating in the vertical direction, the through wiring is provided to surround the inner circumferential surface of the via hole, and the through hole formed in the through wire is filled with a through member.
  • the through wiring is provided to surround the inner circumferential surface of the via hole, and the through hole formed in the through wire is filled with a through member. Can be.
  • the through member may be provided with a non-conductive resin.
  • a method of manufacturing a sensor package including: providing a substrate in which a semiconductor chip is accommodated and a via hole penetrating in an up and down direction from the outside of the accommodation part, along a vertical direction of the via hole; Forming a through wiring, accommodating a semiconductor chip including a signal pad and a sensor pattern in the accommodating portion, laminating an insulating layer on the semiconductor chip and the substrate, wherein the insulating layer is the through wiring, and Stacking the signal pad and the sensor pattern of the semiconductor chip to expose the semiconductor chip; and forming a wiring layer on the insulating layer to electrically connect the signal pad and the through wiring.
  • the method of forming the through wiring may be to surround the inner peripheral surface of the via hole using a deposition or plating process.
  • the through wiring is formed by being deposited or plated on both surfaces of the substrate, and the through wiring provided on both surfaces of the substrate may be connected through an inner circumferential surface of the via hole.
  • the via hole may be filled with the through wiring.
  • a pad part formed of a conductive material may be stacked on a through wire provided on one surface of the substrate.
  • the through member may be filled in the hollow portion of the through wire, and the through wire provided on one surface of the substrate and the pad part provided with the conductive material may be stacked on the through member. have.
  • the method may further include an etching process of removing the pad part and the through wiring.
  • it may further include a step of planarizing the surface opposite to the surface on which the pad portion exists by the patterning.
  • the substrate, the through wiring, and the through member may be provided on the same plane by the planarization process.
  • the sensor package and the method of manufacturing the same according to the embodiment of the present invention can reduce the thickness of the insulating layer provided between the semiconductor chip and the wiring layer, thereby making it possible to manufacture a thin package, the active surface of the semiconductor chip and the overall buildup Sensing sensitivity can be increased by minimizing the thickness between layers.
  • FIG. 1 is a cross-sectional view of a sensor package according to an embodiment of the present invention.
  • FIG. 2 is a plan view of the sensor package of FIG. 1 taken along line AA ′.
  • FIG. 2 is a plan view of the sensor package of FIG. 1 taken along line AA ′.
  • 3 to 16 are cross-sectional views illustrating a manufacturing process of a sensor package according to an embodiment of the present invention.
  • 17 is a cross-sectional view of a sensor package according to an embodiment of the present invention.
  • FIG. 18 is a cross-sectional view of a package-on-package in which the sensor package of FIG. 1 is stacked.
  • a sensor package includes a semiconductor chip including a sensor pattern exposed to the outside, a substrate including an accommodating part in which the semiconductor chip is accommodated, an encapsulant molding the semiconductor chip and the substrate to be integrated;
  • the through wiring penetrating the substrate in the vertical direction, the semiconductor chip and the through wiring are electrically connected to each other, the wiring portion for exposing the sensor pattern of the semiconductor chip and the other side of the through wiring and electrically connected to the outside An external connection electrically connectable thereto.
  • FIG. 1 is a cross-sectional view of a sensor package according to an embodiment of the present invention.
  • FIG. 2 is a plan view of the sensor package of FIG. 1 taken along line AA ′.
  • FIG. A sensor package 100 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.
  • the sensor package 100 may include a semiconductor chip 110 including a sensor pattern 114 exposed to the outside, and a substrate including a receiving part 121 in which the semiconductor chip 110 is accommodated. (120), the encapsulant 140 molding to integrate the semiconductor chip 110 and the substrate 120, a through wiring 123 penetrating the substrate 120 in the vertical direction, the semiconductor chip 110 And electrically connect the through wires 123 to each other, the wire part 130 exposing the sensor pattern 114 of the semiconductor chip 110, and the other side of the through wires 123. And an external connection unit 150 that is electrically connectable to the outside.
  • the substrate 120 may be provided as an insulating substrate.
  • the insulating substrate may include an insulating material, and may include, for example, silicon, glass, ceramic, plastic, or polymer.
  • the substrate 120 may be provided in a flat plate shape and may be provided in various shapes such as a circle or a polygon.
  • the substrate 120 may include an accommodating part 121 accommodating the semiconductor chip 110.
  • the accommodating part 121 may be provided to penetrate the substrate 120, and may be positioned at a central portion of the substrate 120.
  • the accommodating part 121 may be provided wider than the width of the semiconductor chip 110 to accommodate the semiconductor chip 110.
  • the semiconductor chip 110 and the receiving portion 121 may be filled with an encapsulant 140 to be described later.
  • the receiving part 121 may be provided as a groove in which one surface of the substrate 120 is not opened, as shown in the drawing.
  • the semiconductor chip 110 may be formed to have the same widthwise shape as that of the semiconductor chip 110 so as to press-fit the semiconductor chip 110.
  • the semiconductor chip 110 may be various types of sensor chips capable of sensing an external stimulus through the sensor pattern 111 exposed to the outside.
  • the semiconductor chip 110 may use an image sensor chip, a fingerprint sensor chip, a thermal sensor chip, or a humidity sensor chip.
  • the semiconductor chip 110 may be a sensor chip for fingerprint recognition, and the sensor package 100 of the present invention including the semiconductor chip 110 may be used in a sensor device, and in particular, may be used in a fingerprint sensor. Can be.
  • One surface of the semiconductor chip 110 may be an active surface 111 including an active region in which a circuit is formed.
  • the back surface of the semiconductor chip 110 may be an inactive surface 112.
  • the active surface 111 of the semiconductor chip 110 may be provided with a plurality of signal pads 113 for exchanging signals with the outside, and the signal pads 113 may be formed of a conductive material layer such as aluminum (Al). It can be formed as.
  • the signal pad 113 may be integrally formed with the semiconductor chip 110.
  • one semiconductor chip 110 is illustrated in FIG. 1, two or more semiconductor chips may be stacked.
  • the semiconductor chips stacked at this time may be heterogeneous products.
  • one semiconductor chip may be a sensor chip, and the other semiconductor chip may be a memory chip or a logic chip.
  • the sensor package in which two or more semiconductor chips are stacked may be a system on chip (SOC) or a system in package (SIP).
  • the plurality of semiconductor chips may be disposed adjacent to or in contact with each other in the width direction.
  • the sensor package 100 In order for the sensor package 100 to be mounted on a main board (not shown) or to be electrically connected to another chip or a package, an electrical connection part electrically connected between the semiconductor chip 110 and the main board is required. On the other hand, in order to mount the sensor package 100 in the main board connection area of the area larger than the interval of the signal pad 113 of the semiconductor chip 110, a fan-out package in which the circuit is extended to the outside of the semiconductor chip 110 Forms can be provided.
  • the main substrate includes a printed circuit board or a lead flame on which a circuit is printed.
  • the printed circuit board may include a thin film, glass, tape, or the like.
  • Sensor package 100 for the fan-out package form is provided on the outside of the signal pad 113 of the semiconductor chip 110 includes a through wire 123 for transmitting an electrical signal in the vertical direction. can do.
  • One side of the through wire 123 may be electrically connected to the semiconductor chip 110, the other side may be electrically connected to the external connection unit 150, and the external connection unit 150 may be electrically connected to the main substrate or another chip or package. have.
  • the through wire 123 may be disposed in the vertical direction through the via hole 122 provided in the substrate 120 to transmit a data signal or a power signal between the semiconductor chip 110 and the main substrate.
  • the via hole 122 may be formed to penetrate the substrate 120, and a plurality of via holes 122 may be provided along an outer portion of the receiving portion 121 of the substrate 120. Referring to FIG. 2, it can be seen that the through wires 123 are provided in a row along the outer side of the accommodating part 121. Alternatively, two or more rows of through wires 123 may be provided, or through wires 123 may be provided only on one side of the accommodating part 121.
  • the through wire 123 may be a conductive material filled in the via hole 122.
  • the through wire 123 may be provided in a cylindrical shape.
  • the through wiring 123 may be formed in the form of solder balls or the like, penetrating the via hole 122, or may be solder resist ink filled in the via hole 122.
  • the method of forming the through wiring 123 may include electroless plating, electrolytic plating, sputtering, or printing.
  • One side (the upper side in FIG. 1) of the through wire 123 may be provided on the same plane as the substrate 120, and the other side (the lower side in FIG. 1) may be provided to protrude from the substrate 120. Can be.
  • the other side (or lower side) protruding from the substrate 120 may extend outward and be provided in the form of a flange, and the metal layer 120a may be interposed between the substrate 120 and the flange portion extending outwardly.
  • An example of the metal layer 120a may include a copper foil.
  • the through wire 123 may be electrically connected to the wiring layer 132 of the wiring unit 130, and the other side thereof may be electrically connected to the external connection unit 150.
  • the pad part 125 may be interposed between the through wire 123 and the external connection part 150.
  • the pad part 125 may be made of a conductive material to electrically connect the through wire 123 and the external connection part 150, and may allow the external connection part 150 to be firmly adhered to the through wire 123.
  • the method of forming the pad portion 125 includes electroless plating, electrolytic plating, sputtering, printing, or the like.
  • the wiring unit 130 may be provided to electrically connect the signal pad 113 of the semiconductor chip 110 and one side of the through wiring 123.
  • the wiring unit 130 may include a first insulating layer 131, a second insulating layer 133, and a wiring layer 132.
  • the first insulating layer 131 and the second insulating layer 133 are made of an insulating material to insulate the wiring layer 132.
  • the first insulating layer 131 may be provided to be stacked on the active surface 111 of the semiconductor chip 110, the encapsulant 140, and one surface of the substrate 120. In addition, the first insulating layer 131 exposes the signal pad 113 and the through wiring 123 of the semiconductor chip 110 so that the wiring layer 132 stacked on the first insulating layer 131 is the signal pad 113. And through wires 123. Meanwhile, when the encapsulant 140 is provided to cover one surface of the semiconductor chip 110 and / or the substrate 120, the first insulating layer 131 may be formed on the semiconductor chip 110 and / or the substrate 120. It may not be laminated to.
  • the wiring layer 132 includes a conductive material and may be stacked on the first insulating layer 131 through a rearrangement process.
  • the wiring layer 132 may refine the input / output terminals of the semiconductor chip 110 by forming a redistribution pattern, increase the number of input / output terminals, and enable a fanout structure.
  • the conductive material may comprise a metal and may include, for example, copper, a copper alloy, aluminum or an aluminum alloy.
  • the wiring layer 132 may be provided as a prefabricated structure, and the structure is bonded to the semiconductor chip 110, the encapsulant 140, and the substrate 120 by pressing, bonding, or reflowing. Include.
  • the second insulating layer 133 is stacked on the first insulating layer 131 and the wiring layer 132 so as to insulate the wiring layer 132 from the outside.
  • the second insulating layer 133 seals the wiring layer 132
  • the second insulating layer 133 may be provided to expose a portion of the wiring layer 132.
  • 132 may be electrically connected to the outside (such as a main substrate, a semiconductor chip, or a package).
  • one end of the through wire 123 may not protrude on the substrate 120.
  • the through wiring 123 and the wiring layer 132 may be directly connected and electrically connected to each other.
  • the connection means not only physically contacting, but also bonding between a conductive adhesive layer (eg, a seed layer) and the like.
  • the sensitivity of the sensor may be improved by minimizing the thickness between the active surface 111 of the semiconductor chip 110 and the entire buildup layer.
  • the semiconductor chip and the metal frame of the side are connected by wire bonding, so that the thickness of the sensor package is increased by molding for protecting the wire, and the distance between the upper surface of the sensor package and the sensor pattern of the semiconductor chip. As the length becomes longer, there is a problem that the sensitivity of the sensor is lowered.
  • the thickness of the sensor package 100 becomes thick, which is against the purpose of pursuing a light and simple product.
  • the selection of the insulating material is restricted, and the fine pitch patterning also has a limit.
  • the sensor package 100 does not need a wire for connecting the signal pad 113 of the semiconductor chip 110 with the metal frame of the PCB substrate or the side of the lead frame.
  • the sensor package 100 since the thickness of the first insulating layer 131 can be reduced, the sensor package 100 has high utilization in the sensor device.
  • the external connection unit 150 may be connected to the other side of the through wire 123 to be mounted on an external substrate (not shown) or electrically connected to another semiconductor chip or package.
  • the external connection part 150 may be provided with solder balls, solder bumps, conductive balls, or the like.
  • the conductive ball may be made of copper (Cu), gold (Au), nickel (Ni), aluminum (Al), silver (Ag), or an alloy containing at least one of these metals.
  • the encapsulant 140 may be integrated by sealing the substrate 120 and the semiconductor chip 110.
  • the encapsulant 140 may include an insulator and may include, for example, an epoxy mold compound (EMC) or an encapsulant.
  • EMC epoxy mold compound
  • the encapsulant 140 may fill between the semiconductor chip 110 and the substrate 120, and may be provided to surround the outer surface of the substrate 120 to protect it from the outside.
  • the encapsulant 140 may be cured in a high temperature environment after being injected in a fluid state. For example, it may include a step of heating and pressurizing the encapsulant 140 at the same time. In this case, a gas may be removed from the encapsulant 140 by adding a vacuum process.
  • the encapsulant 140 may be provided by a method such as applied or printed, the molding method of the encapsulant 140 may use a variety of techniques commonly used in the art.
  • One surface of the encapsulant 140 may be provided to expose the signal pad of the semiconductor chip 110 and one end of the through wire 123.
  • one surface of the encapsulant 140, the active surface 111 of the semiconductor chip 110, and one surface of the substrate 120 are provided on the same plane.
  • the process of planarizing the encapsulant 140 includes grinding, sanding, etching, or the like.
  • the other surface of the encapsulant 140 may cover the inactive surface 112 of the semiconductor chip 110 to seal and seal the semiconductor chip 110 with airtightness.
  • the non-active surface of the semiconductor chip 110 may be exposed depending on the required characteristics of the sensor package 100.
  • one surface of the encapsulant 140 and the non-active surface 112 of the semiconductor chip 110 are provided on the same plane, thereby reducing the thickness of the sensor package 100 and dissipating heat of the semiconductor chip 110. May be advantageous.
  • 3 to 16 are cross-sectional views illustrating a manufacturing process of a sensor package according to an embodiment of the present invention.
  • a method of manufacturing a sensor package may include an accommodating part 121 in which the semiconductor chip 110 is accommodated and an outer side of the accommodating part 121 in a vertical direction. Providing a substrate 120 through which the via holes 122 are formed, forming through wires 123 along the vertical direction of the via holes 122, and forming a signal pad 113 in the accommodating part 121. And accommodating a semiconductor chip 110 including a sensor pattern 114, wherein an insulating layer 131 is stacked on the semiconductor chip 110 and the substrate 120, wherein the insulating layer 131 is formed on the semiconductor chip 110.
  • the substrate 120 may include an insulating material.
  • it may include silicon, glass, ceramic, plastic, polymer, or the like.
  • the substrate 120 may be provided in a flat plate shape, but may also be provided in a circular or polygonal shape.
  • the accommodating part 121 forms a space for accommodating the semiconductor chip 110 and may be provided in a shape corresponding to the shape of the semiconductor chip 110.
  • the width direction of the accommodating part 121 may be provided as a quadrangular shape.
  • the accommodating part 121 may be provided to penetrate the substrate 120. Or it may be provided with a groove that one side is not open.
  • the metal layer 120a may be stacked on both surfaces of the substrate 120.
  • the metal layer 120a may be provided with a copper foil.
  • the via hole 122 may be provided to penetrate the substrate 120 in an up and down direction, and may be provided at an outer side of the receiving portion 121.
  • the via hole 122 may have a circular cross section but may include a different shape.
  • the via hole 122 may be provided in plural along the circumference of the accommodating part 121, and unlike FIG. 4, two or more via holes 122 may penetrate through an outer direction of the accommodating part 121.
  • the process of forming the receiving part 121 of FIG. 3 and the process of forming the via hole 122 of FIG. 4 may be performed at the same time, which may be preceded by one.
  • the via hole 122 may be formed earlier than the accommodating part 121.
  • the process of forming the accommodating part 121 and the via hole 122 may be performed using a routing process, a mold cutting process, an etching process, a drilling process, or a laser ablation process.
  • the through wire 123 may be made of a conductive material and may include a metal. For example copper, copper alloys, aluminum, or aluminum alloys.
  • the through wire 123 may be deposited or filled in the via hole 122 by a process such as electroless plating, electrolytic plating, sputtering, or printing. For example, it may be a metal coating layer provided to surround the inner surface of the via hole 122, and a through hole may be formed therein.
  • the conductive paste or solder resist ink filled in the via hole 122 may be used.
  • FIG 5 illustrates that both sides of the through wire 123 are formed to cover both surfaces of the substrate 120. This is because the through wire 123 may be stacked on the exposed surface of the substrate 120 when using a process such as plating or sputtering.
  • FIG. 6 illustrates a process of forming pads 125 (125a and 125b) on both sides of the through wiring 123.
  • the pad part 125 may include a conductive material, for example, may include a metal.
  • the pad part 125 may be provided to improve electrical contact between the through wire 123 and the external connection part 150.
  • the pad part 125 may improve contact angle or wettability.
  • the pad part 125 may be stacked on the through wire 123 using a process such as deposition, electroless plating, electroplating, or printing.
  • the pad part 125 may be stacked on all of the through wires 123 stacked on both surfaces of the substrate 120 as illustrated in FIG. 5, and may be stacked on any one surface of both surfaces of the substrate 120. Only the through wires 123 may be stacked. On the other hand, the process of forming the pad portion 125 is optional (optional), it may be omitted in some cases.
  • FIG. 7 illustrates a process of removing a portion of the through line 123 and the pad part 125a.
  • the through wires 123 and the metal layer 120a that have covered only the pad part 125a and the upper surface of the substrate 120 may be removed, leaving only the through member 124 on the upper surface of the substrate 120. have.
  • the through wire 123 and the metal layer 120a which cover the pad portion 125b and the upper surface of the substrate 120 may be removed while leaving only a predetermined range on the lower surface of the substrate 120.
  • a dry film (not shown) may be attached and patterned only on a portion of the lower surface of the substrate 120 to leave the pad part 125b, and then subjected to a pattern etching process.
  • the pad part 125b, the through wiring 123, and the metal layer 120a of the portion where the dry film is not attached may be removed.
  • the planarization process may use grinding, sanding, etching, or the like.
  • the upper surface of the substrate 120 and the through wiring 123 may form the same plane.
  • the planarization process may be performed. Can be removed.
  • the external connection part 150 may be attached to the pad part 125 remaining on the bottom surface of the substrate 120 to be electrically connected to the through wire 123.
  • the external connection unit 150 may be connected to the through wire 123 to be mounted on an external substrate (not shown) or electrically connected to another semiconductor chip or package.
  • the external connection part 150 may be provided with solder balls, solder bumps, conductive balls, or the like.
  • the conductive ball may be made of copper (Cu), gold (Au), nickel (Ni), aluminum (Al), silver (Ag), or an alloy containing at least one of these metals.
  • the first adhesive part 161 may be stacked on an upper surface of the first carrier 160 to fix the substrate 120 and the semiconductor chip 110 to each other.
  • the first carrier 160 may include silicon, glass, ceramic, plastic, polymer, or the like.
  • the first adhesive part 161 may be a liquid adhesive or an adhesive tape.
  • the substrate 120 may have a planarized surface (the upper surface of the substrate 120 in FIG. 9) attached to the first carrier 160 so that the external connection portion 150 may be positioned upward.
  • the semiconductor chip 110 may be inserted into the accommodating part 121 of the substrate 120 such that an active surface 111 may be attached onto the first carrier 160.
  • the active surface 111 on which the signal pad 113 and the sensor pattern 114 are formed is attached to the first adhesive part 161, and the inactive surface 112 is exposed upward.
  • the semiconductor chip 110 may be positioned and fixed to be spaced apart from an inner surface of the receiving portion 121 of the substrate 120. That is, the planar area of the accommodating part 121 may be larger than the planar area of the semiconductor chip 110. Alternatively, the side surface of the semiconductor chip 110 and the inner surface of the receiving portion 121 of the substrate 120 may be positioned to contact each other. For example, the planar area of the accommodating part 121 may be substantially the same as the planar area of the semiconductor chip 110.
  • the thickness of the substrate 120 and the semiconductor chip 110 is the same and attached to the first carrier 160, one surface of the substrate 120 and the inactive surface of the semiconductor chip 110 are illustrated. 112 is shown to have the same height. Alternatively, the height of the semiconductor chip 110 may be smaller than the height of the substrate 120. In this case, the upper surface of the semiconductor chip 110 may have a step with respect to the upper surface of the substrate 120.
  • the encapsulant 140 may be integrated by sealing the substrate 120 and the semiconductor chip 110.
  • the encapsulant 140 may include an insulator, and may include, for example, an epoxy mold compound (EMC) or an encapsulant.
  • EMC epoxy mold compound
  • the encapsulant 140 may fill between the semiconductor chip 110 and the substrate 120, and may surround the outer side surface of the substrate 120 to protect it from the outside. In addition, an upper surface of the encapsulant 140 may be higher than an upper surface of the substrate 120 and the inactive surface 112 of the semiconductor chip 110 to expose an end portion of the external connection portion 150. .
  • the encapsulant 140 may be formed using a printing method or a compression molding method.
  • An example of a method of molding the encapsulant 140 may be a method of injecting a liquid encapsulant 140 into a mold and curing the resin through a thermal process.
  • the liquid encapsulant 140 may be injected between the upper mold and the lower mold to fill the gap between the semiconductor chip 110 and the substrate 120.
  • a mold for molding the encapsulant 140 is omitted.
  • the package intermediate product integrated with the encapsulant 140 may be fixed to the second carrier 170 with the external connection portion 150 facing downward.
  • a second adhesive part 171 may be stacked on an upper surface of the second carrier 170 to fix the package intermediate product integrated with the encapsulant 140.
  • the second carrier 170 may include silicon, glass, ceramic, plastic, polymer, or the like.
  • the second adhesive part 171 may be a liquid adhesive or an adhesive tape.
  • the second adhesive part 171 may accommodate the external connection part 150 protruding from the encapsulant 140 while attaching one surface of the encapsulant 140.
  • the second adhesive part 171 may be provided to have elasticity.
  • the first insulating layer 131 may be stacked to cover the semiconductor chip 110, the substrate 120, and the encapsulant 140. In this case, the first insulating layer 131 may be provided to expose the through wire 123, the signal pad 113, and the sensor pattern 114. A process of removing a portion of the first insulating layer 131 may use an etching process or a laser removal process.
  • the first insulating layer 131 may include an insulator, and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • the wiring layer 132 may be stacked on the first insulating layer 131 to form a redistribution pattern electrically connecting the signal pad 113 and the through wiring 123.
  • the wiring layer 132 may fill the opened portion of the first insulating layer 131, and may be connected to the signal pad 113 and the through wiring 123 in this process.
  • the wiring layer 132 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the wiring layer 132 may be formed using various methods such as deposition, plating, and printing.
  • the wiring layer 132 may be formed of a prefabricated structure, and the structure may be bonded to the signal pad 113 and the through wiring 123 by crimping, bonding, or reflowing. It is included in the technical idea.
  • the second insulating layer 133 may be stacked on exposed surfaces of the first insulating layer 131 and the wiring layer 132. Although the drawing shows that the second insulating layer 133 is warm so that the wiring layer 132 is not exposed to the outside, a part of the second insulating layer 133 is removed to move the wiring layer 132 to the outside. May be exposed. At this time, the exposed wiring layer 132 may be used as a passage that can be electrically connected to the outside.
  • the second insulating layer 133 may include an insulating material, and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • FIG. 16 illustrates a process in which the sensor package 100 according to the embodiment of the present invention is provided by removing the second carrier 170 and the second adhesive part 171.
  • the external connection part 150 is exposed by removing the second carrier 170.
  • 17 is a cross-sectional view of a sensor package according to an embodiment of the present invention.
  • a sensor package 100 according to an embodiment of the present invention will be described with reference to FIG. 17. Referring to FIG. 17, except that the through member is formed in the sensor package according to FIGS. 1 and 2 and the via hole formed in the through wiring and the through wiring, the repeated description will be briefly or omitted.
  • the sensor package 100 includes a semiconductor chip 110 including a sensor pattern 114 exposed to the outside, and a receiving part 121 in which the semiconductor chip 110 is accommodated.
  • An encapsulant 140 molding to integrate the substrate 120, the semiconductor chip 110, and the substrate 120, a through wiring 123 penetrating the substrate 120 in a vertical direction, and the through wiring 123.
  • an external connection unit 150 that is electrically connected to the other side of the wiring unit 130 and the through wire 123 and electrically connected to the outside.
  • the through wire 123 may be a conductive material provided to surround the inner circumferential surface of the via hole 122, and may be a metal layer coated on the via hole 122.
  • the through wire 123 may be provided in a cylindrical shape, and the through member 124 may be filled in the via hole formed in the through wire 123.
  • the through member 124 may be a non-conductive resin, and may be formed to be filled in the via hole, that is, the hollow part of the through wire 123.
  • the penetrating member 124 includes a conductive material.
  • 18 is a cross-sectional view of a package-on-package in which the sensor package of FIG. 1 is stacked.
  • 18 is a cross-sectional view of a package-on-package (POP) in which a plurality of sensor packages 100 of FIG. 1 are stacked.
  • POP package-on-package
  • the package-on-package may be in a form in which two or more semiconductor packages are stacked.
  • the semiconductor packages stacked at this time may be heterogeneous products.
  • the package-on-package may have a structure in which the sensor package 100-2 and another semiconductor package 100-1, for example, a memory or logic semiconductor package, are stacked vertically.
  • the external connection part 150 of the sensor package 100-2 may be electrically connected to the wiring part 130 of the other semiconductor package 100-1.
  • the upper sensor package 100-2 may be positioned on the lower semiconductor package 100-1, and the second insulating layer 133 of the lower semiconductor package 100-1 is part of the wiring layer 132. May be provided to expose the interconnection, and the external connection unit 150 of the upper sensor package 100-2 may be connected to the wiring layer 132 of the exposed lower semiconductor package 100-1.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un boîtier de capteur et son procédé de préparation. Un boîtier de capteur, selon un mode de réalisation de la présente invention, comprend : une puce à semi-conducteur comprenant un motif de capteur qui est exposé de façon externe ; un substrat comprenant une partie de logement dans laquelle la puce à semi-conducteur est logée ; un matériau d'étanchéité pour mouler de façon intégrée la puce à semi-conducteur et le substrat ; un câblage traversant traversant verticalement le substrat ; une unité de câblage interconnectant électriquement la puce à semi-conducteur et le câblage traversant et exposant le motif de capteur de la puce à semi-conducteur ; et une unité de connexion externe électriquement connectée à l'autre côté du câblage traversant et pouvant être électriquement connectée à l'extérieur.
PCT/KR2017/000802 2016-02-04 2017-01-24 Boîtier de capteur et son procédé de préparation WO2017135624A1 (fr)

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KR1020160013959A KR20170093277A (ko) 2016-02-04 2016-02-04 센서 패키지 및 이의 제조 방법
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KR102052804B1 (ko) * 2017-12-15 2019-12-05 삼성전기주식회사 팬-아웃 센서 패키지
KR20190088812A (ko) 2018-01-19 2019-07-29 삼성전자주식회사 팬-아웃 센서 패키지
KR102015910B1 (ko) * 2018-01-24 2019-10-23 삼성전자주식회사 팬-아웃 센서 패키지
CN110993513A (zh) * 2019-12-17 2020-04-10 华天科技（昆山）电子有限公司 一种cis芯片的晶圆级扇出型封装方法以及结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237337A (ja) * 2000-02-23 2001-08-31 Sumitomo Metal Electronics Devices Inc プラスチックパッケージ及びその製造方法
US20100327429A1 (en) * 2009-06-29 2010-12-30 Ying-Te Ou Semiconductor package structure and package method thereof
KR20110076606A (ko) * 2009-12-29 2011-07-06 하나 마이크론(주) 반도체 패키지 제조방법
KR20130132162A (ko) * 2012-05-25 2013-12-04 주식회사 네패스 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
KR20140065723A (ko) * 2012-11-20 2014-05-30 앰코 테크놀로지 코리아 주식회사 지문인식센서 패키지 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237337A (ja) * 2000-02-23 2001-08-31 Sumitomo Metal Electronics Devices Inc プラスチックパッケージ及びその製造方法
US20100327429A1 (en) * 2009-06-29 2010-12-30 Ying-Te Ou Semiconductor package structure and package method thereof
KR20110076606A (ko) * 2009-12-29 2011-07-06 하나 마이크론(주) 반도체 패키지 제조방법
KR20130132162A (ko) * 2012-05-25 2013-12-04 주식회사 네패스 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
KR20140065723A (ko) * 2012-11-20 2014-05-30 앰코 테크놀로지 코리아 주식회사 지문인식센서 패키지 및 그 제조 방법

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