WO2011027185A1 - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
WO2011027185A1
WO2011027185A1 PCT/IB2009/006693 IB2009006693W WO2011027185A1 WO 2011027185 A1 WO2011027185 A1 WO 2011027185A1 IB 2009006693 W IB2009006693 W IB 2009006693W WO 2011027185 A1 WO2011027185 A1 WO 2011027185A1
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WO
WIPO (PCT)
Prior art keywords
protective layer
package structure
opening
openings
bumps
Prior art date
Application number
PCT/IB2009/006693
Other languages
English (en)
French (fr)
Inventor
周辉星
王志坚
罗基广
Original Assignee
先进封装技术私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 先进封装技术私人有限公司 filed Critical 先进封装技术私人有限公司
Priority to CN200980161160.1A priority Critical patent/CN102484078B/zh
Priority to US13/393,459 priority patent/US8766438B2/en
Priority to PCT/IB2009/006693 priority patent/WO2011027185A1/zh
Publication of WO2011027185A1 publication Critical patent/WO2011027185A1/zh

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to a package structure, and more particularly to a package structure having a second protective layer. Background technique
  • FIG. 1 illustrates a schematic diagram of a conventional package structure having a secondary passivation layer.
  • the general package structure 10 includes a semiconductor device 12, a passivation layer 14, a secondary passivation layer 16, a plurality of solder bumps 18, a substrate 20, and an adhesive 22.
  • the surface of the semiconductor component 12 has a plurality of pads 12a for use as end points for electrical connections.
  • the surface of the semiconductor element 12 is further covered with a passivation layer 14 having a protective function, and the passivation layer 14 exposes a portion of the pad 12a.
  • the general passivation layer 14 Since the general passivation layer 14 has a relatively thin thickness, it is susceptible to stress and cracking occurs. Therefore, in recent years, the industry has developed a package structure 10 in which a secondary passivation layer 16 is formed on the passivation layer 14 to avoid the problem that the passivation layer 14 is broken to cause deterioration in quality.
  • the solder bumps 18 connect the semiconductor elements 12 and the reverse 20 via the exposed partial pads 12a.
  • the encapsulant 22 is filled between the substrate 20 and the secondary passivation layer 16 and is coated with a plurality of solder bumps 18.
  • the area of the pad 12a has been reduced by less than 75 micrometers as the package volume is reduced, such a structure in which the passivation layer and the secondary passivation layer 16 are stacked further causes the exposed pads 12a to be exposed.
  • the area is reduced. Therefore, the area in which the solder bumps 18 are in contact with the pads 12a is also reduced by the secondary passivation layer.
  • the stress between the solder bumps 18 and the pads 12a becomes large as the contact area becomes smaller, and cannot pass the subsequent reliability test (e.g., thermal cycle). That is, the bonding force between the bad bump 18 and the pad 12a is increased due to the increase in stress, and the solder bump 18 cannot be tightly bonded to the pad 12a.
  • the secondary passivation layer 16 since the material of the secondary passivation layer 16 is softer and the bonding force of the encapsulant 22 is lower, the secondary passivation layer 16 cannot be firmly bonded to the encapsulant 22 or the solder bumps 18, so that the semiconductor element 12 is It cannot be stably fixed to the substrate 20. Summary of the invention
  • the area of the first protective layer is coupled to increase the bonding force between the sealant and the electric bump and the semiconductor element, and the semiconductor element is firmly fixed on the reverse side.
  • a package structure includes a semiconductor component, a first protection layer, a second protection layer, and at least one conductive bump.
  • the semiconductor component has at least one pad.
  • the first protective layer is disposed on the semiconductor element and exposes the pad.
  • the second protective layer is disposed on the first protective layer, and the second protective layer has at least one first opening and at least one second opening.
  • the first opening exposes a portion of the surface of the pad.
  • the second opening exposes a portion of the surface of the first protective layer.
  • the conductive bumps are disposed on the second protective layer, and the conductive bumps are coupled to the pads through the first openings.
  • the package structure includes a semiconductor component, a protective layer, a plurality of bumps, and at least one conductive bump.
  • the semiconductor component has at least one pad.
  • the protective layer is disposed on the semiconductor component and exposes a portion of the surface of the pad.
  • a plurality of bumps are disposed on the protective layer to expose a portion of the protective layer and the pads.
  • the at least one conductive bump is disposed on the protective layer of the bump and the portion, and the conductive bumps are coupled to the pad.
  • 1 is a schematic view showing a conventional package structure having a secondary passivation layer
  • FIG. 2 is a side view of a package structure in accordance with a first embodiment of the present invention
  • FIG. 3 is a top plan view of a second protective layer in accordance with the package structure of FIG. 2;
  • FIG. 4 is a side view showing a package structure of a second embodiment of the present invention.
  • FIG. 5 is a top plan view of a second protective layer in accordance with the package structure of FIG. 4;
  • FIG. 6 is a side view showing a package structure of a third embodiment of the present invention.
  • Figure 7 is a plan view showing the package structure in accordance with Figure 6;
  • FIG. 8 is a side view showing a package structure of a fourth embodiment of the present invention.
  • FIG. 9 is a top plan view of the package structure in accordance with FIG. 8.
  • Figure 10 is a side elevational view of a package structure in accordance with a fifth embodiment of the present invention.
  • Figure 11 is a top plan view of the conductive bump of the package structure in accordance with Figure 10;
  • Figure 12 is a side elevational view of a package structure of a sixth embodiment of the present invention.
  • FIG. 13 is a top view of a protective layer and bumps in accordance with the package structure of FIG. Main component symbol description
  • the package structure 100 includes a semiconductor component 110, a first protection layer 120, a second protection layer 130, and at least one conductive bump 140.
  • the semiconductor device 110 has at least one pad 110a.
  • the first protective layer 120 is disposed on the semiconductor device 110 and exposes the pad 110a.
  • the second protective layer 130 is disposed on the first protective layer 120, and the second protective layer 130 has at least one first opening 130a and at least one second opening 130b.
  • the first opening 130a exposes a portion of the surface of the pad 110a.
  • the second opening 130b exposes a portion of the surface of the first protective layer 120.
  • the conductive bumps 140 are disposed on the second protective layer 130, and the conductive bumps 140 are coupled to the pads 110a through the first openings 130a.
  • a semiconductor device 110 having two pads 110a and two conductive bumps 140 will be described.
  • the semiconductor device 110 is, for example, a wafer, and the semiconductor device 110 has a plurality of pads 110a.
  • the first protective layer 120 is disposed on the semiconductor device 110.
  • the first protective layer 120 has an opening 120a and the opening 120a exposes a portion of the surface of the plurality of pads 110a.
  • the second protective layer 130 is disposed on the first protective layer 120 for buffering the stress on the first protective layer 120.
  • the second protective layer 130 has a plurality of first openings 130a corresponding to the pads 110a, and exposes a part of the surface of the plurality of pads 110a.
  • the second protective layer 130 has a second opening 130b in the embodiment, and is located on the conductive bump 140, and exposes a part of the surface of the first protective layer 120.
  • the thickness of the first protective layer 120 is, for example, less than 2 micrometers ( ⁇ )
  • the thickness of the second protective layer 130 is, for example, greater than 2 micrometers
  • the material of the first protective layer 120 and the second protective layer 130 are The material of the first protective layer 120 is actually greater than the material hardness of the second protective layer 130.
  • the material of the first protective layer 120 is, for example, selected from the group consisting of silicon nitride (SiyNx) and silicon oxide (SiO x ), and more commonly, silicon nitride (Si 3 N 4 ) or silicon dioxide (Si0 2 ). ).
  • the material of the second protective layer 130 is preferably a polymer. Commonly, there are benzocyclobutane (BCB) or poly-imide (PI).
  • the package structure 100 of the present embodiment preferably further includes a substrate 150 and an adhesive 160.
  • the substrate 150 is bonded to the semiconductor component 110 through the conductive bumps 140.
  • the encapsulant 160 is filled between the substrate 150 and the first protective layer 120.
  • the encapsulant 160 encloses the conductive bump 140 and is coupled to the first protective layer 120 through the second opening 130b. Since the material hardness of the second protective layer 130 is small, the bonding force of the sealant 160 and the second protective layer 130 is weak. Therefore, when the sealant 160 is coupled to the first protective layer 120 through the second opening 130b, the bonding force of the sealant 160 to fix the semiconductor component 110 is increased. In this way, the semiconductor element 110 can be firmly bonded to the substrate 150.
  • the substrate 150 may also be a lead frame. However, the substrate 150 is not limited to a lead frame.
  • the substrate may be a glass substrate, a silicon substrate or a substrate of other materials.
  • FIG. 3 illustrates a top view of the second protective layer in accordance with the package structure of FIG. 2 .
  • the drawing of the partial elements is omitted for the subsequent description. Because the second protective layer 130 is used to buffer the stress on the first protective layer 120, and the sealant 160 is coupled to the first protective layer 120 through the second opening 130b to enhance the bonding force of the sealant 160 to fix the semiconductor element 110.
  • the total area of the first opening 130a of the second protective layer 130 of the present embodiment and the area of the second opening 130b are substantially larger than the opening 120a of the first protective layer 120, preferably
  • the ratio of the area of the two openings 130b to the area of the semiconductor element 110 is substantially between 20% and 99%. That is, an appropriate increase between the ratios
  • the area to which the first protective layer 120 is coupled enables the substrate 150 to be firmly bonded to the semiconductor element 110.
  • the second opening 130b of the embodiment is disposed between the two conductive bumps 140.
  • the second opening 130b of the embodiment only needs to be located outside the conductive bump, so that the sealant 160 can be
  • the first protective layer 130 is coupled through the second opening 130b to increase the bonding force of each other. Therefore, it is not necessary to limit the arrangement position and shape of the second opening 130b. It will be apparent to those skilled in the art that the method of arranging the conductive bump 140 and the pad 110a of the present invention is not limited thereto. Second embodiment
  • the package structure disclosed in this embodiment differs from the package structure of the first embodiment mainly in the number of the second openings 230b of the second protective layer 230, and the rest will not be described again.
  • FIG. 4 a side view of a package structure according to a second embodiment of the present invention is shown.
  • the second protective layer 230 has a plurality of first openings 230a and a plurality of second openings 230b outside the conductive bumps 140.
  • the plurality of first openings 230a of the second protective layer 230 expose a part of the surface of the pad 110a.
  • the plurality of second openings 230b expose a portion of the surface of the first protective layer 120, and the sealant 160 is coupled to the first protective layer 120 through the plurality of second openings 230b to enhance the bonding force of the sealant 160 to fix the semiconductor device 110.
  • FIG. 5 illustrates a top view of the second protective layer in accordance with the package structure of FIG. 4 .
  • the drawing portion portion elements are omitted for clearly indicating the second protective layer 230 for the subsequent description.
  • the second protective layer 230 has a plurality of second openings 230b, and the second openings 230b are arranged in a matrix.
  • the sealant 160 can be coupled to the first protective layer 120 through the second opening 230b to increase the fixing.
  • the combination of the area of the first opening 230a of the second protective layer 230 of the present embodiment and the area of the second opening 230b is larger than the opening 120a of the first protective layer 120, and the preferred second opening 230b.
  • the ratio of the area to the area of the semiconductor element 110 is preferably between 20% and 99%.
  • the second openings 230b of this embodiment may be arranged in other ways than the matrix arrangement, such as an interlaced arrangement. Therefore, those skilled in the art can understand that the arrangement method of the second opening 230b of this embodiment is not limited to the matrix arrangement.
  • the package structure 300 disclosed in this embodiment is different from the package structure 100 of the first embodiment.
  • the location of the second opening 330b of the second protective layer 330 is mainly in the same place, and the rest will not be described again.
  • the second protective layer 330 has a second opening 330b under the conductive bumps 340, and the second opening 330b exposes a portion of the surface of the first protective layer 120.
  • the conductive bumps 340 are disposed on the second protective layer 330, and the conductive bumps 340 are coupled to the pads 110a through the first openings 330a and coupled to the first protective layer 120 through the second openings 330b. .
  • the bonding force between the conductive bump 340 and the semiconductor element 110 can be effectively increased, so that the semiconductor element 110 can be stably fixed to the reverse 150.
  • FIG. 7 illustrates a top view of the package structure in accordance with FIG. 6.
  • the second protective layer 330 has a second opening 330b under the conductive bumps 340.
  • the conductive bumps 340 can be coupled to the first protective layer 120 through the second opening 330b at the same time to increase the fixed bonding force.
  • the total area of the first opening 330a of the second protective layer 330 of the present embodiment and the area of the second opening 330b are substantially larger than the opening 120a of the first protective layer 120, and the area of the preferred second opening 330b and the semiconductor.
  • the ratio of the area of the element 110 is preferably between 20% and 99%.
  • the second protective layer 330 of the present embodiment covers the first protective layer 120.
  • the second protective layer 330 may also be disposed on the first protective layer 120 in an island shape.
  • the second opening 330b may have a square opening or the like in addition to a circular opening. It is to be understood by those skilled in the art that the second protective layer 330 of the present embodiment does not limit the shape it is provided and the shape and size of the second opening 330b.
  • the package structure 400 disclosed in this embodiment differs from the package structure 300 of the third embodiment mainly in the number of the second openings 430b of the second protective layer 430, and the rest are not described again.
  • FIG. 8 is a side view of a package structure according to a fourth embodiment of the present invention.
  • the second protective layer 430 has a second opening 430b under the number of conductive bumps 440, and the second opening 430b exposes a portion of the surface of the first protective layer 120.
  • the conductive bumps 440 are disposed on the second protective layer 120, and the conductive bumps 440 are coupled to the pads 110a through the first openings 430a and through the plurality of second openings 430b and the first protective layer 120. Coupling. In this way, The bonding force between the conductive bump 440 and the semiconductor element 110 can be effectively increased to enable the semiconductor element 110 to be stably fixed to the reverse 150.
  • FIG. 9 is a top view of the package structure according to FIG. Similarly, some of the components of the package structure 400 are omitted for clarity of the second protective layer 430 for subsequent description.
  • the second protective layer 430 of this embodiment is disposed on the first protective layer 120 in an island shape. Therefore, the conductive bump 440 is not completely seated on the second protective layer 430, but is partially seated on the second protective layer 430 and partially seated on the first protective layer 120. In this way, the encapsulant 460 can be directly coupled to the first protective layer 120, and the bonding force between the substrate 150 and the semiconductor element 110 can also be enhanced.
  • the second protective layer 430 has a plurality of second openings 430b under the conductive bumps 440, and the second openings 430b are arranged, for example, in a matrix.
  • the conductive bumps 440 can be coupled to the first protective layer 120 through the plurality of second openings 430b to increase the bonding force between the conductive bumps 440 and the semiconductor device 110, so that the semiconductor device 110 is firmly fixed to the semiconductor device 110.
  • an island-shaped second protective layer 430 is provided with a plurality of conductive bumps 440, for example, but an island-shaped second protective layer 430 may also be provided with only one conductive bump 440.
  • the conductive bumps 440 of the present embodiment are not completely seated on the second protective layer 430. However, the conductive bumps 440 may also be completely seated on the island-shaped second protective layer 430.
  • the second protective layer 430 in order to enable the second protective layer 430 to effectively buffer the stress on the first protective layer 120, and the conductive bumps 460 can be coupled to the first protective layer 120 through the second opening 430b at the same time to increase the fixed bonding force.
  • the sum of the area of the first opening 430a of the second protective layer 430 of the present embodiment and the area of the second opening 430b is substantially larger than the opening 120a of the first protective layer 120, preferably the second opening.
  • the second protective layer 430 is disposed on the first protective layer 120 in an island shape as shown in FIG.
  • the second openings 430b of the second protective layer 430 are arranged in a matrix type in this embodiment, or may be arranged in a non-matrix type, such as a staggered type or a spaced type. That is to say, the second protective layer 430 and the opening 430b thereof are disposed according to actual applications, and the shape of the second protective layer 430 is not limited thereto, and the position, the number and the opening of the second opening 430b are not limited. shape.
  • the second protective layer 530 has at least two second openings 530b, wherein a second opening 530b is located outside the conductive bumps 540, and a second opening 530b is located below the conductive bumps 540.
  • both the sealant 560 and the conductive bumps 540 can be coupled to the first protective layer 120 via the second opening 530b, so that the semiconductor device 110 is stably fixed on the reverse side.
  • FIG. 11 is a top view of the conductive bump of the package structure of FIG.
  • the second protective layer 530 has a plurality of second openings 530b arranged in a matrix, wherein a portion of the second openings 530b are located under the conductive bumps 540, and a portion of the second openings 530b are located at the conductive bumps 540.
  • the conductive bumps 540 are arranged in an interlaced manner in this embodiment, but are not limited to such an arrangement method, and may be arranged in other manners.
  • the conductive bumps 540 and the sealant 560 can be coupled to the first protective layer 120 through the second opening 530b to increase
  • the total bonding force of the second opening 530a of the second protective layer 530 of the present embodiment is substantially larger than the opening 120a of the first protective layer 120.
  • the second protective layer 530 of the present embodiment covers the first protective layer 120.
  • the second protective layer 530 may also be disposed on the first protective layer 120 in an island shape.
  • the second opening 530b may have a circular opening or a square opening or the like. It is to be understood by those skilled in the art that the second protective layer 530 of the present embodiment does not limit the shape it is provided and the shape and size of the second opening 530b.
  • the package structure 600 disclosed in this embodiment differs from the above embodiment mainly in that a plurality of bumps 630 are provided as the second protection layer, and the rest are not described again.
  • the package structure 600 includes a semiconductor component 610, a protective layer 620, a plurality of bumps 630, and at least one conductive bump 640.
  • the semiconductor component 610 has at least one pad 610a.
  • the protective layer 620 is disposed on the semiconductor A portion of the surface of the pad 610a is exposed on the component 610.
  • a plurality of bumps 630 are disposed on the protective layer 620 from each other to expose a portion of the protective layer 620 and the pads 610a.
  • the at least one conductive bump 640 is disposed on the bump 630 and the portion of the protective layer 620, and the conductive bumps 640 are coupled to the pad 610a.
  • the bump 630 is disposed on the protective layer 620 for buffering the stress on the protective layer 620.
  • an opening 630a is further formed between the bumps 630 under the conductive bumps 640, so that the conductive bumps are electrically connected to the pads 610a through the openings 630a.
  • the bumps 630 are disposed apart from each other on the protective layer 620 so that a part of the surface of the protective layer 620 can be exposed.
  • the thickness of the protective layer 620 is, for example, less than 2 micrometers, and the thickness of the bumps 630 is, for example, greater than 2 micrometers ( ⁇ ), and the material of the protective layer 620 is different from the material of the bumps 630, and the protective layer
  • the material hardness of 620 is substantially greater than the material hardness of bump 630.
  • the material of the protective layer 620 is silicon nitride (SiNx), and the material of the bump 630 is preferably a polymer, and a common one is benzocyclobutane (BCB) or poly-imide (poly-imide, PI) and so on.
  • the package 1 600 further includes an anti-650 and a glue 660.
  • the substrate 650 is bonded to the semiconductor element 610 through the conductive bumps 640.
  • the encapsulant 660 is filled between the substrate 650 and the protective layer 620, and the encapsulant 660 covers the conductive bumps 640 and the bumps 630. Since the material of the bump 630 is small, the bonding force between the sealant 660 and the conductive bump 640 and the bump 630 is weak. Therefore, when the sealant 660 and the conductive bump 640 are coupled to the bump 630 and the protective layer 620 at the same time, the bonding force of the sealant 660 and the conductive bump 640 to fix the semiconductor component 610 is enhanced. As a result, the semiconductor element 610 can be firmly fixed to the counter 650.
  • FIG. 13 a top view of the protective layer and the bump according to the package structure of FIG. 12 is illustrated.
  • some components of the package structure 600 are omitted for clearly indicating the configuration of the bumps 630 for the subsequent description.
  • the area of the bumps 630 that is not disposed in the embodiment is substantially larger than the opening 620a of the protective layer 620.
  • the bumps 630 are used.
  • the ratio of the area of the semiconductor element 610 to the area of the semiconductor element 610 is substantially between 1% and 80%.
  • the bumps 630 are arranged in a matrix on the protective layer.
  • the method of arranging the bumps 630 is not limited thereto, and the alignment method may be arranged in an interlaced manner.
  • the bumps 630a of the present embodiment may be, for example, island-like structures and circular bumps, and may be square-shaped bumps. Therefore, those skilled in the art are not limited thereto.
  • the package structure disclosed in the above embodiments of the present invention increases the area where the conductive bumps and/or the sealant are coupled to the first protective layer to increase the bonding between the conductive bumps and/or the sealant and the semiconductor components. Force. In this way, not only the second protective layer or the bump can effectively buffer the stress of the first protective layer, but also the semiconductor element can be stably fixed on the reverse side.

Abstract

本发明公开一种封装结构，封装结构包括一半导体元件、一第一保护层、一第二保护层及至少一导电凸块。半导体元件具有至少一接垫。第一保护层设置于半导体元件上并暴露接垫。第二保护层设置于第一保护层上，且第二保护层具有至少一第一开口及至少一第二开口。第一开口暴露出接垫的部分表面。第二开口暴露出第一保护层的部分表面。导电凸块相对接垫设置于第二保护层上，且此些导电凸块通过此些第一开口耦接于接垫。

Description

封装结构 技术领域
本发明涉及一种封装结构， 且特别是涉及具有第二保护层的封装结构。 背景技术
请参照图 1 , 其绘示传统具有二次钝化层的封装结构的示意图。 一般的 封装结构 10, 包括一半导体元件 (Semiconductor device)12、 一钝化层 14、 一 二次钝化层 16、 数个焊料凸块 18、 基板 20及一封胶 22。 半导体元件 12的 表面具有数个接垫 12a， 用以作为电连接的端点。 半导体元件 12的表面更覆 盖有具保护功能的一钝化层 14 ( passivation layer ), 且此钝化层 14暴露部分 的接垫 12a。
由于一般钝化层 14具有较薄的厚度,容易受到应力作用而发生破裂的现 象。 因此， 近年来业界发展出一种于钝化层 14 上再形成二次钝化层 (repassivation layer) 16的封装结构 10， 以避免钝化层 14破裂导致品质下降的 问题。 焊料凸块 18则经由暴露出的部分接垫 12a连接半导体元件 12与 反 20。 封胶 22则填充于基板 20与二次鈍化层 16之间， 且包覆数个焊料凸块 18。
然而，由于接垫 12a的面积随着封装体积缩小也已低于 75微米 (micron), 而此种由钝化层与二次钝化层 16堆叠的结构更使得所暴露出的接垫 12a的面 积减少。 因此， 焊料凸块 18与接垫 12a接触的面积也因二次钝化层而缩小。 然而，焊料凸块 18与接垫 12a间的应力会因接触的面积变小而变大， 而无法 通过后续可信赖测试 (如热循环)时。 也就是坏料凸块 18与接垫 12a之间会因 应力变大而使彼此间的结合力降低,焊料凸块 18便无法与接垫 12a紧密接合。 此外， 由于二次钝化层 16的材质较软与封胶 22的结合力也较低， 而使二次 钝化层 16无法稳固地与封胶 22或焊料凸块 18接合， 以致于半导体元件 12 无法稳定地固定于基板 20上。 发明内容
本发明的目的在于提供一种封装结构， 通过增加封胶及导电凸块两者与 第一保护层耦接的面积， 以使封胶及电凸块两者与半导体元件间的结合力增 加， 而使半导体元件牢固的固定于 反上。
根据本发明的一观点， 提出一种封装结构， 且封装结构包括一半导体元 件、 一第一保护层、 一第二保护层及至少一导电凸块。 半导体元件具有至少 一接垫。 第一保护层设置于半导体元件上并暴露接垫。 第二保护层设置于第 一保护层上， 且第二保护层具有至少一第一开口及至少一第二开口。 第一开 口暴露出接垫的部分表面。 第二开口暴露出第一保护层的部分表面。 导电凸 块相对接垫设置于第二保护层上， 且此些导电凸块通过此些第一开口耦接于 接垫。 '
根据本发明的一观点， 提出另一种封装结构， 封装结构， 包括一半导体 元件、 一保护层、 数个凸块以及至少一导电凸块。 半导体元件具有至少一个 接垫。 保护层设置于半导体元件上并暴露出该接垫的部分表面。 数个凸块彼 此分隔设置于保护层上， 以暴露出部分的保护层及接垫。 至少一导电凸块相 对接垫设置于此些凸块及部分的保护层上， 且此些导电凸块耦接于接垫。
为让本发明的上述内容能更明显易懂， 下文特举较佳实施例， 并配合所 附附图， 作详细说明如下： 附图说明
图 1绘示传统具有二次钝化层的封装结构的示意图；
图 2绘示依照本发明第一实施例的封装结构的侧视图；
图 3绘示依照图 2中封装结构的第二保护层的俯视图；
图 4绘示本发明第二实施例的封装结构的侧视图；
图 5绘示依照图 4中封装结构的第二保护层的俯视图；
图 6绘示本发明笫三实施例的封装结构的侧视图；
图 7绘示依照图 6中封装结构的俯视图；
图 8绘示本发明第四实施例的封装结构的侧视图；
图 9绘示依照图 8中封装结构的俯视图；
图 10绘示依照本发明第五实施例的封装结构的侧视图；
图 11绘示依照图 10的封装结构的导电凸块的上视图；
图 12绘示本发明第六实施例的封装结构的侧视图； 以及
图 13绘示依照图 12中封装结构的保护层及凸块的上视图。 主要元件符号说明
10、 100、 200、 300、 400、 500、 600: 封装结构
12、 110、 610: 半导体元件
12a、 110a, 610a: 接垫
14: 钝化层
16: 二次钝化层
18: 焊料凸块
20、 150、 650: 基板
22、 160、 460、 560、 660: 封胶
120: 第一保护层
120a、 620a: 开口
130、 230、 330、 430、 530: 第二保护层
130a、 230a, 330a, 430a、 530a: 第一开口
130b, 230b, 330b, 430b ^ 530b: 第二开口
140、 340、 440、 540、 640: 导电凸块
620: 保护层
630: 凸块
630a: 开口 具体实施方式
第一实施例
请参照图 2, 其绘示依照本发明第一实施例的封装结构的侧视图。 封装 结构 100包括一半导体元件 110、一第一保护层 120、一第二保护层 130以及 至少一导电凸块 140。 半导体元件 ( semiconductor device ) 110具有至少一接 垫 110a。 笫一保护层 120设置于半导体元件 110上， 并暴露接垫 110a。 第二 保护层 130设置于第一保护层 120上， 且第二保护层 130具有至少一第一开 口 130a及至少一第二开口 130b。 第一开口 130a暴露出接垫 110a的部分表 面。第二开口 130b暴露出第一保护层 120的部分表面。导电凸块 140相对接 垫 110a设置于第二保护层 130上， 且此些导电凸块 140通过第一开口 130a 耦接于接垫 110a。 在此， 为了方便后续实施例的说明， 以具有二个接垫 110a 的半导体元件 110及二个导电凸块 140作说明。 在本实施例中， 半导体元件 110例如为一晶片， 且此半导体元件 110具 有数个接垫 110a。 第一保护层 120设置于此半导体元件 110上， 此第一保护 层 120具有一开口 120a且此开口 120a曝露出数个接垫 110a的部分表面。第 二保护层 130设置于第一保护层 120上， 用以緩冲笫一保护层 120所受的应 力。 此外， 第二保护层 130对应接垫 110a具有数个第一开口 130a, 并曝露 出数个接垫 110a的部分表面。此外，第二保护层 130在本实施例中具有一第 二开口 130b，且位于导电凸块 140夕卜，并暴露出第一保护层 120的部分表面。
在本实施例中， 第一保护层 120的厚度例如小于 2微米 (μηι), 第二保护 层 130的厚度例如大于 2微米 (μιη), 且第一保护层 120的材料与第二保护层 130的材料不同， 而第一保护层 120的材料硬度实庸上大于第二保护层 130 的材料硬度。 第一保护层 120的材料例如选自于硅氮化物 （SiyNx )及硅氧 化物 （SiOx )群组， 较常见的有四氮化三硅（Si3N4 )或二氧化硅（Si02 )。 且第二保护层 130 的材料较佳地为一聚合物， 常见的有苯并环丁烷 ( benzocyclobutane, BCB )或聚亚醯胺 ( poly-imide, PI )等。
本实施例的封装结构 100较佳地更包括一基板 150及一封胶 160。 基板
150通过此些导电凸块 140与半导体元件 110接合。封胶 160填充于基板 150 与第一保护层 120之间， 封胶 160包覆导电凸块 140且通过第二开口 130b 与第一保护层 120耦接。由于第二保护层 130的材料硬度较小，所以封胶 160 与第二保护层 130的结合力较弱。故，封胶 160通过第二开口 130b与第一保 护层 120耦接时， 便会增加封胶 160固定半导体元件 110的结合力。 如此一 来，便能使半导体元件 110稳固地与基板 150结合。在本实施例中，基板 150 也可为导线架， 然而并不限定基板 150为导线架> 也可为玻璃基板、 硅基板 或其他材质的基板。
请参照图 3, 其绘示依照图 2中封装结构的第二保护层的俯视图。 此处， 为清楚标示第一开口 130a及第二开口 130b的位置而省略绘制部分元件， 以 利后续说明。 由于， 第二保护层 130为了緩冲第一保护层 120所受的应力， 且封胶 160通过第二开口 130b与第一保护层 120耦接以增强封胶 160固定半 导体元件 110的结合力。 为能同时达成上述的功效， 本实施例的第二保护层 130的第一开口 130a的面积与第二开口 130b的面积的总合实质上大于第一 保护层 120的开口 120a， 较佳的第二开口 130b的面积与半导体元件 110的 面积的比值实质上界于 20 % ~ 99 %之间。 也就是说， 在比值间适当的增加与 第一保护层 120耦接的面积， 便能使基板 150稳固地接合于半导体元件 110 上。 此外， 如图 2所示， 本实施例的第二开口 130b设置于二个导电凸块 140 间， 实际上本实施例的第二开口 130b仅需位于导电凸块外， 以使封胶 160 可通过第二开口 130b与第一保护层 130耦接以增加彼此的结合力。故在此不 需限定其第二开口 130b的配置位置及形状。然熟知此技术者均可明了本发明 的导电凸块 140与接垫 110a的配置方法并不局限在此。 第二实施例
本实施例所揭示封装结构， 其与第一实施例的封装结构不同之处， 主要 在于第二保护层 230的第二开口 230b的数量，其余相同之处并不再赘述。请 参照图 4, 其绘示本发明第二实施例的封装结构的侧视图。 在本实施例中， 第二保护层 230具有数个第一开口 230a及数个位于导电凸块 140外的第二开 口 230b。
其中， 第二保护层 230的数个第一开口 230a暴露出接垫 110a的部分表 面。数个第二开口 230b曝露出部分的第一保护层 120表面，而封胶 160通过 数个第二开口 230b与第一保护层 120耦接，以增强封胶 160固定半导体元件 110的结合力。
接着， 请参照图 5 , 其绘示依照图 4中封装结构的第二保护层的俯视图。 相同地，为清楚标示第二保护层 230而省略绘制部部分元件， 以利后续说明。 在本实施例中，第二保护层 230具有数个第二开口 230b，且此些第二开口 230b 以矩阵式排列。 同于第一实施例， 为使第二保护层 230能有效緩冲第一保护 层 120所受的应力，且封胶 160能同时通过第二开口 230b与第一保护层 120 耦接以增加固定的结合力，本实施例的第二保护层 230的第一开口 230a的面 积与第二开口 230b的面积的总合实盾上大于第一保护层 120的开口 120a， 较佳的第二开口 230b的面积与半导体元件 110的面积的比值较佳地界于 20 % ~99 %之间。 然而本实施例的第二开口 230b除矩阵式排列的方法外也可以 其他方式排列， 如交错式排列。 故熟知此技术者均可明了本实施例的第二开 口 230b的排列方法并不限定于矩阵式排列。 第三实施例
本实施例所揭示的封装结构 300, 其与第一实施例的封装结构 100不同 之处，主要在于第二保护层 330的第二开口 330b的位置，其余相同之处并不 再赘述。
请参照图 6, 其绘示本发明第三实施例的封装结构的侧视图。 在本实施 例中， 第二保护层 330具有位于导电凸块 340下的第二开口 330b， 且此第二 开口 330b暴露出第一保护层 120的部分表面。 导电凸块 340相对接垫 110a 设置于第二保护层 330上，且此些导电凸块 340通过第一开口 330a耦接于接 垫 110a, 并通过第二开口 330b与第一保护层 120耦接。 如此一来， 便能有 效增加导电凸块 340与半导体元件 110之间的结合力， 以使半导体元件 110 能稳定的固定于 反 150上。
接着， 请参照图 7, 其绘示依照图 6中封装结构的俯视图。 相同地， 为 清楚标示第二保护层 330而省略绘制封装结构 300的部分元件， 以利后续说 明。 在本实施例中， 第二保护层 330具有一第二开口 330b位于导电凸块下 340。此外， 为使第二保护层 330能有效緩冲第一保护层 120所受的应力， 且 导电凸块 340能同时通过笫二开口 330b与第一保护层 120耦接以增加固定的 结合力。 故本实施例的第二保护层 330的第一开口 330a的面积与第二开口 330b的面积的总合实质上大于第一保护层 120的开口 120a,较佳的第二开口 330b的面积与半导体元件 110的面积的比值较佳地界于 20 % ~99 %之间。 此 夕卜， 本实施例的第二保护层 330覆盖于第一保护层 120上， 除此之外， 第二 保护层 330也可以岛状设置于第一保护层 120上。另外，第二开口 330b除可 为圆型开口外， 也可为方型开口等型状。 故熟知此技艺者均可明了本实施例 的第二保护层 330并不限定其设置的形状以及第二开口 330b的形状及大小。 第四实施例
本实施例所揭示封装结构 400， 其与第三实施例的封装结构 300不同之 处，主要在于第二保护层 430的第二开口 430b的数量，其余相同之处并不再 赘述。
请参照图 8, 其绘示本发明第四实施例的封装结构的侧视图。 在本实施 例中， 第二保护层 430具有位数个导电凸块 440下的第二开口 430b, 且此第 二开口 430b暴露出第一保护层 120的部分表面。导电凸块 440相对接垫 110a 设置于第二保护层 120上，且此些导电凸块 440通过第一开口 430a耦接于接 垫 110a， 并通过数个第二开口 430b与第一保护层 120耦接。 如此一来， 便 能有效增加导电凸块 440与半导体元件 110之间的结合力， 以使半导体元件 110能稳定的固定于 反 150上。
接着， 请参照图 9, 其绘示依照图 8中封装结构的俯视图。 相同地， 为 清楚标示第二保护层 430而省略绘制封装结构 400的部分元件， 以利后续说 明。 本实施例的第二保护层 430以岛状设置于第一保护层 120上。 故导电凸 块 440并非完全座落于第二保护层 430上， 而是局部座落于第二保护层 430 上且局部座落于笫一保护层 120上。 如此一来， 封胶 460便能直接与第一保 护层 120耦接， 也能加强基板 150与半导体元件 110间的结合力。
此外，第二保护层 430具有数个第二开口 430b位于导电凸块 440下，且 此些第二开口 430b例如以矩阵式排列。如此一来，导电凸块 440可通过数个 第二开口 430b与笫一保护层 120耦接， 以增加导电凸块 440与半导体元件 110之间的结合力， 以使半导体元件 110稳固地固定于 ^反 150上。 此外， 在本实施例中， 一岛状的第二保护层 430例如同时设置数个导电凸块 440， 然而一岛状的第二保护层 430也可仅设置一导电凸块 440。 另外， 本实施例 的导电凸块 440并非完全座落于第二保护层 430上， 然不限于此， 导电凸块 440也可完全座落于岛状的第二保护层 430上。
相同地， 为使第二保护层 430能有效緩冲第一保护层 120所受的应力， 且导电凸块 460能同时通过第二开口 430b与第一保护层 120耦接以增加固定 的结合力， 本实施例的第二保护层 430的第一开口 430a的面积与第二开口 430b的面积的总合实质上大于第一保护层 120的开口 120a，较佳的第二开口 然而， 对于熟知此项技术的人士而言， 皆可明了本发明并不限于上述实 施方式。在本实施例中，第二保护层 430如图 9以岛状设置于笫一保护层 120 上， 也可如图 7的第二保护层 330般平铺覆盖于第一保护层 120上。 此外， 笫二保护层 430的第二开口 430b于本实施例以矩阵型排列，也可以非矩阵型 排列， 如交错型或间隔型。也就是说， 第二保护层 430及其开口 430b视实际 应用设置， 在此并不限定其第二保护层 430的所设置的形状， 也不限定其第 二开口 430b的设置位置、 数量及开口形状。 第五实施例
在本实施例所揭示的封装结构 500中， 其与第四实施例的不同之处， 主 要在于第二保护层 530的第二开口 530b的位置， 其余相同之处并不再赘述。 请参照图 10, 其绘示依照本发明第五实施例的封装结构的侧视图。 在本 实施例中，第二保护层 530具有至少二第二开口 530b,其中的一第二开口 530b 位于导电凸块 540外，其中的一第二开口 530b位于导电凸块 540的下方。如 此一来， 封胶 560及导电凸块 540两者可经由第二开口 530b与第一保护层 120耦接， 而使半导体元件 110稳定的固定于 反上。
请同时参照图 10及图 11 , 图 11是图 10的封装结构的导电凸块的上视 图。 相同地， 为清楚标示导电凸块 540在图 11 中则省略绘制封装结构 500 的部分元件， 以利后续说明。 在本实施例中， 第二保护层 530具有数个第二 开口 530b, 且以矩阵式排列， 其中部分的第二开口 530b位于导电凸块 540 下，部分的笫二开口 530b位于导电凸块 540外。此外， 导电凸块 540于本实 施例以交错式的方式排列， 然而并不限于此种排列方法， 也可以其他的方式 排列。
相同地， 为使第二保护层 530能同时有效緩冲第一保护层 120所受的应 力，且导电凸块 540及封胶 560能通过第二开口 530b与第一保护层 120耦接 以增加固定的结合力，本实施例的第二保护层 530的第一开口 530a的面积与 第二开口 530b的面积的总合实质上大于第一保护层 120的开口 120a， 伞支佳
%之间。
此外，本实施例的第二保护层 530覆盖于第一保护层 120上，除此之外， 第二保护层 530也可以岛状设置于第一保护层 120上。 另外， 第二开口 530b 除可为圆型开口外， 也可为方型开口等型状。 故熟知此技术者均可明了本实 施例的第二保护层 530并不限定其设置的形状以及第二开口 530b的形状及大 小。 第六实施例
在本实施例中所揭示的封装结构 600， 其与上述实施例的不同之处， 主 要在于以设置数个凸块 630做为第二保护层， 其余之处并不再赘述。
请参照图 12, 其绘示本发明第六实施例的封装结构的侧视图。 封装结构 600包括一半导体元件 610、一保护层 620、数个凸块 630以及至少一导电凸 块 640。 半导体元件 610具有至少一个接垫 610a。 保护层 620设置于半导体 元件 610上并暴露出接垫 610a的部分表面。数个凸块 630彼此分隔设置于保 护层 620上， 以暴露出部分的保护层 620及接垫 610a。 至少一导电凸块 640 相对接垫 610a设置于此些凸块 630及部分的保护层 620上，且此些导电凸块 640耦接于接垫 610a。 于本实施例中， 设置凸块 630于保护层 620上用以緩 冲保护层 620所受的应力。 此外， 位于导电凸块 640下的凸块 630间更具有 一开口 630a, 以使导电凸块通过此开口 630a与接垫 610a电连接。 凸块 630 彼此分隔设置于保护层 620上， 故可棵露出保护层 620的部分表面。
在本实施例中， 保护层 620的厚度例如小于 2微米 (μιη), 且凸块 630的 厚度例如大于 2微米 (μηι), 且保护层 620的材料与凸块 630的材料不同， 且 保护层 620的材料硬度实质上大于凸块 630的材料硬度。 保护层 620的材料 为硅氮化物（SiNx ), 且凸块 630的材料较佳地为一聚合物， 常见的有苯并 环丁烷（benzocyclobutane, BCB )或聚亚醯胺（poly-imide, PI )等。
在本实施例中，封装 1 600更包括一 反 650及一封胶 660。基板 650 通过此些导电凸块 640与半导体元件 610接合。 封胶 660填充于基板 650与 保护层 620之间， 封胶 660包覆此些导电凸块 640及此些凸块 630。 由于凸 块 630的材料碩度较小 , 所以封胶 660及导电凸块 640与凸块 630的结合力 较弱。故， 当封胶 660与导电凸块 640同时与凸块 630及保护层 620耦接时， 便会增强封胶 660与导电凸块 640固定半导体元件 610的结合力。如此一来， 便能使半导体元件 610稳固地固定于 反 650上。
此外， 请参照图 13, 其绘示依照图 12中封装结构的保护层及凸块的上 视图。 此处， 为清楚标示凸块 630的配置而省略绘制封装结构 600的部分元 件， 以利后续说明。 由于， 此些凸块 630为了緩冲保护层 620所受的应力而 设置， 在本实施例未设置凸块 630 的面积实质上略大于保护层 620 的开口 620a, 较佳地此些凸块 630占半导体元件 610的面积与半导体元件 610的面 积的比值实质上界于 1 % ~ 80 %之间。
此外， 在本实施例中， 凸块 630以矩阵式排列在保护层上， 实际上凸块 630 的排列设置方法并不限定于此， 也可以交错式排列等排列方法。 再者， 本实施例的凸块 630a例如为岛状结构及圆形凸点也可为方形凸块，故熟悉此 技术者明了并不限定于此。
本发明上述实施例所揭露的封装结构，是增加导电凸块及 /或者封胶与第 一保护层耦接的面积， 以增加导电凸块及 /或者封胶与半导体元件间的结合 力。如此一来，不但第二保护层或凸块能有效緩冲笫一保护层的所受的应力， 更能使半导体元件稳定的固定在 反上。
综上所述， 虽然结合以上较佳实施例揭露了本发明， 然而其并非用以限 定本发明。 本发明所属技术领域中熟悉此技术者， 在不脱离本发明的精神和 范围内， 可作各种的更动与润饰。 因此， 本发明的保护范围应以附上的权利 要求所界定的为准。

Claims

权利要求书
1.一种封装结构， 包括：
半导体元件 ( semiconductor device ), 具有至少一接塾；
第一保护层， 设置于该半导体元件上， 并暴露该接垫；
第二保护层， 设置于该第一保护层上， 且该第二保护层具有：
至少一第一开口， 暴露出该接垫的部分表面；
至少一第二开口， 暴露出该第一保护层的部分表面； 以及 至少一导电凸块， 相对该接垫设置于该笫二保护层上， 且该些导电凸块 通过该第一开口耦接于该接垫。
2. 如权利要求 1所述的封装结构， 其中该第二开口位于该导电凸块外， 该封装结构还包括：
基板， 通过该些导电凸块与该半导体元件接合； 以及
封胶， 填充于该基板与该第二保护层之间， 该封胶包覆该导电凸块且通 过该笫二开口与该第一保护层耦接。
3. 如权利要求 2所述的封装结构，其中该第二保护层具有多个第二开口， 该些第二开口以矩阵式排列。
4. 如权利要求 1所述的封装结构，其中该笫二开口位于该导电凸块的下 方， 该导电凸块通过该笫二开口与该第一保护层耦接。
5. 如权利要求 4所述的封装结构，其中该第二保护层具有多个第二开口， 该些第二开口以矩阵式排列。
6. 如权利要求 1所述的封装结构，其中该第二保护层具有至少两个笫二 开口， 其中之一该第二开口位于该导电凸块外， 其中之一该第二开口位于该 导电凸块的下方。
7. 如权利要求 1所述的封装结构， 其中该第二保护层为岛状。
8. 如权利要求 1所述的封装结构， 其中该笫一保护层具有多个开口， 该 第二保护层具有多个第一开口及多个第二开口， 且该些笫一开口及该些第二 开口的面积实质上大于该半导体元件的开口的面积。
9. 如权利要求 1所述的封装结构，其中该第一保护层的材料与该笫二保 护层的材料不同.。
10. 如权利要求 1所述的封装结构， 其中该第一保护层的材料硬度实质 上大于该第二保护层的材料硬度。
11. 如权利要求 1所述的封装结构， 其中该第一保护层的材料选自于硅 氮化物 （SiyNx )及硅氧化物（SiyOx )群组。
12. 如权利要求 1所述的封装结构， 其中该第二保护层的材料选自于苯 并环丁烷（benzocyclobutane, BCB )及聚亚醯胺 ( poly-imede, PI )群組。
13. 一种封装结构， 包括：
半导体元件， 具有至少一个接垫；
保护层， 设置于该半导体元件上并暴露出该接垫的部分表面； 多个凸块， 彼此分隔设置于该保护层上， 以暴露出部分的该保护层及该 接垫； 以及
至少一导电凸块， 相对该接垫设置于该些凸块及部分的该保护层上， 且 该些导电凸块鎬接于该接垫。
14. 如权利要求 13所述的封装结构， 还包括：
基板， 通过该些导电凸块与该半导体元件接合； 以及
封胶， 填充于该基板与保护层之间， 该封胶包覆该些导电凸块及该些凸 块。
15. 如权利要求 13所述的封装结构，其中该些凸块占该半导体元件的面 积与该半导体元件的面积的比值实质上界于 1% ~ 80%之间。
16. 如权利要求 13所述的封装结构，其中该些凸块的材料硬度实质上小 于该保护层的材利-硬度。
17. 如权利要求 13 所述的封装结构， 其中该保护层的材料为硅氮化物 ( SiNx X
18. 如权利要求 13所述的封装结构，其中该些凸块的材料选自于苯并环 丁烷（benzocyclobutane, BCB )及聚亚醯胺 ( poly-imede, PI )群组。
PCT/IB2009/006693 2009-09-01 2009-09-01 封装结构 WO2011027185A1 (zh)

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