TWI373831B - Package structure - Google Patents

Description

1373831

Sanda number: TW4116PA IX. Description of the invention: [Technical field to which the invention pertains] and particularly relates to a package structure having a package structure and a second protective layer. [Prior Art] Referring to Fig. 1, there is shown a schematic view of a conventional package having a secondary passivation layer. The general package structure 10 includes a semiconductor device 12, a passivation layer 14, a 22a, a plurality of solder bumps 18, a substrate 20, and an adhesive 22. The surface of the semiconductor component 12 has a plurality of pads 12a' for use as an end point for electrical connection. The surface of the semiconductor component 12 is further covered with a protective layer - a passivation layer ' and the passivation layer 14 is a portion of the exposed pad 12a. " Knife Since the general passivation layer 14 has a thin thickness, it is susceptible to cracking due to stress. Therefore, in recent years, the industry has developed a package structure for forming a secondary passivation layer on the purification layer 14 to avoid the problem that the passivation layer 14 is broken and the quality is lowered. The solder bumps 18 are connected to the semiconductor device 12 and the substrate 20 via the exposed portions of the pads 12a. The encapsulant 22 is filled between the substrate 20 and the secondary passivation layer 16 and is coated with a plurality of solder bumps is. However, since the area of the pad 12a has been reduced by less than 75 micrometers as the package volume is reduced, such a structure in which the passivation layer and the secondary passivation layer 16 are stacked further reduces the area of the exposed pad 12a. . Therefore, the area in which the solder bumps 18 are in contact with the pads 12a is also reduced by the secondary passivation layer. However, the stress between the solder bump 18 and the pad i2a will be contacted by the 6 1373831

" Sanda number: TW4116PA 'The area becomes smaller and larger, and cannot pass the subsequent trustworthy test (such as thermal cycle). That is, the bonding force between the solder bumps 18 and the pads 12a is increased due to the increase in stress, and the solder bumps 18 cannot be tightly bonded to the pads 12a. In addition, since the material of the secondary passivation layer 16 is softer and the bonding force of the encapsulant 22 is lower, the secondary passivation layer 16 cannot be firmly bonded to the encapsulant 22 or the solder bumps 18, so that the semiconductor device 12 cannot be It is stably fixed to the substrate 20. SUMMARY OF THE INVENTION The present invention relates to a package structure by increasing the area of the sealant and the conductive bumps coupled to the first protective layer, so that the sealant and the electrical bumps are interposed between the semiconductor components. The bonding force is increased, and the semiconductor element is firmly fixed to the substrate. According to one aspect of the present invention, a package structure is proposed, and the package structure includes a semiconductor component, a first protection layer, a second protection layer, and at least one conductive bump. The semiconductor component has at least one pad. The first protective layer is disposed on the semiconductor component and exposes the pads. The second protective layer is disposed on the first protective layer of φ, and the second protective layer has at least one first opening and at least one second opening. The first opening exposes a portion of the surface of the pad. Second opening. The mouth system exposes part of the surface of the first protective layer. The conductive bumps are disposed on the second protective layer, and the conductive bumps are coupled to the pads through the first openings. According to one aspect of the present invention, another package structure is proposed, the package structure comprising a semiconductor component, a protective layer, a plurality of bumps, and at least one conductive bump. The semiconductor component has at least one pad. The protective layer is disposed on the semiconductor component and exposes a portion of the surface of the pad. Several bump systems 7 1373831

Sanda number: TW4116PA 'separated from each other on the protective layer' to expose part of the protective layer and the interface. The at least one conductive bump is disposed opposite to the protective layer of the bump and the portion, and the conductive bumps are coupled to the pad. In order to make the above-mentioned contents of the present invention more comprehensible, the following detailed description of the preferred embodiment 'with the accompanying drawings' is as follows: [Embodiment] The first embodiment is shown in FIG. It shows a side view of a package structure in accordance with a first embodiment of the present invention. The package structure 10 includes a semiconductor device 1 1 , a first edge layer 120 , a second protection layer 13 , and at least one conductive bump 140 . The semiconductor device 11 has at least one pad 110a. The first protective layer 120 is disposed on the semiconductor device 11A and exposes the pads 11A. The second protective layer 130 is disposed on the first protective layer 120, and the second protective layer 130 has at least one first opening 13〇a and at least one first opening 130b. The first opening 13〇a exposes a portion of the surface of the contact layer 110a. The second opening 130b exposes a portion of the surface of the first protective layer 12'. The conductive bumps 140 are disposed on the second protective layer 130, and the conductive bumps 14 are transmitted through the first opening 13A. The plurality of conductive bumps 140 are coupled to the pads 11A. Here, in order to facilitate the description of the subsequent embodiments, a semiconductor element no having two pads 11a and two conductive bumps 140 will be described. In the present embodiment, the semiconductor element 11 is, for example, a wafer, and the semiconductor body element 110 has a plurality of pads 11a. The first protective layer 12 is disposed on the semiconductor device 110. The first protective layer 12 has an opening 120a and the opening 120a exposes a portion of the surface of the plurality of pads 11a. No. 8 1373831

The third protective layer 130 is disposed on the first protective layer 120 for buffering the stress on the first protective layer 120. In addition, the second protective layer 13 〇 corresponding pad 110 a has a plurality of first openings 13 〇 a, and exposes a part of the surface of the plurality of pads 。. In addition, the second protective layer 130 has one in this embodiment. The second opening 130b is located outside the conductive bump 140 and exposes a portion of the surface of the first protective layer 120. In the present embodiment, the thickness of the first protective layer 120 is, for example, less than 2 micrometers (ym), the first protection The thickness of the layer 130 is, for example, greater than £micron ("m), and the material of the first protective layer 12A is different from the material of the second protective layer 130, and the material hardness of the first protective layer 120 is substantially greater than the second protective layer. 130 material hardness. The material of the first protective layer 12 is, for example, selected from the group consisting of yttrium nitride (SiyNx) and yttrium oxide (Si〇x), and the more common one is ruthenium tetranitride (ShN4) or bismuth dioxide (Si). 〇 2). Further, the material of the second protective layer 13A is preferably a polymer, and benzocyclobutane (BCB) or polyp-imide (PI) or the like is common. The package structure 100 of this embodiment preferably further includes a substrate 15 and a glue. The substrate 150 is bonded to the semiconductor π-member 110 through the conductive bumps 14A. The sealant 160 is filled between the substrate 15 and the first protective layer . The sealant ribs are covered with the conductive bumps 140 and are lightly connected to the first protective layer through the second openings i3Gb. Since the material hardness of the second protective layer 13Q is small, the bonding strength between the sealant 160 and the second protective layer 13 is weak. Therefore, when the sealant 160 is coupled to the first protective layer 12A through the second opening 13〇b, the bonding force of the sealing member 16〇 to fix the semiconductor device 11〇 is increased, so that the semiconductor device 11 can be firmly stabilized. Combined with the substrate bo. In this embodiment, the substrate 15 can also be a lead frame, but not 9 1373831

Sanda number: TW4II6PA ϋΪ基Ϊ Μ0 is a lead frame, which can also be a glass substrate, a ruthenium substrate or a substrate of other materials. Referring to Figure 3, there is shown a plan view of a second protective layer in accordance with the package structure of Figure 2. Here, in order to clearly indicate the position of the first opening and the second opening 130b, the drawing of some of the elements is omitted for the subsequent explanation. Because the second protective layer 130 is used to buffer the stress of the first protective layer 12 ' and the sealing layer 160 is coupled to the first protective layer 12 透过 through the second opening _ to enhance the encapsulation 160 to fix the semiconductor device 11 〇 The combination of strength. In order to achieve the above-mentioned effects, the total area of the first opening 130a of the second protective layer 130 of the present embodiment and the area of the second opening 13〇1} are substantially larger than the opening i20a of the first protective layer 120. Preferably, the ratio of the area of the second opening 13 〇b to the area of the semiconductor element 110 is substantially between about 9% and 99%. . That is, an appropriate increase in the area of coupling with the first protective layer 120 between the ratios enables the substrate 15 to be firmly bonded to the semiconductor element 110. In addition, as shown in FIG. 2, the second opening 130b of the embodiment is disposed between the two conductive bumps 14b. In fact, the second opening 130b of the embodiment only needs to be located outside the conductive bump to make the sealing. The glue 16 can be joined to the first protective layer 13 through the second opening 130b to increase the bonding force of each other. Therefore, it is not necessary to limit the arrangement position and shape of the second opening 13〇b here. It is well known in the art that the method of arranging the conductive bumps 14A and the pads 110a of the present invention is not limited thereto. Second Embodiment The package structure disclosed in this embodiment differs from the package structure of the first embodiment mainly in the number of second openings 23〇b of the second protective layer 23〇, and the rest are not the same. Let me repeat. Please refer to Figure 4, which depicts 1373831

Sanda number: TW4116PA * A side view showing the package structure of the second embodiment of the present invention. In this embodiment, the second protective layer 230 has a plurality of first openings 230a and a plurality of second openings 230b outside the conductive bumps 140. The plurality of first openings 230a of the second protective layer 230 expose a portion of the surface of the pad 110a. The plurality of second openings 230b expose a portion of the surface of the first protective layer 120, and the sealant 160 is coupled to the first protective layer 120 through the plurality of second openings 230b to enhance the bonding force of the sealing member 160 to fix the semiconductor device 110. . Next, please refer to FIG. 5, which shows a top view of the second protective layer according to the package structure ® in FIG. 4. Similarly, the drawing portion portion elements are omitted for clearly indicating the second protective layer 230 for the subsequent description. In this embodiment, the second protective layer 230 has a plurality of second openings 230b, and the second openings 230b are arranged in a matrix. In the same manner as the first embodiment, in order to enable the second protective layer 230 to effectively buffer the stress on the first protective layer 120, the sealant 160 can be coupled to the first protective layer 120 by the second opening 230b to increase The total bonding force of the area of the first opening 230a of the second protective layer 230 of the present embodiment and the area of the second opening 230b is substantially greater than the opening 120a of the first protective layer 120, preferably the second. The ratio of the area of the opening 230b to the area of the semiconductor component 110 is preferably between 20% and 99%. However, the second openings 230b of this embodiment may be arranged in other ways, such as a staggered arrangement, in addition to the matrix arrangement. It is to be understood by those skilled in the art that the arrangement of the second openings 230b of the present embodiment is not limited to a matrix arrangement. Third Embodiment The package structure 300 disclosed in this embodiment is the same as the first embodiment 1373831

Sanda number: TW4116PA. The difference in the package structure 100 is mainly in the position of the second opening 330b of the second protective layer 330, and the rest will not be described again. Referring to Figure 6, there is shown a side view of a package structure in accordance with a third embodiment of the present invention. In this embodiment, the second protective layer 330 has a second opening 330b under the conductive bump 340, and the second opening 330b exposes a portion of the surface of the first protective layer 120. The conductive bumps 340 are disposed on the second protective layer 330, and the conductive bumps 340 are coupled to the pads 110a through the first openings 330a and through the second openings 330b and the first protective layer 120. Coupling. As a result, the bonding force between the conductive bumps 340 and the semiconductor device 110 can be effectively increased to stably fix the semiconductor device 110 on the substrate 150. Next, please refer to Fig. 7, which shows a plan view of the package structure according to Fig. 6. Similarly, some of the components of the package structure 300 are omitted for clearly indicating the second protective layer 330 for the subsequent description. In this embodiment, the second protective layer 330 has a second opening 330b under the conductive bumps 340. In addition, in order to enable the second protective layer 330 to effectively buffer the stress on the first protective layer 120, and the conductive bumps 340 can be coupled to the first protective layer 120 by the second opening φ port 330b to increase the fixed Binding force. Therefore, the total area of the first opening 330a of the second protective layer 330 of the present embodiment and the area of the second opening 330b are substantially larger than the opening 120a of the first protective layer 120, and the area of the preferred second opening 330b. The ratio of the area to the area of the semiconductor element 110 is preferably between 20% and 99%. . In addition, the second protective layer 330 of the embodiment is covered on the first protective layer 120. In addition, the second protective layer 330 may also be disposed on the first protective layer 120 in an island shape. Further, the second opening 330b may have a circular opening or a square opening or the like. Therefore, those skilled in the art can understand the 12th 1373831 of this embodiment.

The third protection number T W4 丨丨 6PA . . . The second protective layer 330 does not limit the shape of the arrangement and the shape and size of the second opening 330b. The fourth embodiment is different from the package structure 300 of the third embodiment, mainly in the number of the second openings 430b of the second protection layer 430, and the rest are not described again. . Referring to Figure 8, there is shown a side view of a package structure in accordance with a fourth embodiment of the present invention. In this embodiment, the second protective layer 430 has a second opening 430b under the number of conductive bumps 440, and the second opening 430b exposes a portion of the surface of the first protective layer 120. The conductive bumps 440 are disposed on the second protective layer 120, and the conductive bumps 440 are coupled to the pads 110a through the first openings 430a, and are transmitted through the plurality of second openings 430b and the first protection. Layer 120 is coupled. In this way, the bonding force between the conductive bumps 440 and the semiconductor element 110 can be effectively increased, so that the semiconductor device 110 can be stably fixed on the substrate 150. Next, please refer to Fig. 9, which shows a plan view of the package structure φ according to Fig. 8. Similarly, some of the components of the package structure 400 are omitted for clarity of the second protective layer 430 for subsequent description. The second protective layer 430 of this embodiment is disposed on the first protective layer 120 in an island shape. Therefore, the conductive bump 440 is not completely seated on the second protective layer 430, but is partially seated on the second protective layer 430 and partially seated on the first protective layer 120. In this way, the encapsulant 460 can be directly coupled to the first protective layer 120, and the bonding force between the substrate 150 and the semiconductor device 110 can also be enhanced. In addition, the second protective layer 430 has a plurality of second openings 430b under the conductive bumps 440, and the second openings 430b are arranged in a matrix, for example, 13 1373831

Sanda number: TW4I16PA 'column. As such, the conductive bumps 440 can be coupled to the first protective layer 120 by the plurality of second openings 430b to increase the bonding force between the conductive bumps 440 and the semiconductor device 110, so that the semiconductor device 110 is firmly It is fixed on the substrate 150. In addition, in the embodiment, an island-shaped second protective layer 430 is provided with a plurality of conductive bumps 440 at the same time. However, an island-shaped second protective layer 430 may also be provided with only one conductive bump 440. In addition, the conductive bumps 440 of the present embodiment are not completely seated on the second protective layer 430. However, the conductive bumps 440 may be completely seated on the island-shaped second protective layer 430. Similarly, in order to enable the second protective layer 430 to effectively buffer the stress on the first protective layer 120, and the conductive bumps 460 can be coupled to the first protective layer 120 by the second opening 430b to increase the fixed The combination of the area of the first opening 430a of the second protective layer 430 of the present embodiment and the area of the second opening 430b is substantially greater than the opening 120a of the first protective layer 120, preferably the second opening 430b. The ratio of the area to the area of the semiconductor component 110 is preferably between 20% and 99%. However, it will be apparent to those skilled in the art that the present invention is not limited to the embodiments described above. In this embodiment, the second protective layer 430 is disposed on the first protective layer 120 in an island shape as shown in FIG. 9, or may be covered on the first protective layer 120 as in the second protective layer 330 of FIG. on. In addition, the second openings 430b of the second protective layer 430 are arranged in a matrix pattern in this embodiment, or may be arranged in a non-matrix type, such as a staggered type or a spaced type. That is, the second protective layer 430 and the opening 430b thereof are disposed according to actual applications, and the shape of the second protective layer 430 is not limited thereto, and the position and number of the second openings 430b are not limited thereto. Opening shape. 14 1373831

* 达达编号号: TW4116PA: The fifth embodiment is different from the fourth embodiment in the package structure 500 disclosed in the embodiment, mainly in the position of the second opening 530b of the second protective layer 530, and the rest are the same. The details are not repeated here. Referring to Figure 10, there is shown a side view of a package structure in accordance with a fifth embodiment of the present invention. In this embodiment, the second protective layer 530 has at least two second openings 530b, one of the second openings 530b is located outside the conductive bumps 540, and one of the second openings 530b is located below the conductive bumps 540. In this way, both the encapsulant 560 and the conductive bumps 540 can be coupled to the first protective layer 120 via the second opening 530b, so that the semiconductor device 110 is stably fixed on the substrate. Please refer to FIG. 10 and FIG. 11 at the same time. FIG. 11 is a top view of the conductive bumps of the package structure according to FIG. Similarly, some of the components of the package structure 500 are omitted for clarity of the conductive bumps 540 in FIG. 11 for subsequent description. In this embodiment, the second protective layer 530 has a plurality of second openings 530b arranged in a matrix, wherein a portion of the second openings 530b are located under the conductive bumps 540, and a portion of the second openings 530b φ are electrically conductive. The bump 540 is outside. Further, the conductive bumps 540 are arranged in an interlaced manner in this embodiment, but are not limited to such an arrangement method, and may be arranged in other manners. Similarly, in order to enable the second protective layer 530 to effectively buffer the stress of the first protective layer 120, the conductive bumps 540 and the sealant 560 can be coupled to the first protective layer 120 by the second opening 530b. The total bonding force of the second opening 530a of the second protective layer 530 of the present embodiment is substantially greater than the opening 120a of the first protective layer 120, preferably the second. The ratio of the area of the opening 530b to the area of the semiconductor 15 1373831 three-numbered: TW4116PA element 110 is preferably between 20% and 99%. In addition, the second protective layer 530 of the present embodiment is covered on the first protective layer 120. In addition, the second protective layer 53 can also be disposed on the first protective layer 120 in an island shape. Further, the second opening σ 53Qb may be in the form of a square opening or the like in addition to the mouth. Therefore, it is well known that the second protective layer 53 of this embodiment does not limit the shape and size of the two openings 530b. The singularity and the sixth embodiment of the package structure disclosed in the present embodiment are different in that the main difference is that a plurality of bumps 63 〇 are applied to the cover layer, and the rest are No longer. BRIEF DESCRIPTION OF THE DRAWINGS Referring to Figure 12, there is shown a side view of a sixth embodiment of the present invention. The package structure 6A includes a semiconductor device. The s-layer 620, the plurality of bumps 630, and the at least one conductive bump 610 have at least one pad 61A. The protective layer is partially disposed on the semiconductor element 610 and exposed to the pad 610a. The bumps 630 are disposed on the protective layer 62A from each other. A plurality of protective layers 620 and pads 610a. The at least one conductive bump 64 is disposed on the bump 630 and a portion of the protective layer 62f and the conductive bumps 640 are coupled to the pad 610a. In the present embodiment, the bump 630 is disposed on the protective layer 620 to buffer the stress of the protective layer. In addition, the bump 63 位于 under the conductive bump 640 has a double opening 630a' to electrically connect the conductive bump through the opening 630a. The bumps 630 are spaced apart from each other and disposed on the protective layer 62〇6l〇a to expose a portion of the surface of the protective layer 620. On 1373831

Sanda number: TW41I6PA: In this embodiment, the thickness of the protective layer 620 is, for example, less than 2 micrometers (//m), and the thickness of the bumps 630 is, for example, greater than 2 micrometers (//m), and the material of the protective layer 620 is Different from the material of the bump 630, the material hardness of the protective layer 620 is substantially greater than the material hardness of the bump 630. The material of the protective layer 620 is yttrium nitride (SiNx), and the material of the bump 630 is preferably a polymer, and benzocyclobutane (BCB) or poly-liminamide (poly-) is common. Imide, PI), etc. In this embodiment, the package substrate 600 further includes a substrate 650 and a glue 660. The substrate 650 is bonded to the semiconductor element 610 through the conductive bumps 640. The sealant 660 is filled between the substrate 650 and the protective layer 620. The sealant 660 covers the conductive bumps 640 and the bumps 630. Since the material hardness of the bump 630 is small, the bonding force between the sealant 660 and the conductive bump 640 and the bump 630 is weak. Therefore, when the sealant 660 and the conductive bump 640 are coupled to the bump 630 and the protective layer 620 at the same time, the bonding force of the sealant 660 and the conductive bump 640 to fix the semiconductor component 610 is enhanced. In this way, the semiconductor element 610 can be firmly fixed to the substrate 650. • In addition, please refer to Fig. 13 for a view of the protective layer and the bumps in accordance with the package structure in Fig. 12. Here, some of the components of the package structure 600 are omitted for the purpose of clearly indicating the configuration of the bumps 630. For the convenience of the following description. Because the bumps 630 are disposed to buffer the stress on the protective layer 620, the area of the bumps 630 that is not disposed in the embodiment is substantially larger than the opening 620a of the protective layer 620, preferably the bumps. The ratio of the area of the semiconductor element 610 to the area of the semiconductor element 610 is substantially between 1% and 80%. In addition, in the present embodiment, the bumps 630 are arranged in a matrix in the form of 1373831.

Sanda number: TW4116PA On the cover layer, the arrangement method of the bumps 630 is not limited to this, and the arrangement method such as staggered arrangement may be used. Further, the bumps 630a of the present embodiment may be, for example, island-like structures and circular bumps, and may be square-shaped bumps, and it is obvious to those skilled in the art that the present invention is not limited thereto. The package structure disclosed in the above embodiments of the present invention increases the area where the conductive bumps and/or the sealant are coupled to the first protective layer to increase the bonding force between the conductive bumps and/or the sealant and the semiconductor component. In this way, not only the second protective layer or the bump can effectively buffer the stress applied to the first protective layer, but also the semiconductor element can be stably fixed on the substrate. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1373831 三达号: TW4116PA [Simple description of the drawings] Fig. 1 is a conventional diagram; FIG. 2 is a schematic view showing a package structure of a second passivation layer according to the present invention, and a side view of the package structure of the embodiment is 3 FIG. 4 is a second side view of the second protective layer of the package structure in FIG. 2, and FIG. 5 is a side view of the second embodiment of the present invention; FIG. 6 is a side view showing the third embodiment of the present invention according to the second embodiment of the present invention; FIG. 8 is a view showing a fourth embodiment of the present invention; The side view shows the side view of the package structure according to FIG. 8; the view ISI · the circumference, the first figure shows the conductive protrusion of the package structure of the side of the package structure according to the fifth embodiment of the fifth embodiment of the present invention. Above view of the block; jT and 12 are not shown on the side of the package structure of the sixth embodiment of the present invention. FIG. 13 is a protective layer and a bump 1373831 according to the package structure in FIG.

Sanda number: TW4116PA: [Description of main component symbols] 10, 100, 200, 300, 400, 500, 600: package structure 12, 110, 610: semiconductor components 12a, 110a, 610a: pads 14: purification layer 16: Secondary passivation layer 18: solder bumps 20, 150, 650: substrate 22, 160, 460, 560, 660: sealant ~ 120: first protective layer 120a, 620a: openings 130, 230, 330, 430, 530: Second protective layer 130a, 230a, 330a, 430a, 530a: first opening 130b, 230b, 330b, 430b, 530b: second opening 140, 340, 440, 540, 640: conductive bump 620: protective layer 630: convex Block φ 630a : opening

Claims (1)

1101 June 2012/6/19_la Application & Amendment 10, Patent Application Range: h A package structure comprising: a semiconductor device having at least one pad; a first protective layer disposed on the semiconductor And the second protective layer is disposed on the first protective layer, and the second protective layer has: at least one first opening 'exposing the surface of the pad; at least one second Opening, exposing a surface of the first protective layer; and forming at least one conductive bump on each of the pads, wherein the first opening and the second opening are located below the conductive bump, the conductive bump The conductive bump is coupled to the first protective layer through the second opening by being lightly connected to the pad through the first opening. 2. The package structure of claim 2, further comprising: a substrate through which the conductive bump is bonded; and a glue filled between the substrate and the second protective layer, The sealant coats the conductive bumps. 3. The package structure of claim 1, wherein the second protective layer has a plurality of second openings, the second openings being arranged in a matrix. 4. The package structure of claim 1, wherein the second protective layer has at least two second openings, one of the second openings being located outside the conductive bumps, and the other of the second The opening is located below the conductive bump, and the conductive bump passes through the second opening and the first protection 1013229573-0 097106232 1373831 i June 19, 2010 nuclear replacement page 2012/6/19_lsl Shen Fu &; Correct the sheath coupling. 5. The package structure of claim 4, further comprising: a substrate through which the conductive bump is bonded; and a glue filled between the substrate and the second protective layer, The encapsulant encapsulates the conductive bump and is coupled to the first protective layer through a second opening located outside the conductive bump. 6. The package structure of claim 5, wherein the second protective layer has a plurality of second openings outside the conductive bumps, the second openings being arranged in a matrix. 7. The package structure of claim 1, wherein the first protective layer has a plurality of openings, the second protective layer has a plurality of first openings and a plurality of second openings, and the first openings And the total area of the second openings is substantially greater than the total area of the openings of the half of the conductor elements. 8. The package structure of claim 1, wherein the material of the first protective layer is different from the material of the second protective layer. 9. The package structure of claim 1, wherein the material hardness of the first protective layer is substantially greater than the material hardness of the second protective layer. 10. The package structure of claim 1, wherein the material of the first protective layer is tantalum nitride (SiyNx) or tantalum oxide (SiA). 11. The package structure of claim 1, wherein the material of the second protective layer is benzocyclobutane (BCB) or poly-imide (PI). 12. A package structure comprising: a semiconductor component having at least one pad; 097106232 1013229573-0 22 T ^73831 ιοί 〇 ΐ ΐ 曰 9曰 正 杂 2012 2012 2012/6/丨9_丨8 Shen Fu & Correcting a protective layer disposed on the semiconductor device and exposing a surface of the pad; a plurality of bumps disposed on the protective layer to cover a portion of the protective layer; and at least one conductive bump The conductive bump covers the entire surface of the at least one bump, and the conductive bump is coupled to the pad and the protective layer. The conductive bump covers the entire surface of the bump and the bump. 13. The package structure of claim 12, further comprising: a substrate 'bonding to the semiconductor component through the conductive bump; and a sealant filling the substrate and the protective layer, the sealant The conductive bumps (4) are covered with the bumps of the protective layer. 14. The entire package is disclosed in the package structure of claim 12, wherein the ratio of the bumps to the surface of the semiconductor element is between 1% and 80%. The square bS is a package structure as described in Patent No. 12, wherein the mi-degree field cuts the hardness of the material. The package structure described in item 12 of the ==, where frUt nitride (8 (4) or Wei (4)).如. As claimed in the patent scope, the materials of the bumps are stupid and ring τα. Where B(8) or polyamidoline 097106232 1013229573-0 23