WO2011024598A1 - 電力増幅回路ならびにそれを用いた送信装置および通信装置 - Google Patents
電力増幅回路ならびにそれを用いた送信装置および通信装置 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/108—A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
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- the present invention relates to a power amplification circuit used for amplification of a transmission signal in a wireless communication device or the like, and in particular, a power amplification circuit capable of amplifying a signal having an envelope variation with high power added efficiency and the same
- the present invention relates to a transmission device and a communication device used.
- LINC Linear Amplification with Nonlinear Component
- the above-described conventional LINC power amplifier circuit has a problem that the power added efficiency of the power amplifier circuit decreases when the amplitude of the input signal decreases.
- the present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a power amplifier circuit in which a decrease in power added efficiency due to a decrease in the amplitude of an input signal is reduced, and the power amplifier circuit. Another object is to provide a transmission device and a communication device using the above.
- the first power amplifier circuit converts an input signal having an envelope variation into first and second constant envelope signals having a phase difference that increases or decreases inversely with an increase or decrease in amplitude of the input signal.
- a constant envelope signal generation circuit for outputting, and a first transistor in which the first constant envelope signal is input to a source terminal and a signal in phase with the second constant envelope signal is input to a gate terminal;
- a second transistor in which the second constant envelope signal is input to the source terminal and a signal in phase with the first constant envelope signal is input to the gate terminal; and a drain terminal of the first transistor
- a first variable gain amplifier that amplifies and outputs a signal output from the source terminal, the source terminal is connected to the reference potential, the drain terminal is connected to the power supply potential via the first low-pass filter, and the gate Before the terminal
- a third transistor to which an output signal of the first variable gain amplifier is input and an output signal from the drain terminal is output via an output matching circuit; and a part of the input signal is input to the input
- a second variable gain amplifier that amplifies and outputs a signal output from the drain terminal of the second transistor, and a source terminal
- the drain terminal is connected to the power supply potential via the second low-pass filter, and the output signal of the second variable gain amplifier is input to the gate terminal.
- a fourth transistor that outputs an output signal via the output matching circuit, wherein the gain control circuit includes the first and second variable when the amplitude of the input signal is smaller than a predetermined value.
- a gain control signal for controlling the first and second variable gain amplifiers is output so that the gain of the gain amplifier is increased.
- the transmission device of the present invention is characterized in that an antenna is connected to the transmission circuit via the power amplification circuit having the above-described configuration.
- the communication device of the present invention is characterized in that an antenna is connected to the transmission circuit via the power amplifier circuit having the above-described configuration, and a reception circuit is connected to the antenna.
- the power amplifier circuit of the present invention a power amplifier circuit with low power consumption and high power added efficiency can be obtained.
- FIG. 1 is a block diagram schematically showing a power amplifier circuit of a first example of an embodiment of the present invention. It is a circuit diagram which shows typically an example of the constant envelope signal generation circuit in FIG. It is a block diagram which shows typically the power amplifier circuit of the 2nd example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 3rd example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 4th example of embodiment of this invention.
- (A) is a graph which shows the simulation result of the electrical property of the power amplifier circuit of a comparative example
- (b) is a graph which shows the simulation result of the electrical property of the power amplifier circuit of the 2nd example of embodiment of this invention. It is.
- FIG. 1 is a circuit diagram showing a power amplifier circuit of a first example of an embodiment of the present invention.
- FIG. 2 is a circuit diagram showing an example of the constant envelope signal generation circuit of FIG.
- the power amplifier circuit of this example includes an input terminal 39, a constant envelope signal generation circuit 100, a first transistor 11, a second transistor 12, and a first variable gain amplifier 21.
- the constant envelope signal generation circuit 100 includes a first constant envelope signal having a phase difference that increases or decreases an input signal having an envelope variation input from the input terminal 39 in reverse to the increase or decrease of the amplitude of the input signal. 2 is converted into a constant envelope signal and output.
- the first constant envelope signal is input to the source terminal, and the second constant envelope signal is input to the gate terminal.
- the second constant envelope signal is input to the source terminal and the first constant envelope signal is input to the gate terminal.
- the first variable gain amplifier 21 amplifies and outputs a signal output from the drain terminal of the first transistor 11.
- the third transistor 13 has a source terminal connected to the reference potential (ground potential), a drain terminal connected to the power supply potential via the first low-pass filter 32, and a gate terminal connected to the first potential.
- the output signal of the variable gain amplifier 21 is input, and the output signal from the drain terminal is output via the output matching circuit 37.
- the first low-pass filter 32 is for preventing the outflow of a high-frequency signal, and is composed of an inductor.
- the first low-pass filter 32 has one end connected to the drain terminal of the third transistor 13 via the harmonic matching circuit 34a and the other end connected to the power supply potential Vdd.
- the output matching circuit 37 has one end connected to the drain terminal of the third transistor 13 and the harmonic matching circuit 34a via the capacitor 36a, and the other end connected to the output terminal 38.
- the first to third transistors 11 to 13 are all n-channel FETs, and the pinch-off voltage (threshold voltage for flowing a drain current) is Vp.
- the output matching circuit 37 matches the impedance of the third transistor 13 as viewed from the drain terminal of the third transistor 13 with the fundamental wave.
- the harmonic matching circuit 34a sets the impedance to be short-circuited with the even-order harmonics of the fundamental wave and open with the odd-order harmonics of the fundamental wave. For this reason, the third transistor 13 is configured to operate in class F. In the case where the third transistor 13 is not operated in class F, the harmonic matching circuit 34a is not necessary.
- the capacitor 36a is a DC blocking capacitor.
- the drain terminal of the second transistor 12 is terminated with a predetermined impedance (not shown), the drain terminal of the second transistor 12 is connected to the input terminal of the first variable gain amplifier 21 in some cases. It doesn't matter. Further, the output signal from the drain terminal of the second transistor 12 may be used in another circuit.
- the first and second transistors 11 and 12 form a transfer gate circuit, and the first transistor 11 is turned on only when the voltage of the second constant envelope signal is larger than Von. Pass the first constant envelope signal.
- the third transistor 13 is turned on only during a period in which both the first constant envelope signal and the second constant envelope signal are greater than Von. Therefore, compared with the case where the first constant envelope signal is applied to the gate terminal of the third transistor 13 as it is, the period during which the third transistor 13 is in the ON state is shortened, so that the power consumption is reduced. , Power supply efficiency (ratio of output power to power supplied from the constant voltage power supply Vdd) is improved. As a result, a power amplifier circuit with high power added efficiency can be obtained.
- the drain voltage of the third transistor 13 also includes a fundamental wave component. Therefore, the fundamental component is extracted from the drain voltage of the third transistor 13 by the output matching circuit 37 and output from the output terminal 38.
- the amplitude of the output signal from the output terminal 38 increases and decreases as the first constant envelope signal and the second constant envelope signal both increase and decrease over a period greater than Von, so the first constant envelope signal and the second constant envelope signal It increases or decreases in reverse to the increase or decrease of the phase difference of the constant envelope signal. That is, the output signal from the output terminal 38 has an amplitude that increases / decreases in accordance with the increase / decrease of the amplitude of the input signal, and the input signal is amplified.
- the gain control circuit 40 includes a mixer 41, a first addition circuit 42, and a second addition circuit 43.
- the mixer 41 receives a part of the input signal and outputs an amplitude detection signal having a DC voltage corresponding to the amplitude of the input signal.
- the first adder circuit 42 receives the reference signal Vref having a predetermined DC voltage and the amplitude detection signal from the mixer 41, and has a gain control basic signal having a voltage obtained by subtracting the voltage of the amplitude detection signal from the voltage of the reference signal Vref. Is output. When the voltage of the amplitude detection signal is larger than the voltage of the reference signal Vref, the voltage of the gain control basic signal is zero.
- the second adder circuit receives the reference signal Vst having a predetermined DC voltage and the gain control basic signal from the first adder circuit, and adds the voltage of the reference signal Vst and the voltage of the gain control basic signal.
- a gain control signal having a voltage is output. Therefore, the DC voltage of the gain control signal increases when the amplitude of the input signal is smaller than a predetermined value, and the increase amount increases or decreases opposite to the increase or decrease of the amplitude of the input signal.
- the gain of the first variable gain amplifier 21 increases when the amplitude of the input signal is smaller than a predetermined value, and the amount of increase is increased.
- the gain of the first variable gain amplifier 21 can be controlled so as to increase or decrease contrary to the increase or decrease of the amplitude of the input signal.
- the amplitude of the input signal at which the gain of the first variable gain amplifier 21 starts to increase can be determined by the DC voltage of the reference signal Vref input to the first adder circuit 42.
- the phase difference between the first constant envelope signal and the second constant envelope signal increases. Since the first constant envelope signal and the second constant envelope signal are not perfect rectangular signals, the phase difference between the first constant envelope signal and the second constant envelope signal increases as the phase difference between the first constant envelope signal and the second constant envelope signal increases. The amplitude of the signal passing through the transfer gate circuit constituted by the first transistor 11 and the second transistor 12 is reduced. Therefore, when the first variable gain amplifier 21 is not provided, there arises a problem that the third transistor 13 cannot be turned on.
- the detection circuit of the present example having the above-described configuration, when the amplitude of the input signal is smaller than a predetermined value, the gain of the first variable gain amplifier 21 is increased and the third transistor 13 is connected to the gate terminal.
- the voltage of the input signal can be increased.
- the power amplifying circuit of this example it is possible to obtain a power amplifying circuit in which the power added efficiency is high and the decrease in power added efficiency due to the amplitude of the input signal is reduced.
- FIG. 2 is a circuit diagram showing an example of the constant envelope signal generation circuit 100 in FIG.
- the constant envelope signal generation circuit 100 includes a phase shifter 102, a variable gain amplifier 104, an adder circuit 106, a phase shifter 110, an adder circuit 108, a mixer 116, and a mixer 118.
- the phase shifter 102 advances the phase of the input signal Sin by ⁇ / 2 and outputs it.
- the variable gain amplifier 104 amplifies the output signal of the phase shifter 102 and generates the first signal e.
- the adder circuit 106 generates a first constant envelope signal S1 by vector addition of the first signal e and the input signal Sin.
- the phase shifter 110 delays the first signal e by ⁇ and generates the second signal ⁇ e.
- the adder circuit 108 generates a second constant envelope signal S2 by vector addition of the second signal -e and the input signal Sin.
- the mixer 116 outputs a signal having a voltage corresponding to the amplitude (specifically, the square of the amplitude) of the first constant envelope signal S1.
- the mixer 118 outputs a signal having a voltage corresponding to the amplitude (specifically, the square of the amplitude) of the second constant envelope signal S2.
- the adder circuit 120 adds the output signals of the mixers 116 and 118 and outputs the result.
- the adder circuit 114 generates a signal having a voltage difference between the voltage of the output signal of the adder circuit 120 and the predetermined voltage Vref.
- the output signal of the adder circuit 114 is input as a gain control signal to the variable gain amplifier 104 via the low-pass filter 112 and a buffer amplifier (not shown).
- the gain of the variable gain amplifier 104 is feedback-controlled so that the sum of squares of the amplitudes of the first constant envelope signal S1 and the second constant envelope signal S2 becomes a constant value.
- the envelope signal S1 and the second constant envelope signal S2 are constant envelope signals in which the phase difference between the envelope signal S1 and the second constant envelope signal S2 increases or decreases opposite to the increase or decrease of the input signal.
- FIG. 3 is a circuit diagram showing a power amplifier circuit according to a second example of the embodiment of the present invention.
- differences from the power amplifier circuit of the first example of the above-described embodiment will be described, and the same constituent elements will be denoted by the same reference numerals and redundant description will be omitted.
- the power amplifier circuit of the present example includes a second variable gain amplifier 22, a fourth transistor 14, a second low-pass filter 33, a harmonic matching circuit 34b, and a capacitor 36b. And further.
- the second variable gain amplifier 22 amplifies and outputs a signal output from the drain terminal of the second transistor 12.
- the fourth transistor 14 has a source terminal connected to the reference potential (ground potential), a drain terminal connected to the power supply potential via the second low-pass filter 33, and a gate terminal connected to the second variable gain.
- the output signal of the amplifier 22 is input, and the output signal from the drain terminal is output via the output matching circuit 37.
- the second low-pass filter 33 is for preventing outflow of a high-frequency signal, and is composed of an inductor.
- the second low-pass filter 33 has one end connected to the drain terminal of the fourth transistor 14 via the harmonic matching circuit 34 and the other end connected to the power supply potential Vdd.
- the harmonic matching circuit 34b sets the impedance to be short-circuited with the even-order harmonics of the fundamental wave and open with the odd-order harmonics of the fundamental wave. For this reason, the fourth transistor 14 is configured to operate in class F. Note that the harmonic matching circuit 34b is not necessary when the fourth transistor 14 is not operated in class F.
- the capacitor 36b is a direct current blocking capacitor.
- the output matching circuit 37 in this example matches the impedance viewed from the drain terminal of the third transistor 13 to the output terminal 38 side and the impedance viewed from the drain terminal of the fourth transistor 14 to the output terminal 38 with a fundamental wave.
- the fourth transistor 14 is an n-channel FET, and its pinch-off voltage (threshold voltage for flowing drain current) is Vp.
- the first and second transistors 11 and 12 form a transfer gate circuit, and the second transistor 12 is turned on only when the voltage of the first constant envelope signal is larger than Von, and the second transistor 12 is turned on. Pass the constant envelope signal.
- the fourth transistor 14 is turned on only during a period in which both the first constant envelope signal and the second constant envelope signal are greater than Von. Therefore, compared with the case where the second constant envelope signal is applied to the gate terminal of the fourth transistor 14 as it is, the period during which the fourth transistor 14 is in the ON state is shortened, so that the power consumption is reduced.
- the power supply efficiency (the ratio of the output power to the power supplied from the constant voltage power supply Vdd) is improved. As a result, a power amplifier circuit with high power added efficiency can be obtained.
- the drain voltages of the third transistor 13 and the fourth transistor 14 also include a fundamental wave component. Therefore, the output matching circuit 37 extracts the fundamental wave component from the drain voltages of the third transistor 13 and the fourth transistor 14, and the basic signal of the combined signal of the first constant envelope signal and the second constant envelope signal. The wave component is output from the output terminal 38.
- the amplitude of the output signal from the output terminal 38 increases and decreases as the first constant envelope signal and the second constant envelope signal both increase and decrease over a period greater than Von, so the first constant envelope signal and the second constant envelope signal It increases or decreases in reverse to the increase or decrease of the phase difference of the constant envelope signal. That is, the output signal from the output terminal 38 has an amplitude that increases or decreases in accordance with the increase or decrease of the amplitude of the input signal, and is an amplified input signal.
- the power amplifier circuit of this example controls the gains of the first and second variable gain amplifiers 21 and 22 using the above-described gain control signal, so that when the amplitude of the input signal is smaller than a predetermined value, The gains of the first and second variable gain amplifiers 21 and 22 can be increased, and the voltage of the signal input to the gate terminals of the third and fourth transistors 13 and 14 can be increased. As a result, the occurrence of the problem that the third transistor 13 and the fourth transistor 14 cannot be turned on when the amplitude of the input signal becomes small can be reduced. Decreasing problems can be improved. Therefore, according to the power amplifying circuit of this example, it is possible to obtain a power amplifying circuit in which the power added efficiency is high and the decrease in the power added efficiency due to the amplitude of the input signal is reduced.
- FIG. 4 is a block diagram showing a transmission apparatus according to a third example of the embodiment of the present invention.
- an antenna 82 is connected to a transmission circuit 81 via a power amplification circuit 70 shown in FIG. 1 is connected to the transmission circuit 81 and the output terminal 38 is connected to the antenna 82.
- the transmission signal having the envelope fluctuation output from the transmission circuit 81 is amplified using the power amplification circuit 70 with low power consumption and high power addition efficiency. Therefore, it is possible to obtain a transmission apparatus with low power consumption and a long transmission time.
- FIG. 5 is a block diagram showing a communication apparatus according to a fourth example of the embodiment of the present invention.
- an antenna 82 is connected to the transmission circuit 81 via the power amplification circuit 70 shown in FIG. 1, and a reception circuit 83 is connected to the antenna 82.
- An antenna sharing circuit 84 is inserted between the antenna 82 and the transmission circuit 81 and the reception circuit 83. 1 is connected to the transmission circuit 81 and the output terminal 38 is connected to the antenna 82.
- the transmission signal having the envelope variation output from the transmission circuit 81 is amplified using the power amplification circuit 70 with low power consumption and high power addition efficiency. Therefore, it is possible to obtain a transmission apparatus with low power consumption and a long transmission time.
- the electrical characteristics in the power amplifier circuit of the second example of the embodiment of the present invention shown in FIG. 3 were calculated by circuit simulation. All transistors were n-channel MOSFETs, the power supply voltage was 1.5 V, and the frequency of the input signal was 850 MHz.
- FIG. 6A shows a simulation result of the power amplifier circuit of the comparative example in which the gain control circuit 40, the first variable gain amplifier 21, and the second variable gain amplifier 22 are removed from the power amplifier circuit shown in FIG. Show. 6A and 6B, the horizontal axis represents the power of the input signal, and the vertical axis represents the power added efficiency of the power amplifier circuit.
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Abstract
Description
図1は本発明の実施の形態の第1の例の電力増幅回路を示す回路図である。図2は図1の定包絡線信号生成回路の一例を示す回路図である。
図3は本発明の実施の形態の第2の例の電力増幅回路を示す回路図である。なお、本例においては、前述した実施の形態の第1の例の電力増幅回路と異なる点について説明し、同一の構成要素には同一の参照符号を付して重複する説明を省略する。
図4は本発明の実施の形態の第3の例の送信装置を示すブロック図である。本例の送信装置は、図4に示すように、送信回路81に図1に示す電力増幅回路70を介してアンテナ82が接続されている。なお、図1に示す増幅回路70の入力端子39が送信回路81に接続されるとともに出力端子38がアンテナ82に接続されている。このような構成を有する本例の送信装置によれば、送信回路81から出力された包絡線変動を有する送信信号を、消費電力が小さく電力付加効率が高い電力増幅回路70を用いて増幅することができるので、消費電力が小さく送信時間が長い送信装置を得ることができる。
図5は本発明の実施の形態の第4の例の通信装置を示すブロック図である。本例の通信装置は、図5に示すように、送信回路81に図1に示す電力増幅回路70を介してアンテナ82が接続されており、アンテナ82に受信回路83が接続されている。また、アンテナ82と送信回路81および受信回路83との間にはアンテナ共用回路84が挿入されている。なお、図1に示す増幅回路70の入力端子39が送信回路81に接続されるとともに出力端子38がアンテナ82に接続されている。このような構成を有する本例の通信装置によれば、送信回路81から出力された包絡線変動を有する送信信号を、消費電力が小さく電力付加効率が高い電力増幅回路70を用いて増幅することができるので、消費電力が小さく送信時間が長い送信装置を得ることができる。
12:第2のトランジスタ
13:第3のトランジスタ
14:第4のトランジスタ
21:第1の可変利得増幅器
22:第2の可変利得増幅器
32:第1の低域通過フィルタ
33:第2の低域通過フィルタ
37:出力整合回路
38:出力端子
40:利得制御回路
70:電力増幅回路
81:送信回路
82:アンテナ
83:受信回路
100:定包絡線信号生成回路
Claims (4)
- 包絡線変動を有する入力信号を、該入力信号の振幅の増減と逆に増減する位相差を有する第1および第2の定包絡線信号に変換して出力する定包絡線信号生成回路と、
ソース端子に前記第1の定包絡線信号が入力されるとともにゲート端子に前記第2の定包絡線信号と同相の信号が入力される第1のトランジスタと、
ソース端子に前記第2の定包絡線信号が入力されるとともにゲート端子に前記第1の定包絡線信号と同相の信号が入力される第2のトランジスタと、
前記第1のトランジスタのドレイン端子から出力される信号を増幅して出力する第1の可変利得増幅器と、
ソース端子が基準電位に接続され、ドレイン端子が第1の低域通過フィルタを介して電源電位に接続されるとともに、ゲート端子に前記第1の可変利得増幅器の出力信号が入力されて、前記ドレイン端子からの出力信号が出力整合回路を介して出力される第3のトランジスタと、
前記入力信号の一部が入力されて、前記入力信号の振幅が所定の値より小さいときに前記第1の可変利得増幅器の利得が増加するように前記第1の可変利得増幅器を制御する利得制御信号を出力する利得制御回路とを備えることを特徴とする電力増幅回路。 - 前記第2のトランジスタのドレイン端子から出力される信号を増幅して出力する第2の可変利得増幅器と、
ソース端子が基準電位に接続され、ドレイン端子が第2の低域通過フィルタを介して電源電位に接続されるとともに、ゲート端子に前記第2の可変利得増幅器の出力信号が入力されて、前記ドレイン端子からの出力信号が前記出力整合回路を介して出力される第4のトランジスタとをさらに備え、
前記利得制御回路は、前記入力信号の振幅が所定の値より小さいときに前記第1および前記第2の可変利得増幅器の利得が増加するように前記第1および前記第2の可変利得増幅器を制御する利得制御信号を出力することを特徴とする電力増幅回路。 - 送信回路に請求項1または請求項2に記載の電力増幅回路を介してアンテナが接続されていることを特徴とする送信装置。
- 送信回路に請求項1または請求項2に記載の電力増幅回路を介してアンテナが接続されており、該アンテナに受信回路が接続されていることを特徴とする通信装置。
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JP2011528718A JPWO2011024598A1 (ja) | 2009-08-27 | 2010-07-29 | 電力増幅回路ならびにそれを用いた送信装置および通信装置 |
US13/392,080 US20120157010A1 (en) | 2009-08-27 | 2010-07-29 | Electrical Power Amplifier Circuit, and Transmission Device and Communication Device Using the Same |
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JP2009-196316 | 2009-08-27 | ||
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PCT/JP2010/062820 WO2011024598A1 (ja) | 2009-08-27 | 2010-07-29 | 電力増幅回路ならびにそれを用いた送信装置および通信装置 |
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US (1) | US20120157010A1 (ja) |
JP (1) | JPWO2011024598A1 (ja) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014158179A (ja) * | 2013-02-15 | 2014-08-28 | Harada Ind Co Ltd | アンプ装置 |
US9531086B1 (en) | 2016-01-06 | 2016-12-27 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5589887B2 (ja) * | 2011-02-17 | 2014-09-17 | 富士通株式会社 | 増幅回路、送信機及び増幅回路制御方法 |
DE112012006242T5 (de) * | 2012-04-19 | 2014-12-31 | Intel Corporation | Ein Signalverstärker mit aktivem Energiemanagement |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007096410A (ja) * | 2005-09-27 | 2007-04-12 | Interchip Kk | パルス信号発生器及びクロック信号発生器 |
JP2007300400A (ja) * | 2006-04-28 | 2007-11-15 | Matsushita Electric Ind Co Ltd | 送信回路、送信方法、及びそれを用いた通信機器 |
WO2008044268A1 (fr) * | 2006-10-05 | 2008-04-17 | Panasonic Corporation | Appareil et procédé de transmission |
JP2009182906A (ja) * | 2008-01-31 | 2009-08-13 | Kyocera Corp | 増幅器 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003298357A (ja) * | 2002-03-29 | 2003-10-17 | Shimada Phys & Chem Ind Co Ltd | 電力増幅方法および電力増幅器 |
JP2006333167A (ja) * | 2005-05-27 | 2006-12-07 | Japan Radio Co Ltd | 高周波増幅回路 |
-
2010
- 2010-07-29 JP JP2011528718A patent/JPWO2011024598A1/ja active Pending
- 2010-07-29 WO PCT/JP2010/062820 patent/WO2011024598A1/ja active Application Filing
- 2010-07-29 US US13/392,080 patent/US20120157010A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007096410A (ja) * | 2005-09-27 | 2007-04-12 | Interchip Kk | パルス信号発生器及びクロック信号発生器 |
JP2007300400A (ja) * | 2006-04-28 | 2007-11-15 | Matsushita Electric Ind Co Ltd | 送信回路、送信方法、及びそれを用いた通信機器 |
WO2008044268A1 (fr) * | 2006-10-05 | 2008-04-17 | Panasonic Corporation | Appareil et procédé de transmission |
JP2009182906A (ja) * | 2008-01-31 | 2009-08-13 | Kyocera Corp | 増幅器 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014158179A (ja) * | 2013-02-15 | 2014-08-28 | Harada Ind Co Ltd | アンプ装置 |
US9531086B1 (en) | 2016-01-06 | 2016-12-27 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
US10008995B2 (en) | 2016-01-06 | 2018-06-26 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
US10298190B2 (en) | 2016-01-06 | 2019-05-21 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
US10693429B2 (en) | 2016-01-06 | 2020-06-23 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
US10749489B2 (en) | 2016-01-06 | 2020-08-18 | International Business Machines Corporation | Dynamic phased array tapering without phase recalibration |
Also Published As
Publication number | Publication date |
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JPWO2011024598A1 (ja) | 2013-01-24 |
US20120157010A1 (en) | 2012-06-21 |
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