WO2010104249A1 - Dispositif émetteur de lumière à séparation de substrat par implantation ionique - Google Patents

Dispositif émetteur de lumière à séparation de substrat par implantation ionique Download PDF

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Publication number
WO2010104249A1
WO2010104249A1 PCT/KR2009/004510 KR2009004510W WO2010104249A1 WO 2010104249 A1 WO2010104249 A1 WO 2010104249A1 KR 2009004510 W KR2009004510 W KR 2009004510W WO 2010104249 A1 WO2010104249 A1 WO 2010104249A1
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WIPO (PCT)
Prior art keywords
layer
forming
semiconductor layer
substrate
stacked structure
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PCT/KR2009/004510
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English (en)
Inventor
Deok Ha Woo
Sun Ho Kim
Seok Lee
Young Tae Byun
Young Min Jhon
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Korea Institute Of Science And Technology
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Publication of WO2010104249A1 publication Critical patent/WO2010104249A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • the present disclosure relates to a light emitting device, more particularly, to a method of forming a light emitting device using substrate separation by ion implantation.
  • a light emitting diode as a representative example of a light emitting device, is formed with compound semiconductor materials suitable for emitting green, blue or ultraviolet light.
  • a semiconductor layer of a first conductivity type, an active layer, and a semiconductor layer of a second conductivity type are formed one after another on a substrate.
  • An electrode of the first conductivity type (a first electrode) and another electrode of the second conductivity type (a second electrode) are formed.
  • the substrate is a dielectric
  • the semiconductor layer of the second conductivity type and the active layer are selectively etched to expose a part of the semiconductor layer of the first conductivity type.
  • the first and second electrodes are respectively formed on the exposed part of the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type. In this fashion, the conventional horizontal structure LED may be formed.
  • the area of the first electrode that does not emit light causes loss in effective light emitting areas.
  • the effect of current crowding appears around the first electrode, which generates excessive heat.
  • the heat cannot be sufficiently emitted due to the low thermal conductivity of the dielectric substrate, notably degrading the performance of the device.
  • defects are generated in the semiconductor layer of the first conductivity type due to the difference in lattice constants of the substrate and the semiconductor layer of the first conductivity type.
  • a thick buffer layer is required on the substrate to reduce the defects.
  • the difference in the coefficients of thermal expansion between the substrate and the first semiconductor layer causes the substrate to bend.
  • a vertical structure LED has been proposed using a conductive SiC substrate, where two electrodes are vertically located on opposite sides of the substrate.
  • the LED using the conductive SiC substrate fails to provide solutions to the fundamental problems such as the generation of defects in the semiconductor layer formed on the substrate and bending of the wafer.
  • a metal reflecting layer may be formed over the grown epilayers.
  • a conductive bonding layer may be formed on the metal reflecting layer to bond a conductive substrate to the metal reflecting layer, and the substrate may be lifted off by laser irradiation (Laser Lift Off, LLO).
  • LLO Laser Lift Off
  • the vertical structure LED also has a smaller chip area, compared to the horizontal structure LED. Nevertheless, the vertical structure LED fabricated by LLO process is still confronted with the same problems as associated with the horizontal structure, such as the defects due to the lattice mismatch, a thick buffer layer, difficulty in using a large size substrate, and so on.
  • physical impact may be imposed to the interface between the substrate and the semiconductor layer during the LLO process. This physical impact causes cracks in the semiconductor layer, and the performance and reliability of the device may be degraded.
  • a method of forming a light emitting device includes forming a stacked structure including a substrate, a lower semiconductor layer of a first conductivity type, an active layer, and an upper semiconductor layer of a second conductivity type, wherein the stacked structure includes a separation layer formed below the active layer; and performing a thermal process upon the stacked structure to divide the separation layer laterally such that the stack structure is separated into an upper part and a lower part.
  • the forming of the stacked structure includes forming the lower semiconductor layer of the first conductivity type on a substrate, forming the active layer on the lower semiconductor layer, forming the upper semiconductor layer of the second conductivity type on the active layer; and forming the separation layer by implanting ions into the substrate or the lower semiconductor layer.
  • forming the stacked structure includes forming the separation layer by implanting ions into the substrate; and sequentially forming the lower semiconductor layer of the first conductivity type, the active layer and the upper semiconductor layer of the second conductivity type on the substrate having the separation layer formed therein.
  • the forming of the separation layer further includes forming an ion implantation mask covering an edge of the substrate; forming the separation layer by implanting the ions on portions of the substrate not covered by the mask and wherein ions are not implanted in portions of the substrate covered by the mask; and removing the ion implantation mask after the ion implantation.
  • a cutting process or etching along a base line extended from a border between the separation layer and the non-implantation area is performed after separating the stacked structure into the upper part and the lower part through the thermal process.
  • a vertical structure light emitting device can be formed without using conventional laser lift off (LLO) processes, so that no mechanical impact may be imposed, thus making no cracks, increasing device yields, and improving reliability.
  • LLO laser lift off
  • a semiconductor substrate may be reused, and the fabrication cost may be drastically reduced.
  • Figs. 1 to 5 are cross sectional views showing a process of forming a vertical structure light emitting device in accordance with a first embodiment.
  • Figs. 6 to 11 are cross sectional views showing a process of forming a vertical structure light emitting device in accordance with a second embodiment.
  • One aspect of the present invnetion relates to a method of forming a vertical structure light emitting device.
  • a lower semiconductor layer of a first conductivity type, an active layer, and an upper semiconductor layer of a second conductivity type may be stacked on a substrate to form a stacked structure.
  • a separation layer may be formed in an area beneath the active layer.
  • a thermal process may be performed to divide the separation layer SL1 laterally such that the stacked structure is separated into an upper part and a lower part.
  • a separation layer may be formed in a substrate by implanting ions at a predetermined depth before epilayer growth.
  • the substrate including the separation layer may constitute a stacked structure together with semiconductor layers laminated on the growth substrate by crystal growth processes.
  • a thermal process may be performed to divide the stacked structure so that it is separated laterally into an upper part and a lower part.
  • a thermal process for forming Ohmic contact may unintentionally induce such separation.
  • Layers of thin films constituting a light emitting device may be formed on a substrate to configure a stacked structure.
  • An ion implantation process may be performed to implant ions at a depth where a separation layer is to be formed.
  • a conductive layer may be formed on the top of the stacked structure for reflection and/or Ohmic contact.
  • a thermal process may be further performed to cause lateral separation in the layer to which the ions have been implanted, i.e., in the separation layer to separate the stacked structure into an upper part and a lower part.
  • a fundamental light emitting device structure may be formed with the separated upper part of the stacked structure.
  • a process of forming electrodes for applying currents to the fundamental light emitting device structure may also be performed.
  • a lower semiconductor layer 11 of a first conductivity type, an active layer 12, and an upper semiconductor layer 13 of a second conductivity type may be sequentially grown on a substrate 10.
  • the lower semiconductor layer 11, the active layer 12, and the upper semiconductor layer 13 may constitute the basic structure of the light emitting device.
  • the growth substrate 10 may be selected from the group consisting essentially of a sapphire substrate, a SiC substrate, a sapphire substrate having a GaN-based semiconductor layer laminated thereon, a SiC substrate having a GaN-based semiconductor layer laminated thereon, and a GaN substrate.
  • the lower semiconductor layer 11 and the upper semiconductor layer 13 may be formed with the GaN-based semiconductor layers to prevent generation of defects due to a difference in the lattice constants.
  • the upper semiconductor 13 may be a p-type semiconductor
  • the upper semiconductor 13 may be an n-type semiconductor.
  • the "GaN-based" semiconductor may be represented as Al x Ga y In (1-x-y) N(0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and 0 ⁇ x+y ⁇ 1), and may include compound semiconductor materials suitable for emitting green, blue or ultraviolet light.
  • a separation layer SL1 may be formed by accelerating and implanting ions at a desired depth from the surface of the upper semiconductor layer 13. While Fig. 2 illustrates an example of forming the separation layer SL1 within the lower semiconductor layer 11, the separation layer SL1 may be formed within the growth substrate 10 in accordance with another embodiment.
  • acceleration energy of the ions may be determined by the depth from the surface of the upper semiconductor 13 to the position where the separation layer SL1 is to be formed, and the type of ions used.
  • ions of light chemical elements whose atomic numbers are 54 or less, are implanted with an acceleration energy ranging from 100 KeV to 10 MeV, thereby forming separation layer SL1 within the lower semiconductor layer 11 or the growth substrate 10.
  • the stack structure formed in accordance with the processes of Figs. 1 and 2 may include growth substrate 10, lower semiconductor layer 11, active layer 12, and upper semiconductor layer 13, which are formed on growth substrate 10.
  • the stacked structure also may include separation layer SL1 formed in the lower area (lower semiconductor layer 11 or growth layer 10) which is lower than active layer 12.
  • an Ohmic contact layer 14 and a metal layer 15 for reflecting light are formed on the upper semiconductor layer 13, and a conductive substrate 20 may be joined to the metal layer 15.
  • the metal layer 15 may be at least one film of one metal selected from the group consisting essentially of Cu, Al, Au, Pd, Ti, In, Ni and Pt or an alloy film of at least two metals selected from the above-mentioned group.
  • Conductive substrate 20 may be made of a low-priced semiconductor or metal substrate having a high heat transmission coefficient, such as Si, Cu and Al, or an alloy substrate whose composition can be adjusted to have the same thermal expansion coefficient as the GaN semiconductor layer.
  • a conductive transparent electrode of Indium Tin Oxide (ITO) may be used as the Ohmic contact layer 14.
  • ITO Indium Tin Oxide
  • the Ohmic contact layer 14 may be omitted in some embodiments if metal layer 15 has sufficient Ohmic contact characteristics.
  • the stacked structure formed in accordance with the processes of Figs. 1 to 2 may include growth substrate 10, lower semiconductor layer 11, active layer 12, upper semiconductor layer 13 and separation layer SL1 which is formed in the lower area (lower semiconductor layer 11 or growth layer 10), which is lower than active layer 12.
  • the stacked structure may further include Ohmic contact layer 14, metal layer 15 and conductive layer 20.
  • a thermal process may be applied to the stacked structure in accordance with the processes illustrated in Figs. 1 and 2 or in accordance with the processes illustrated in Figs. 1 to 3, in order to divide the separation layer SL1 laterally such that the stack structure is separated into an upper part and a lower part.
  • the thermal process includes a heating process or a process involving heating.
  • the heating process may be applied to the stacked structure at a temperature ranging from 100°C to 1000°C, so that the lower semiconductor layer 11 may be separated along the separation layer SL1 into a first lower semiconductor layer 11a and a second lower semiconductor 11b, as shown in Fig. 4.
  • the separation along the separation layer SL1 may be accomplished by the heating process for the Ohmic contact only if the heating process can supply sufficient heat for separation.
  • an electrical contact pad 16 may be formed on a surface of the first lower semiconductor layer 11a, which is exposed by the separation process.
  • a transparent electrode (not illustrated) may be formed on the surface of the first lower semiconductor layer 11a.
  • the electrical contact pad 16 may be formed on the transparent electrode.
  • a roughening process may be performed upon the surface of the first lower semiconductor layer 11a before forming the transparent electrode or the electrical contact pad 16.
  • the stacked layers from the first lower semiconductor layer 11a to the electrical contact pad 16 are diced into the individual chips and packaged into a lamp or SMD (surface mount device) form.
  • the conductive substrate 20 and the transparent electrode (or the electrical contact pad 16) function as an n (or p)- type electrode and a p (or n)-type electrode, respectively.
  • Light may be generated in the active layer 12 by the combination of the electrons and the holes when a voltage is applied to each end of the electrodes.
  • the generated light may be emitted in the direction of all solid angle.
  • the light emitted from the active layer 12 in the direction of the conductive layer 20 may be reflected toward and emitted through the surface of the first lower semiconductor layer 11a, with the result that optical power output may increase.
  • the growth substrate 10 and the second lower semiconductor layer 11b remaining thereon may be reused as a growth substrate to form another vertical semiconductor light emitting device.
  • the loss of the growth substrates can be prevented when fabricating the light emitting devices.
  • the manufacturing costs can be remarkably reduced owing to the reuse of the growth substrate 10.
  • the same kind of thin film having no defects can be grown on the second lower semiconductor layer 11b, which enables repeated manufacture of the vertical structure light emitting devices with high efficiency at lower costs.
  • polishing may be performed upon the second lower semiconductor layer 11b before reuse.
  • a separation layer SL2 may be formed by implanting ions into a growth substrate 30.
  • Ion implanting energy may be adjusted to be approximately in the range of 1 keV to 10 MeV so that separation layer SL2 may be formed at the depth ranging from about 10 nm to 10,000 nm from the surface of the growth substrate 30.
  • the growth substrate 30 may be selected from the group consisting essentially of a sapphire substrate, a SiC substrate, a sapphire substrate having a GaN-based semiconductor layer laminated thereon, a SiC substrate having a GaN-based semiconductor layer laminated thereon and a GaN substrate.
  • the implanted ions may be at least one kind of light chemical element, whose atomic numbers are 54 or less.
  • implanting ions at the edge of growth substrate 30 may not be necessary.
  • the edge area A of the growth substrate 30 may be covered with an ion implantation mask M.
  • the mask M may be removed after finishing the ion implantation.
  • a device such as a chuck for holding the growth substrate 30 may function as the ion implantation mask M while implanting ions.
  • a lower semiconductor layer 31 of a first conductivity type, an active layer 32 and an upper semiconductor layer 33 of a second conductivity type may be sequentially formed on the growth substrate 30 in which the separation layer SL2 has been formed.
  • the upper semiconductor layer 33 is a p-type.
  • the upper semiconductor layer 33 is an n-type. If the substrate having the GaN-based semiconductor layer is adopted as the growth substrate 30, a lower semiconductor layer 31 and an upper semiconductor layer 33 may be formed with the GaN-based semiconductor layers to thereby prevent generation of the defects due to a difference in the lattice constants.
  • the "GaN-based" semiconductor may be represented as Al x Ga y In(1-x-y)N(0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1), and may include compound semiconductor materials suitable for emitting light in green, blue or ultraviolet light.
  • the stacked structure formed according to the processes of Figs. 6 and 7 may include the growth substrate 30, the lower semiconductor layer 31, the active layer 32 and the upper semiconductor layer 33, which are formed one after another on the growth substrate 30 in which the separation layer SL2 is formed.
  • the separation layer SL2 may exist in the lower area (the growth substrate 30), which is lower than the active layer 32 similar to the first embodiment.
  • an Ohmic contact layer 34 and a metal layer 35 for reflecting light are formed on top of the upper semiconductor layer 33.
  • the metal layer 35 in one embodiment may be formed of at least one film of one metal selected from the group consisting essentially of Cu, Al, Au, Pd, Ti, In, Ni and Pt or an alloy film of at least two metals selected from the above-mentioned group.
  • An ITO type conductive transparent electrode may be used as the Ohmic contact layer 34, which however may be omitted if the metal layer 35 has sufficient Ohmic contact characteristics.
  • a conductive substrate 40 may be joined to the metal layer 35, as shown in Fig. 9.
  • a low-priced semiconductor or metal substrate having a high heat transmission rate, such as Si, Cu and Al, or an alloy substrate whose composition can be adjusted to have the same thermal expansion coefficient as the GaN semiconductor layer, may be employed as the conductive substrate 40.
  • An end portion of the conductive substrate 40 may be positioned at lines B extended from the border between the separation layer SL2 and the edge area A to which ions have not been implanted.
  • the stacked structure formed according to the processes of Figs. 6 to 9 may include the growth substrate 30, the lower semiconductor layer 31, the active layer 32, the upper semiconductor layer 33, the Ohmic contact layer 34, the metal layer 35, the conductive substrate 40 joined to the metal layer 35, and the separation layer SL2 formed below active layer 32, i.e., in the growth substrate 30.
  • the stacked structure may be separated into an upper part and a lower part.
  • the stacked structure including the lower semiconductor layer 31, the active layer 32, the upper semiconductor layer 33, the Ohmic contact layer 34 and the conductive layer 40 may still be attached to the growth substrate 30 without being detached from the growth substrate 30. This is accomplished during the ion implantation stage by ensuring ions are not implanted in edge area A through the use of an ion implantation mask. In some embodiments, it is possible that some ions may be implanted in some portions that are covered by the mask, but ions for the most part will not be implanted in portions covered by the mask.
  • a cutting process may be performed by using a laser, a scriber or a diamond saw to cut the metal layer 35, the Ohmic contact layer 34, the upper semiconductor layer 33, the active layer 32, the lower semiconductor layer 31 and a part of the growth substrate 30, along the lines B to which the ends of the conductive substrate 40 are aligned.
  • the growth substrate 30, the lower semiconductor layer 31, the active layer 32, the upper semiconductor layer 33 and the Ohmic contact layer 34 are respectively divided into a first growth substrate 30a and a second growth substrate 30b, a first lower semiconductor layer 31a and a second lower semiconductor layer 31b, a first active layer 32a and a second active layer 32b, a first upper semiconductor layer 33a and a second upper semiconductor 33b, a first Ohmic contact layer 34a, a second Ohmic contact layer 34b and the first metal layer 35a and the second metal layer 35b.
  • the second growth substrate 30b may include the edge of the growth substrate 30 and a lower part of the separation layer SL2.
  • the second lower semiconductor layer 31b, the second active layer 32b, the second upper semiconductor 33b, the second Ohmic contact layer 34b and the second metal layer 35b may be left on the edge of the growth substrate 30.
  • a dry etching or wet chemical etching process may be applied to remove the second metal layer 35b, a second Ohmic contact layer 34b, a second upper semiconductor 33b, a second active layer 32b, a second lower semiconductor layer 31b, and upper portion of the substrate down to separation layer SL2.
  • the stack structure of the first growth substrate 30a, the first lower semiconductor layer 31a, the first active layer 32a, the first upper semiconductor layer 33a, the first Ohmic contact layer 34a, the first metal layer 35a and the conductive substrate 40 may constitute the light emitting device.
  • An etching process and a polishing process may be performed to remove the second lower semiconductor 31b, the second active layer 32b, the second upper semiconductor layer 33b, the second Ohmic contact layer 34b and the second metal layer 35b, which have been left on the edge of the second growth substrate 30b, so that only the second growth substrate 30b may remain.
  • the remaining second growth substrate 30b may be reused as the growth substrate 30 shown in Fig. 6, after going through a surface smoothing process such as polishing.
  • the first growth substrate 30a may be part of the first lower semiconductor layer 31a. If first growth substrate 30a is a dielectric, the first growth substrate 30a may be removed to expose the surface of the first lower semiconductor layer 31a, and a transparent electrode (not illustrated) may be formed on the exposed surface of the first lower semiconductor 31a. An electrical contact pad 36 may be formed on the transparent electrode, as shown in Fig. 11. An electrical contact pad 36 may be formed directly on the first lower semiconductor layer 31a if transparent electrode is not needed. Further, in order to improve light emission efficiency, a roughening process may be performed upon the surface of the first lower semiconductor layer 31a before forming the transparent electrode or the electrical pad 36. A dicing process to form individual chips and packaging into a lamp or SMD (surface mount device) form may also be performed in some embodiments.
  • SMD surface mount device
  • the currents may flow vertically from the p-type electrode to the n-type electrode of the light emitting device.
  • Light may be generated in the first active layer 32a by the combination of electrons and holes, and the generated light may be emitted in the direction of all solid angle.
  • the light emitted in the direction of the conductive substrate 40 may be reflected toward and emitted through the surface of the first lower semiconductor layer 31a, resulting in an increased optical power output.
  • an edge emitting laser may be manufactured by additionally performing a cleavage process on the first lower semiconductors 11a and 31a, the active layers 12 and 32a, and the first upper semiconductor layers 13 and 33a.
  • a light emitting device may be formed using separation by ion implantation to prevent cracking, and it may enable fabrication of a large size light emitting device having high efficiency at a low costs. Further, by preventing or minimizing damage on the growth substrate, the unit price of a device may not increase despite the use of a high-priced substrate. Therefore, a high-priced substrate with high performance can be used at a minimum cost. Light emitting devices formed using methods in accordance with the described embodiments may enable mass production of a GaN-based LEDs having high quality, high brightness, high yield and improved reliability at low costs.
  • the light emitting device forming methods in accordance with the described embodiments do not need to utilize conventional laser lift off (LLO) processes, so that no mechanical impact may be imposed, thus making no cracks, increasing performance and improving reliability.
  • LLO laser lift off
  • the semiconductor growth substrate may be reused, the fabrication cost may be drastically reduced.
  • the size of a substrate (wafer) may not be limited to 2 inches which a large size substrate producible with a wafer fabricating technique may be limited to.
  • a light emitting device may be formed using substrate separation by ion implantation.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne, selon des modes de réalisation, un procédé de fabrication d'un dispositif émetteur de lumière, le procédé comprenant les étapes consistant à : former une structure empilée comportant un substrat, une couche semiconductrice inférieure possédant une conductivité d'un premier type, une couche active, et une couche semiconductrice supérieure possédant une conductivité d'un second type, la structure empilée comportant une couche de séparation formée sous la couche active par implantation ionique ; et soumettre la structure empilée à un traitement thermique dans le but de la diviser latéralement et la séparer en une partie supérieure et une partie inférieure. Le dispositif émetteur de lumière avec séparation de substrat par implantation ionique ainsi obtenu résiste aux fissures, peut présenter des dimensions importantes et offrir un rendement élevé à moindre coût.
PCT/KR2009/004510 2009-03-09 2009-08-12 Dispositif émetteur de lumière à séparation de substrat par implantation ionique WO2010104249A1 (fr)

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KR10-2009-0019990 2009-03-09
KR1020090019990A KR101119009B1 (ko) 2009-03-09 2009-03-09 이온주입에 의한 분리를 이용한 발광소자 제조 방법

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US9356188B2 (en) * 2013-09-06 2016-05-31 Veeco Instruments, Inc. Tensile separation of a semiconducting stack
KR102001791B1 (ko) 2018-12-26 2019-07-18 한양대학교 산학협력단 이온 주입을 이용한 질화갈륨 기판 제조 방법

Citations (3)

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Publication number Priority date Publication date Assignee Title
US20030189212A1 (en) * 2002-04-09 2003-10-09 Yoo Myung Cheol Method of fabricating vertical devices using a metal support film
KR100835076B1 (ko) * 2006-12-08 2008-06-03 삼성전기주식회사 수직구조 ｌｅｄ 소자 및 그 제조 방법
KR20080078679A (ko) * 2005-12-21 2008-08-27 에스.오.아이. 테크 실리콘 온 인슐레이터 테크놀로지스 기판들의 제조 방법, 특히 광학, 전자공학 또는 광전자공학분야들에 대한, 및 상기 방법에 의해 구현되는 기판

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KR100638617B1 (ko) * 2004-09-22 2006-10-26 삼성전기주식회사 질화갈륨계 반도체 소자용 버퍼층 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189212A1 (en) * 2002-04-09 2003-10-09 Yoo Myung Cheol Method of fabricating vertical devices using a metal support film
KR20080078679A (ko) * 2005-12-21 2008-08-27 에스.오.아이. 테크 실리콘 온 인슐레이터 테크놀로지스 기판들의 제조 방법, 특히 광학, 전자공학 또는 광전자공학분야들에 대한, 및 상기 방법에 의해 구현되는 기판
KR100835076B1 (ko) * 2006-12-08 2008-06-03 삼성전기주식회사 수직구조 ｌｅｄ 소자 및 그 제조 방법

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