WO2010092843A1 - 同期整流方式を用いたコンパレータ方式dc-dcコンバータ - Google Patents
同期整流方式を用いたコンパレータ方式dc-dcコンバータ Download PDFInfo
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- WO2010092843A1 WO2010092843A1 PCT/JP2010/050066 JP2010050066W WO2010092843A1 WO 2010092843 A1 WO2010092843 A1 WO 2010092843A1 JP 2010050066 W JP2010050066 W JP 2010050066W WO 2010092843 A1 WO2010092843 A1 WO 2010092843A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a comparator type DC-DC converter using a synchronous rectification method.
- a DC-DC converter that generates a stabilized output voltage from an input voltage.
- the DC-DC converter includes a voltage conversion unit that generates an output voltage obtained by converting an input voltage by switching the switching element, and a control unit that controls switching of the switching element in order to stabilize the output voltage of the voltage conversion unit. And have.
- Patent Document 1 discloses a DC-DC converter using a synchronous rectification system in a voltage conversion unit. In this synchronous rectification DC-DC converter, in order to prevent a short circuit due to two switching elements being simultaneously turned on, a period during which these switching elements are simultaneously turned off, that is, a dead time is provided. .
- control method of the control unit includes, for example, a method using a PWM (pulse width modulation) method, a method using a comparator method, and the like.
- PWM pulse width modulation
- comparator method the on-pulse width of the switching element is made constant using a comparator, and the output voltage of the voltage converter is stabilized by adjusting the off-pulse width (that is, switching frequency).
- the comparator method has the following advantages compared with the PWM method.
- the DC-DC converter may be used as a voltage source such as a PU (Processor Unit).
- PU Processor Unit
- the current consumption increases rapidly when shifting from the standby state to the processing state.
- the comparator type DC-DC converter detects a drop in the output voltage by the comparator and immediately outputs an on-pulse.
- the comparator method has a characteristic that the response characteristic with respect to a sudden increase in load current is better than that of the PWM method.
- This comparator DC-DC converter is provided with an on-time for determining a fixed on-pulse width and a minimum off-time for determining a minimum width of an off-pulse. This minimum off time is provided for the following reasons.
- the comparator type DC-DC converter when the switching element is switched on / off, the power supply voltage on the high potential side may fluctuate due to switching of the operation state of the drive circuit for driving the switching element. is there. In particular, when the switching element on the high side switches from on to off and the switching element on the low side switches from off to on, that is, when the output voltage drops below the reference voltage, the comparator operates. .
- the minimum off state is to prevent the on-pulse generation even if the comparator malfunctions for a predetermined period until the fluctuation of the power supply voltage and reference voltage on the high potential side is settled, that is, to continue the off-pulse generation. Time is provided.
- the delay time of the analog delay circuit that is, the dead time, the on time, and the minimum off time, due to the manufacturing variation of the resistor element and the capacitor element and the temperature fluctuation.
- the accuracy was bad.
- the present invention provides a comparator-type DC-DC converter using a synchronous rectification method that can improve the accuracy of on-time, minimum off-time, and dead time without hindering downsizing and cost reduction.
- the purpose is that.
- a comparator-type DC-DC converter using a synchronous rectification method of the present invention has a switching element, and controls the switching element in accordance with a control signal to generate an output voltage obtained by voltage-converting an input voltage. And a control unit that generates a control signal for stabilizing the output voltage of the voltage conversion unit, the control unit detecting that the output voltage of the voltage conversion unit is lower than the reference voltage, and a minimum A trigger signal generation unit that generates a trigger signal when receiving an output signal from the comparator after receiving an off-time signal, a reference delay clock that is delayed by a reference delay amount from the reference clock, and the reference A DLL unit that generates a reference delay signal having a value corresponding to the delay amount, and a trigger signal based on the reference delay signal from the DLL unit From the trigger delay signal delayed by a predetermined delay amount from the trigger signal from the generator, the first dead time delay signal delayed from the trigger delay signal by the delay amount corresponding to the desired first dead time, and the first dead time delay signal An on-time delay signal
- the DLL unit and the delay unit for determining the dead time, the on time, and the minimum off time can be configured by, for example, one DSP (Digital Signal Processor). Therefore, the control unit can be reduced in size and price as compared with the case where a plurality of analog delay circuits each including a resistor element and a capacitor element are used.
- DSP Digital Signal Processor
- the delay unit determines the dead time, the on time, and the minimum off time based on the reference delay signal from the DLL unit.
- the accuracy of the dead time, the on time, and the minimum off time determined by the delay unit can be increased only by increasing the accuracy of the reference delay amount in the signal, that is, by increasing the accuracy of the DLL unit. Therefore, compared with the case where a trimming circuit element is used for each of a plurality of conventional analog delay circuits, the accuracy of dead time, on-time, and minimum off-time can be improved without hindering downsizing and cost reduction. Is possible.
- the DLL unit described above includes a DLL reference unit that generates a reference delay clock obtained by delaying the reference clock by a reference delay amount, a DLL delay unit that generates a DLL delay clock obtained by delaying the reference clock based on the reference delay signal, and a reference delay
- the delay unit described above includes a delay unit for generating a plurality of delay clocks having different delay amounts from the trigger signal from the trigger signal generation unit based on the reference delay signal from the DLL unit, and a delay unit for delay And a counter unit that generates a divided clock obtained by dividing a plurality of delay clocks for delay from the trigger delay signal, the first dead time delay signal, the on-time from the plurality of delay clocks and the divided clock.
- the delay signal, the second dead time delay signal, and the minimum off time delay signal are determined.
- the control unit since the counter unit generates the frequency-divided clock of the delay clock generated by the delay unit for delay, the number of delay clocks generated by the delay unit for delay can be reduced. That is, the circuit scale of the delay unit for delay can be reduced. Therefore, the control unit can be further reduced in size and price.
- the timing control unit described above includes an off-pulse end comparison unit that generates an off-pulse end signal indicating an end point of the off-pulse in the control signal in response to a trigger delay signal from the delay unit, and a first dead time delay signal from the delay unit.
- On-pulse start comparator for generating an on-pulse start signal indicating the start time of the on-pulse in the control signal and an on-pulse end signal generating an on-pulse end signal indicating the end time of the on-pulse according to the on-time delay signal from the delay unit
- Minimum off-time comparator that generates time signal and on-pulse start signal
- On-pulse logic operation unit that generates an on-pulse in the control signal by performing a logical operation between the off-pulse end signal and the on-pulse end signal, and an off-pulse that generates an off-pulse in the control signal by performing a logical operation between the off-pulse end
- the timing control unit can be configured by the same DSP as the DSP that configures the DLL unit and the delay unit, so that the control unit can be further reduced in size and price.
- the accuracy of on-time, minimum off-time and dead time can be improved without impeding the downsizing and cost reduction of the comparator-type DC-DC converter using the synchronous rectification method.
- FIG. 1 is a circuit diagram showing a comparator type DC-DC converter according to a first embodiment of the present invention.
- FIG. 2 is a circuit diagram showing the DLL section shown in FIG.
- FIG. 3 is a circuit diagram showing the delay unit shown in FIG.
- FIG. 4 is a circuit diagram showing the timing control unit shown in FIG.
- FIG. 5 is a timing chart showing signal waveforms of the comparator type DC-DC converter of the first embodiment.
- FIG. 6 is a timing chart showing signal waveforms of the control unit in the comparator type DC-DC converter of the first embodiment.
- FIG. 7 is a circuit diagram showing a comparator type DC-DC converter according to the second embodiment of the present invention.
- FIG. 8 is a circuit diagram showing the adjustment unit shown in FIG.
- FIG. 9 is a circuit diagram showing the delay unit shown in FIG.
- FIG. 10 is a timing chart showing signal waveforms of the adjusting unit shown in FIG.
- FIG. 1 is a circuit diagram showing a comparator-type DC-DC converter using a synchronous rectification method according to a first embodiment of the present invention.
- the DC-DC converter 1 shown in FIG. 1 includes a voltage conversion unit 100 and a control unit 200.
- the voltage converter 100 constitutes a synchronous rectifier circuit, and an output voltage Vout obtained by converting the input voltage Vin applied to the input terminal 2 in accordance with the switching control signals S SWHG and S SWLG from the controller 200 is converted. Occurs at the output terminal 3.
- the voltage conversion unit 100 includes two switching elements 11 and 12, a drive circuit 13, a coil 14, and a capacitive element 15.
- Switching elements 11 and 12 are N-type MOSFETs.
- the drain of the high-side switching element 11 is connected to the input terminal 2, and the source is connected to the drain of the low-side switching element 12.
- the source of the switching element 12 is grounded to the GND 5.
- the gates of the switching elements 11 and 12 are each connected to the drive circuit 13.
- the drive circuit 13 receives the switching control signals S SWHG and S SWLG from the control unit 200 and supplies them to the gates of the switching elements 11 and 12, respectively.
- the drive circuit 13 includes an amplifier, a booster circuit for a drive signal supplied to the switching element 11, and the like.
- One end of a coil 14 is connected to the source of the switching element 11 and the drain of the switching element 12. The other end of the coil 14 is connected to the output terminal 3.
- a capacitive element 15 for smoothing the output voltage is connected between the output terminal 3 and the GND 5.
- the control unit 200 uses a comparator method, and generates switching control signals S SWHG and S SWLG for stabilizing the output voltage Vout of the voltage conversion unit 100.
- the control unit 200 includes a comparator 20, a trigger signal generation unit 30, a DLL unit 40, a delay unit 50, and a timing control unit 60.
- the positive input terminal of the comparator 20 is connected to the output terminal 3 of the voltage converter 100, and the reference voltage Vref is input to the negative input terminal.
- the comparator 20 compares the output voltage Vout from the voltage converter 100 with the reference voltage Vref, and ends the off- pulse in the switching control signals S SWHG and S SWLG when the output voltage Vout becomes smaller than the reference voltage Vref.
- the pulse voltage Voff1 is generated.
- the output terminal of the comparator 20 is connected to one input terminal of the trigger signal generation unit 30.
- the minimum input time signal from the timing controller 60 is input to the other input terminal of the trigger signal generator 30.
- the trigger signal generation unit 30 constitutes an AND circuit, and receives the pulse voltage Voff1 after receiving the minimum off time signal, and terminates the off pulse in the switching control signals S SWHG and S SWLG .
- a pulse-like trigger voltage (trigger signal) Voff2 is generated.
- the output terminal of the trigger signal generation unit 30 is connected to the input terminal of the delay unit 50.
- the comparator 20 and the trigger signal generation unit 30 delay the trigger voltage Voff2 in order to increase the output voltage Vout when the output voltage Vout becomes smaller than the reference voltage Vref, that is, to create an on-pulse.
- the switching control signal S SWLG becomes a low level
- the switching control signal S SWHG becomes a high level after a dead time for preventing the switching elements 11 and 12 from penetrating. It will be.
- the comparator 20 and the trigger signal generation unit 30 can generate a signal for shifting to the next pulse generation sequence as described above.
- various circuit methods can be applied in place of the comparator 20 and the trigger signal generation unit 30.
- the DLL unit 40 receives the reference clock Cref and generates a reference delay clock Cref2 obtained by delaying the reference clock Cref by a reference delay amount. Further, the DLL unit 40 generates a reference delay voltage (reference delay signal) Vd having a value corresponding to the reference delay amount.
- FIG. 2 shows a circuit diagram of the DLL unit 40.
- the DLL unit 40 includes a high-accuracy delay unit (DLL reference unit) 41, a DLL delay unit 42, an amplifier 43, and a capacitive element 44.
- the amplifier 43 and the capacitive element 44 constitute a DLL comparison unit 45 described in the claims.
- the high accuracy delay unit 41 has a high accuracy reference delay amount.
- the high precision delay unit 41 generates a reference delay clock Cref2 obtained by delaying the reference clock Cref by this high precision reference delay amount.
- the high-accuracy delay unit 41 outputs the reference delay clock Cref2 to one input terminal of the amplifier 43.
- the DLL delay unit 42 includes m DLL partial delay units 42 1 to 42 m .
- Each of the DLL partial delay units 42 1 to 42 m includes transistors Tr1 to Tr6 and an inverter INV.
- the transistors Tr1 and Tr4 are P-type MOSFETs, and the transistors Tr2, Tr3, Tr5, and Tr6 are N-type MOSFETs.
- the transistor Tr1 and the transistor Tr2 are inverter-connected, and a reference clock Cref (a clock from the preceding DLL partial delay unit in the second and subsequent DLL partial delay units from the input side) is input to each gate.
- the source of the transistor Tr1 is connected to the power source Vcc on the high potential side.
- the transistor Tr3 is cascode-connected between the source of the transistor Tr2 and the GND 5, and the reference delay voltage Vd is input to the gate of the transistor Tr3.
- the transistor Tr4 and the transistor Tr5 are inverter-connected, and the drains of the transistors Tr1 and Tr2 are connected to the respective gates.
- the source of the transistor Tr4 is connected to the power source Vcc on the high potential side.
- the transistor Tr6 is cascode-connected between the source of the transistor Tr5 and the GND 5, and the reference delay voltage Vd is input to the gate of the transistor Tr6.
- the drains of the transistors Tr4 and Tr5 are connected to the DLL partial delay section at the subsequent stage via the inverter INV.
- the resistance values of the transistors Tr3 and Tr6 are determined according to the reference delay voltage Vd, and the delay amount of each of the DLL partial delay units 42 1 to 42 m , that is, the delay amount of the DLL delay unit 42 is set. It will be decided.
- the DLL delay unit 42 outputs the DLL delay clock Cref3 having the delay amount thus determined to the other input terminal of the amplifier 43.
- the amplifier 43 functions as a push-pull type current source, and in accordance with the difference between the phase of the reference delay clock Cref2 from the high-precision delay unit 41 and the phase of the DLL delay clock Cref3 from the DLL delay unit 42 44 is charged and discharged to generate a reference delay voltage Vd between the terminals of the capacitive element 44.
- the DLL unit 40 generates the reference delay voltage Vd so that the phase of the DLL delay clock Cref3 matches the phase of the reference delay clock Cref2, so that the reference delay voltage Vd having a highly accurate reference delay amount is generated. Will be generated.
- the DLL unit 40 supplies the reference delay voltage Vd to the delay unit 50.
- the delay unit 50 includes n delay clocks (delay signals) Cd 1 having different delay amounts from the trigger voltage Voff2 from the trigger signal generation unit 30 based on the reference delay voltage Vd from the DLL unit 40. to generate a ⁇ Cd n.
- FIG. 3 shows a circuit diagram of the delay unit 50.
- the delay unit 50 includes a delay unit 51 for delay, a counter unit 54, and a decoder 55.
- the delay unit 51 for delay uses m (m ⁇ n) delay signals Sd 1 having different delay amounts from the trigger voltage Voff2 from the trigger signal generation unit 30. to generate a ⁇ Sd m.
- the delay unit 51 for delay has an AND circuit 52 and m partial delay units 53 1 to 53 m for delay. To one input terminal of the AND circuit 52 trigger voltage Voff2 is input to the other input terminal is input delayed delay signal Sd m from the delaying delay section 53. Output terminals of the AND circuit 52 is connected to the input terminal of the delay for partial delay unit 53 1.
- Each of the delay partial delay units 53 1 to 53 m includes transistors Tr1 to Tr6 and an inverter INV, similarly to each of the DLL partial delay units 42 1 to 42 m .
- the resistance values of the transistors Tr3 and Tr6 are determined according to the reference delay voltage Vd, and the delay amounts of the delay partial delay units 53 1 to 53 m are determined.
- the partial delay units 53 1 to 53 m for delay supply the delay signals Sd 1 to Sd m having a delay amount determined in this way to the decoder 55, and the delay signal Sd m for delay is supplied to the counter unit 54. Supply to the input terminal.
- the counter unit 54 has p D-FF units 54 1 to 54 p .
- the clock signal of the D-FF unit 54 1 is input with a delay signal Sd m from the delay unit 51 for delay (in the second and subsequent D-FF units from the input side, a normal rotation signal from the preceding D-FF unit).
- the inverted output signal Sdm + 1 is input to the data input terminal.
- Normal output signal of the D-FF 54 1 is supplied to the (downstream of D-FF unit is D-FF of the second and subsequent from the input side) the clock terminal of the D-FF 54 2, trigger a reset terminal
- the trigger voltage Voff2 from the signal generation unit 30 is input as a reset signal.
- D-FF section 54 1 ⁇ 54 p is twice the delay for the delay signal Sd m, it supplies the divided signal Sd m + 1 ⁇ Sd n that four times ... to the decoder 55. Further, D-FF section 54 1 ⁇ 54 p by resetting in response to the trigger voltage Voff2, then a delay for the delay unit 51 to delay for the delay signal Sd m is input, the divided signal Sd m + 1 ⁇ to stop the generation of Sd n.
- the decoder 55 decodes the delay signals Sd 1 to Sd m from the delay unit 51 and the frequency-divided signals Sd m + 1 to Sd n from the counter unit 54, for example, different delay amounts in increments of 1 ns. N delay clocks Cd 1 to Cd n are generated. These delay clock Cd 1 ⁇ Cd n is contains delayed clock having a delay amount corresponding to each of the desired first dead time, the desired second dead time, desired on-time and the desired minimum off-time Yes.
- the desired on-time that is, the on-pulse width Ton
- Ton (1 / f) ⁇ (Vout / Vin)
- Ton 400 ns may be set.
- the desired first dead time and the desired second dead time are preferably about 40 ns, and the desired minimum off time is preferably about 200 ns.
- the delay unit 50 includes a trigger delay clock (trigger delay signal) Cd 1 delayed from the trigger voltage Voff2 by a minimum delay amount of 1 ns, and a delay amount of a desired first dead time 40 ns from the trigger delay clock Cd 1.
- a second dead time delay clock (second dead time delay signal) Cd 481 delayed from the on-time delay clock Cd 441 by a delay amount of a desired second dead time 40 ns, and the second dead time of the desired from the delay clock Cd 481 minimum off-time 2
- FIG. 4 shows a circuit diagram of the timing control unit 60.
- the timing control unit 60 forms a decoder, and includes an off-pulse end comparison unit 61, an on-pulse start comparison unit 62, an on-pulse end comparison unit 63, and an off-pulse start comparison unit 64.
- a minimum off-time comparison unit 65 inverters 66 and 69, an on-pulse AND circuit (on-pulse logic operation unit) 67, and an off-pulse OR circuit (off-pulse logic operation unit) 68.
- the off-pulse end comparison unit 61 To one input terminal of the off-pulse termination comparing portion 61 is inputted delay clock Cd n, to the other input terminal trigger delay clock Cd 1 is input.
- the off-pulse end comparison unit 61 generates an off-pulse end signal Soffe indicating the end point of the off- pulse in the switching control signal S SWLG according to the trigger delay clock Cd 1 .
- the on-pulse start comparison unit 62 To one input terminal of the on-pulse start comparison section 62 is input delay clock Cd n, to the other input terminal is the first dead time delay clock Cd 41 is input.
- the on-pulse start comparison unit 62 generates an on-pulse start signal Sons indicating the on-pulse start time in the switching control signal S SWHG according to the first dead time delay clock Cd 41 .
- the on-pulse end comparison unit 63 generates an on-pulse end signal Sone indicating the end time of the on-pulse in the switching control signal S SWHG in accordance with the on-time delay clock Cd 441 .
- the off-pulse start comparison unit 64 To one input terminal of the off-pulse start comparison section 64 is input delay clock Cd n, to the other input terminal and the second dead time delay clock Cd 481 are input.
- the off-pulse start comparison unit 64 generates an off-pulse start signal Poffs indicating the start time of the off- pulse in the switching control signal S SWHG according to the second dead time delay clock Cd 481 .
- the minimum off time comparison unit 65 To one input terminal of the minimum off-time comparison section 65 is input delay clock Cd n, to the other input terminal minimum off-time clock Cd 681 is input.
- the minimum off time comparison unit 65 generates a minimum off time signal Soffmin in accordance with the minimum off time clock Cd 681 .
- the on-pulse AND circuit 67 obtains a logical product of the on-pulse start signal Sons from the on-pulse start comparison unit 62 and the signal obtained by inverting the on-pulse end signal Sone from the on-pulse end comparison unit 63 by the inverter 66, and the switching control signal An on-pulse is generated in S SWHG . In this way, the start time and end time of the on-pulse in the switching control signal S SWHG are determined.
- the off-pulse OR circuit 68 obtains the logical sum of the signal obtained by inverting the off-pulse end signal Soffe from the off-pulse end comparison unit 61 by the inverter 69 and the off-pulse start signal Soffs from the off-pulse start comparison unit 64, and the switching control signal Generate an off- pulse in S SWLG . In this manner, the start time and end time of the off pulse in the switching control signal S SWLG are determined.
- the timing control unit 60 generates the switching control signals S SWHG and S SWLG having a dead time of 40 ns, an on time of 400 ns, and a minimum off time of 200 ns.
- FIG. 5 is a timing chart showing each signal waveform in the DC-DC converter 1
- FIG. 6 is a timing chart showing each signal waveform in the control unit 200 of the DC-DC converter 1.
- a high-level pulse voltage Voff1 is generated by the comparator 20 of the control unit 200 (FIGS. 5C and 6A).
- the trigger signal generation unit 30 generates a high-level trigger voltage Voff2
- the delay unit 50 generates a reference delay voltage from the DLL unit 40.
- n delay clocks Cd 1 to Cd n delayed by an interval of 1 ns are generated (FIGS. 6B to 6D).
- the off-pulse end comparison unit 61 of the timing control unit 60 generates the off-pulse end signal Soffe (FIG. 6 (e)), and the off-pulse AND
- the circuit 68 ends the generation of the off pulse Poff in the switching control signal S SWLG at the end time Toffe of the off pulse Poff (FIG. 6 (k), FIG. 5 (e)). Then, the switching element 12 is turned off.
- the on pulse start signal Sons is generated by the on pulse start comparison unit 62 of the timing control unit 60 (FIG. 6 ( f))
- the on-pulse AND circuit 67 starts the generation of the on-pulse Pon in the switching control signal S SWHG at the start time Tons of the on-pulse Pon (FIG. 6 (j), FIG. 5 (d)).
- the switching element 11 is turned on, the coil current IL is increased (FIG. 5B), and the output voltage Vout is increased (FIG. 5A).
- the on-pulse end signal Sone is generated by the on-pulse end comparison unit 63 of the timing control unit 60 (FIG. 6 (g)).
- the generation of the on pulse Pon in the switching control signal S SWHG is ended by the on pulse AND circuit 67 at the end time Tone of the on pulse Pon (FIG. 6 (j), FIG. 5 (d)). Then, the switching element 11 is turned off.
- the off pulse start comparison unit 64 of the timing control unit 60 generates the off pulse start signal Soffs (FIG. 6 ( h)), the generation of the off pulse Poff in the switching control signal S SWLG is started by the off pulse OR circuit 68 at the start time Toffs of the off pulse Poff (FIG. 6 (k), FIG. 5 (e)). Then, the switching element 12 is turned on, the coil current IL is decreased (FIG. 5B), and the output voltage Vout is decreased (FIG. 5A).
- the minimum off time delay clock Cd 681 delayed by the minimum off time 200 ns is generated by the delay unit 50, the minimum off time signal Soffmin is generated (FIG. 6 (i)).
- the output voltage Vout next decreases and reaches the reference voltage Vref and the comparator 20 generates the high-level pulse voltage Voff1
- the above operation can be repeated.
- the pulse width of the on pulse Pon is set to a fixed on time of 400 ns.
- a dead time of 40 ns is provided between the on-pulse Pon and the off-pulse Poff, and a dead time of 40 ns is provided between the off-pulse Poff and the on-pulse Pon to prevent the switching elements 11 and 12 from being turned on simultaneously. It can. That is, it is possible to prevent a through current from flowing through the switching elements 11 and 12. As a result, power conversion efficiency can be improved.
- a minimum off time of 200 ns is set, and the pulse width of the off pulse Poff can be prevented from being narrowed to 200 ns or less.
- the comparator type DC-DC converter when the switching element is turned on / off, the power supply voltage on the high potential side fluctuates due to the switching of the operation state of the drive circuit for driving the switching element. There are things to do. In particular, when the switching element on the high side switches from on to off and the switching element on the low side switches from off to on, that is, when the output voltage drops below the reference voltage, the comparator operates. . At this time, if the power supply voltage or the reference voltage for the comparator fluctuates due to the fluctuation of the power supply voltage on the high potential side, the comparator may malfunction.
- the DLL unit 40 and the delay unit 50 that determine the dead time, the on time, and the minimum off time can be configured by, for example, a DSP (Digital Signal Processor).
- the control unit 200 can be reduced in size and price as compared with the case where a plurality of analog delay circuits each including a resistor element and a capacitor element are used. Moreover, you may comprise the control part 200 whole with DSP.
- the output voltage Vout of the control unit 200 can be configured by an AD conversion unit that performs AD conversion and a DSP.
- the delay unit 50 determines the dead time, the on time, and the minimum off time based on the reference delay voltage Vd from the DLL unit 40.
- the accuracy of the dead time, the on time, and the minimum off time determined by the delay unit 50 can be increased only by increasing the accuracy of the reference delay amount in the delay voltage Vd, that is, by increasing the accuracy of the DLL unit 40. Therefore, compared with the case where a trimming circuit element is used for each of a plurality of conventional analog delay circuits, the accuracy of dead time, on-time, and minimum off-time can be improved without hindering downsizing and cost reduction. Is possible.
- the reference delay voltage Vd having a highly accurate reference delay amount can be generated only by improving the accuracy of the high accuracy delay unit 41 in the DLL unit 40. it can. Therefore, it is possible to increase the accuracy of dead time, on time, and minimum off time without further hindering miniaturization and price reduction.
- the counter unit 54 in the delay unit 50 causes the delay signals Sd 1 to Sd m generated by the delay unit 51 to be divided signals Sd m + 1. Since generating a ⁇ Sd n, keep signal for generating a delayed clock Cd 1 ⁇ Cd n required, it is possible to reduce the number of delay signals generated by delaying the delay unit 51. That is, the circuit scale of the delay unit 51 for delay can be reduced. Therefore, the control unit 200 can be further reduced in size and price.
- the timing control unit 60 can be configured by the same DSP as the DSP configuring the DLL unit 40 and the delay unit 50. 200 can be further reduced in size and price.
- FIG. 7 is a circuit diagram showing a comparator type DC-DC converter using the synchronous rectification method according to the second embodiment of the present invention.
- a DC-DC converter 1A shown in FIG. 7 is different from the first embodiment in that the DC-DC converter 1 includes a control unit 200A instead of the control unit 200.
- the control unit 200A is different from the control unit 200 in that the control unit 200 includes a DLL unit 40A instead of the DLL unit 40, and further includes an adjustment unit 70A.
- Other configurations of the control unit 200A are the same as those of the control unit 200.
- the adjustment unit 70A receives the switching control signal S SWHG (or S SWLG ) and the reference clock Cref5.
- the adjustment unit 70A compares the switching control signal S SWHG (or S SWLG ) with the reference clock Cref5, and determines a predetermined ON pulse so that the frequencies of the switching control signals S SWHG and S SWLG become constant according to the comparison result. Adjust the on width of. Specifically, the adjustment unit 70A counts an ON pulse in the switching control signal S SWHG (or an OFF pulse in the switching control signal S SWLG ) and counts the reference clock Cref5, and counts the switching control signal S SWHG (or S SWLG ).
- a frequency control signal Sf for adjusting a predetermined ON width of the ON pulse is generated so that the value and the count value of the reference clock Cref5 are equal.
- the frequency control signal Sf is a 4-bit digital signal.
- FIG. 8 is a circuit diagram showing the adjustment unit 70A shown in FIG.
- the adjustment unit 70 ⁇ / b> A illustrated in FIG. 8 includes two counters 71 and 72 and an up / down counter 73.
- the switching control signal S SWHG is input to the input terminal of the first counter 71, and the output voltage of the second counter 72 is input to the reset terminal.
- the first counter 71 is a 4-bit counter.
- the first counter 71 counts the ON pulse of the switching control signal S SWHG , and outputs a high-level pulse voltage when the count value reaches the maximum value “1111”, and at the next count of “1111”. Reset the output voltage.
- the first counter 71 also resets the output voltage when the output voltage of the second counter 72 becomes high level.
- the output terminal of the first counter 71 is connected to one input terminal of the up / down counter 73.
- the reference clock Cref5 is input to the input terminal of the second counter 72, and the output voltage of the first counter 71 is input to the reset terminal.
- the second counter 72 is a 4-bit counter.
- the second counter 72 counts the period of the reference clock Cref5. When the count value reaches the maximum value “1111”, the second counter 72 outputs a high level pulse voltage and outputs the voltage at the next count of “1111”. To reset.
- the second counter 72 also resets the output voltage when the output voltage of the first counter 71 becomes high level.
- the output terminal of the second counter 72 is connected to the other input terminal of the up / down counter 73.
- the up / down counter 73 receives the pulse voltage from the first counter 71 and the pulse voltages Vdown and Vup from the second counter 72 and increases or decreases the count value.
- the up / down counter 73 decreases the count value when the high level pulse voltage Vdown is input from the first counter 71, and the high level pulse voltage Vup is input from the second counter 72.
- the count value is increased when The up / down counter 73 outputs a 4-bit digital frequency control signal Sf to the DLL unit 40A.
- FIG. 9 is a circuit diagram showing the DLL unit 40A.
- the DLL unit 40A shown in FIG. 9 is different from the DLL unit 40 in that the DLL unit 40 further includes a digital / analog conversion unit (hereinafter referred to as DAC) 46 and an amplifier 47.
- DAC digital / analog conversion unit
- the DAC 46 performs digital / analog conversion on the frequency control signal Sf from the adjustment unit 70 ⁇ / b> A and outputs it to one input terminal of the amplifier 47.
- the reference voltage Vref2 is input to the other input terminal of the amplifier 47.
- the amplifier 47 functions as a push-pull type current source. For example, when the frequency control signal Sf is equal to or higher than the reference voltage Vref2, the amplifier 47 supplies current to the capacitive element 44, and when the frequency control signal Sf is smaller than the reference voltage Vref2, the capacitive element. The current is drawn from 44.
- the amplifier 47 increases the value of the reference delay voltage Vd when the frequency control signal Sf is equal to or higher than the reference voltage Vref2, and decreases the value of the reference delay voltage Vd when the frequency control signal Sf is smaller than the reference voltage Vref2.
- the DC-DC converter 1A of the second embodiment also has the same configuration as that of the DC-DC converter 1 of the first embodiment, and thus has the same advantages as the DC-DC converter 1 of the first embodiment. Can be obtained.
- the off-pulse width is shortened and the on-duty is increased in order to compensate for a decrease in output voltage due to an increase in internal loss.
- the switching frequency gradually varies due to the variation of the environmental temperature.
- Other variations in input voltage, output voltage, and output current also change the off-pulse width and change the switching frequency.
- the fluctuation of the switching frequency may cause the output voltage ripple to fluctuate, which may cause a subsequent circuit such as PU to malfunction.
- measures against EMI over a wide band are required.
- the DC-DC converter 1A of the second embodiment when the environmental temperature is lowered, for example, the internal resistance values of the switching elements 11, 12 and the coil 14 are lowered, and the internal loss is lowered. At this time, in order to compensate for the increase in the output voltage Vout, the off width of the off pulse Poff is widened, and the on-duty is reduced. On the other hand, the predetermined ON width of the ON pulse Pon is adjusted by the adjusting unit 70A.
- the second counter 72 is ahead of the first counter 71. Then, the count ends and a high level pulse voltage Vup is output (FIG. 10B). On the other hand, the output voltage Vdown of the first counter 71 remains at a low level (FIG. 10D). As a result, the up / down counter 73 increases the value of the frequency control signal Sf (FIG. 10 (e)).
- the amplifier 47 supplies a current proportional to the differential voltage between the frequency control signal Sf and the reference voltage Vref2 to the capacitive element 44, and the reference delay voltage Vd increases.
- the delay amount in the delay unit 50 is reduced, and the on-time, the first and second dead times, and the minimum off-time are reduced.
- the on-width of the on-pulse Pon is narrowed and the on-duty is determined by Vin and Vout, so that the off-width of the off-pulse Poff is also narrowed and the switching frequency is increased.
- the adjustment unit 70A controls the switching frequency so as to be close to the frequency of the reference clock Cref5, so that fluctuations in the switching frequency are reduced.
- the off width of the off pulse Poff is narrowed, and the on-duty is increased.
- the predetermined ON width of the ON pulse Pon is adjusted by the adjusting unit 70A.
- the first counter 71 finishes counting before the second counter 72, and the high level pulse voltage Vdown is output.
- the output voltage Vup of the second counter 72 remains at a low level.
- the up / down counter 73 decreases the value of the frequency control signal Sf.
- the amplifier 47 draws out a current proportional to the differential voltage between the frequency control signal Sf and the reference voltage Vref2 from the capacitive element 44, and the reference delay voltage Vd decreases.
- the delay amount in the delay unit 50 is increased, and the on-time, the first and second dead times, and the minimum off-time are increased.
- the on-width of the on-pulse Pon is widened, and the on-duty is determined by Vin and Vout. Therefore, the off-width of the off-pulse Poff is also widened, and the switching frequency is reduced.
- the adjustment unit 70A controls the switching frequency so as to be close to the frequency of the reference clock Cref5, so that fluctuations in the switching frequency are reduced.
- the frequency of the reference clock Cref5 in the adjustment unit 70A is the same as the frequency of the switching control signal S SWHG , but the ratio between the frequency of the reference clock Cref5 and the frequency of the switching control signal S SWHG is N: M. (M and N are natural numbers).
- the adjustment unit 70A adjusts the predetermined on-width of the on-pulse Pon in the switching control signal S SWHG so that the ratio of the count value of the switching control signal S SWHG and the count value of the reference clock Cref5 is M: N.
- the frequency of the reference clock Cref5 is lower than the frequency of the switching control signal SSWHG . According to this, current consumption can be reduced.
- the first counter 71 counts the ON pulse in the switching control signal S SWHG , but may count the switching control signal S SWLG .
- the reference delay voltage Vd of the DLL unit 40A is adjusted by the adjustment unit 70A in order to make the frequency constant.
- the on-time delay clock Cd 441 of the delay unit 50 is adjusted by the adjustment unit 70A. You may adjust. According to this, the frequency can be made constant by changing only the on-time while keeping the dead time and the minimum offset time constant.
- an n-type MOSFET is used as the switching element 11 in the voltage conversion unit 100, but a p-type MOSFET may be used.
- various transistors such as FETs and bipolar transistors can be applied to the switching elements and transistors in this embodiment.
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Abstract
Description
[第1の実施形態]
Ton=(1/f)×(Vout/Vin)
例えば、Vin=5V、Vout=1Vであり、スイッチング周波数をf=500kHzとしたい場合には、Ton=400nsに設定すればよい。このとき、所望の第1デッドタイム及び所望の第2デッドタイムは40ns程度であることが好ましく、所望のミニマムオフタイムは200ns程度であることが好ましい。
[第2の実施形態]
13 駆動回路
14 コイル
15 容量素子
20 コンパレータ
30 トリガ信号生成部
40,40A DLL部
41 高精度遅延部(DLL基準部)
42 DLL遅延部
421~42m DLL部分遅延部
43 アンプ
44 容量素子
45 DLL比較部
46 DAC
47 アンプ
50 遅延部
51 遅延用遅延部
52 AND回路
531~53m 遅延用部分遅延部
54 カウンタ部
541~54p D-FF部
60 タイミング制御部
61 オフパルス終了用比較部
62 オンパルス開始用比較部
63 オンパルス終了用比較部
64 オフパルス開始用比較部
65 ミニマムオフタイム用比較部
66 インバータ
67 オンパルス用AND回路(オンパルス用論理演算部)
68 オフパルス用AND回路(オフパルス用論理演算部)
70A 調整部
71,72 カウンタ
73 アップダウンカウンタ
100 電圧変換部
200,200A 制御部
Claims (4)
- スイッチング素子を有し、該スイッチング素子を制御信号に応じて制御することによって入力電圧を電圧変換した出力電圧を生成する電圧変換部と、
前記電圧変換部の前記出力電圧を安定化するための前記制御信号を生成する制御部と、
を備え、
前記制御部は、
前記電圧変換部の前記出力電圧が基準電圧より小さくなったことを検出するコンパレータと、
ミニマムオフタイム信号を受けた後であって前記コンパレータからの出力信号を受けたときにトリガ信号を生成するトリガ信号生成部と、
基準クロックを基準遅延量だけ遅延した基準遅延クロックを生成すると共に、当該基準遅延量に応じた値を有する基準遅延信号を生成するDLL部と、
前記DLL部からの前記基準遅延信号に基づいて、前記トリガ信号生成部からの前記トリガ信号から所定の遅延量だけ遅延したトリガ遅延信号、当該トリガ遅延信号から所望の第1デッドタイムに対応した遅延量だけ遅延した第1デッドタイム遅延信号、当該第1デッドタイム遅延信号から所望のオンタイムに対応した遅延量だけ遅延したオンタイム遅延信号、当該オンタイム遅延信号から所望の第2デッドタイムに対応した遅延量だけ遅延した第2デッドタイム遅延信号、及び、当該第2デッドタイム遅延信号から所望のミニマムオフタイムに対応した遅延量だけ遅延したミニマムオフタイム遅延信号を生成する遅延部と、
前記遅延部からの前記トリガ遅延信号に応じて前記制御信号におけるオフパルスの終了時点を決定し、前記遅延部からの前記第1デッドタイム遅延信号に応じて前記制御信号におけるオンパルスの開始時点を決定し、前記遅延部からの前記オンタイム遅延信号に応じて前記オンパルスの終了時点を決定し、前記遅延部からの前記第2デッドタイム遅延信号に応じて前記オフパルスの開始時点を決定し、前記遅延部からの前記ミニマムオフタイム遅延信号に応じて前記ミニマムオフタイム信号を生成するタイミング制御部と、
を有する、
同期整流方式を用いたコンパレータ方式DC-DCコンバータ。 - 前記DLL部は、
前記基準クロックを前記基準遅延量だけ遅延した前記基準遅延クロックを生成するDLL基準部と、
前記基準クロックを前記基準遅延信号に基づいて遅延したDLL遅延クロックを生成するDLL遅延部と、
前記基準遅延クロックの位相と前記DLL遅延クロックの位相との差に応じた値を有する前記基準遅延信号を生成するDLL比較部と、
を有し、
前記DLL遅延クロックの位相が前記基準遅延クロックの位相に一致するように前記基準遅延信号を生成することによって、前記基準遅延量に応じた値を有する前記基準遅延信号を生成する、
請求項1に記載の同期整流方式を用いたコンパレータ方式DC-DCコンバータ。 - 前記遅延部は、
前記DLL部からの前記基準遅延信号に基づいて、前記トリガ信号生成部からの前記トリガ信号から異なる遅延量を有する複数の遅延用遅延クロックを生成する遅延用遅延部と、
前記遅延用遅延部からの前記複数の遅延用遅延クロックを分周した分周クロックを生成するカウンタ部と、
を有し、
前記複数の遅延用遅延クロック及び前記分周クロックから、前記トリガ遅延信号、前記第1デッドタイム遅延信号、前記オンタイム遅延信号、前記第2デッドタイム遅延信号及び前記ミニマムオフタイム遅延信号を決定する、
請求項1に記載の同期整流方式を用いたコンパレータ方式DC-DCコンバータ。 - 前記タイミング制御部は、
前記遅延部からの前記トリガ遅延信号に応じて前記制御信号における前記オフパルスの終了時点を示すオフパルス終了信号を生成するオフパルス終了用比較部と、
前記遅延部からの前記第1デッドタイム遅延信号に応じて前記制御信号における前記オンパルスの開始時点を示すオンパルス開始信号を生成するオンパルス開始用比較部と、
前記遅延部からの前記オンタイム遅延信号に応じて前記オンパルスの終了時点を示すオンパルス終了信号を生成するオンパルス終了用比較部と、
前記遅延部からの前記第2デッドタイム遅延信号に応じて前記オフパルスの開始時点を示すオフパルス開始信号を生成するオフパルス開始用比較部と、
前記遅延部からの前記ミニマムオフタイム遅延信号に応じて前記ミニマムオフタイム信号を生成するミニマムオフタイム用比較部と、
前記オンパルス開始信号と前記オンパルス終了信号との論理演算を行うことによって前記制御信号における前記オンパルスを生成するオンパルス用論理演算部と、
前記オフパルス終了信号と前記オフパルス開始信号との論理演算を行うことによって前記制御信号における前記オフパルスを生成するオフパルス用論理演算部と、
を有する、
請求項1に記載の同期整流方式を用いたコンパレータ方式DC-DCコンバータ。
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KR1020117016661A KR101237581B1 (ko) | 2009-02-10 | 2010-01-06 | 동기 정류 방식을 이용한 콤퍼레이터 방식 dc-dc 컨버터 |
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- 2010-01-06 CN CN201080007123.8A patent/CN102308463B/zh active Active
- 2010-01-06 WO PCT/JP2010/050066 patent/WO2010092843A1/ja active Application Filing
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CN102694462A (zh) * | 2011-03-24 | 2012-09-26 | 株式会社东芝 | Dc-dc变换器控制装置及dc-dc变换器 |
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US9083247B2 (en) | 2011-04-25 | 2015-07-14 | Fairchild Semiconductor Corporation | Synchronous rectifier control techniques for a resonant converter |
CN106688174A (zh) * | 2014-10-03 | 2017-05-17 | 科索株式会社 | 开关电源装置 |
CN106688174B (zh) * | 2014-10-03 | 2019-05-17 | 科索株式会社 | 开关电源装置 |
Also Published As
Publication number | Publication date |
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KR101237581B1 (ko) | 2013-02-26 |
TW201108587A (en) | 2011-03-01 |
CN102308463A (zh) | 2012-01-04 |
KR20110095961A (ko) | 2011-08-25 |
JP2010187437A (ja) | 2010-08-26 |
US20120062201A1 (en) | 2012-03-15 |
US8368374B2 (en) | 2013-02-05 |
JP5315078B2 (ja) | 2013-10-16 |
CN102308463B (zh) | 2014-02-19 |
TWI418131B (zh) | 2013-12-01 |
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