WO2010082781A2 - Dispositif de d'ajustement et tranche sur laquelle ce dispositif est établi - Google Patents

Dispositif de d'ajustement et tranche sur laquelle ce dispositif est établi Download PDF

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Publication number
WO2010082781A2
WO2010082781A2 PCT/KR2010/000259 KR2010000259W WO2010082781A2 WO 2010082781 A2 WO2010082781 A2 WO 2010082781A2 KR 2010000259 W KR2010000259 W KR 2010000259W WO 2010082781 A2 WO2010082781 A2 WO 2010082781A2
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WO
WIPO (PCT)
Prior art keywords
trimming
diode
pad
chip
terminal
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Application number
PCT/KR2010/000259
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English (en)
Korean (ko)
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WO2010082781A3 (fr
Inventor
권성준
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(주)싸이닉솔루션
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Publication of WO2010082781A2 publication Critical patent/WO2010082781A2/fr
Publication of WO2010082781A3 publication Critical patent/WO2010082781A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology

Definitions

  • the present invention relates to a trimming apparatus of a semiconductor manufacturing apparatus, and more particularly, to a trimming apparatus in which a trimming pad is located outside a chip, and a wafer on which a trimming apparatus is formed.
  • a technique of trimming a fusing resistor is used to finely adjust the characteristics of the circuit using a dummy resistor.
  • the fusing resistor is usually composed of a poly resistor, and the resistance is about tens of ohms, and has an electrical property that is disconnected when a momentary voltage or current is applied.
  • a trimming pad for applying a voltage or a current to the fusing resistor is required.
  • One trimming pad is needed for each fusing resistor. The trimming pad will no longer be used after trimming the fusing resistor.
  • the conventional trimming device 100 has a structure in which a fusing resistor RF is directly connected between the trimming pad 110 and the ground, and is applied by applying a high voltage or a large current to the trimming pad 110. Trim the resistor (RF).
  • the trimming pad 110 is positioned inside the semiconductor chip indicated by the dotted line in FIG. 1, and consequently occupies a considerable portion of the chip area. Therefore, there is a disadvantage in that the number of chips per wafer is reduced.
  • FIG. 1 Another prior art proposed to improve this problem of the prior art is shown in FIG.
  • the trimming apparatus shown in FIG. 2 reduces the size of the semiconductor chip by placing the trimming pad 210 in a scribe lane between the chip and the chip indicated by dotted lines.
  • the prior art of FIG. 2 there is a disadvantage that a malfunction may occur in the chip when the remaining portion of the trimming pad cut after the chip cutting is shorted to the wafer substrate.
  • FIG. 3 shows another prior art that solves the problems of the prior art shown in FIG. 3 shows a trimming apparatus 300 in which a MOS switch 310 is added between the trimming pad and the inside of the chip so that the trimming pad 320 does not affect the internal circuit even if the trimming pad 320 is shorted to the wafer substrate after chip cutting. To provide.
  • the device also has a separate trimming mode pad 330 for adjusting the MOS switch.
  • the problem to be solved by the present invention is to reduce the size of the chip by placing the trimming pad in the scribe lane between the chip and the chip, and does not affect the internal circuit even if the trimming pad is shorted to the wafer substrate after chip cutting It is to provide a trimming device.
  • Trimming apparatus of the present invention for solving the above problems, the fusing resistor; A trimming pad located in a scribe lane outside the chip and applying a voltage or current to trim the fusing resistor; And a diode for applying the forward current or voltage to the fusing resistor when a predetermined level or more forward current or voltage is applied from the trimming pad.
  • the trimming device may further include a first load having one terminal connected to the common terminal of the trimming pad and the diode and the other terminal connected to the ground voltage.
  • the trimming apparatus may further include a second load having one terminal connected to a power supply voltage and the other terminal connected to a common terminal of the diode and the fusing resistor; And an inverter for inverting and outputting a voltage output from the common terminal of the diode, the second load, and the fusing resistor.
  • the diode of the trimming apparatus described above may be implemented with an NMOS transistor having a gate and a drain connected to the trimming pad and a source connected to the fusing resistor.
  • the diode of the trimming apparatus described above may be implemented with a PMOS transistor having a gate and a drain connected to the fusing resistor and a source connected to the trimming pad.
  • trimming pads formed in the chip are formed in the space of the scribe lane between the chip and the chip, thereby reducing the area of the chip.
  • the present invention separates the internal circuit and the external by using a diode, even if a part of the pad is disconnected to the substrate of the wafer after sawing, the effect does not affect the internal circuit.
  • the present invention does not require an additional trimming mode pad for adjusting the switch as in the prior art by using a diode instead of the MOS switch of the trimming device of the prior art, thereby simplifying circuit design and layout.
  • 1 to 3 are diagrams illustrating trimming devices according to the prior art, respectively.
  • FIG. 4 is a diagram illustrating a trimming device according to a preferred embodiment of the present invention.
  • 5 and 6 are diagrams showing an example in which the diode shown in FIG. 4 is implemented with a MOS transistor.
  • FIG. 7 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
  • FIGS. 9 and 10 are diagrams showing the layout of a wafer in which the trimming apparatus of the present invention is implemented.
  • Trimming apparatus for solving the above problems is provided with a fusing resistor, trimming pad and diode, the trimming pad is located in the scribe lane outside the chip.
  • the fusing resistor is located inside the chip.
  • the trimming pad applies a voltage or current to trim the fusing resistor.
  • the diode has an anode terminal connected to the trimming pad and a cathode terminal connected to the other terminal of the fusing resistor.
  • the diode may be implemented with a MOS transistor.
  • Trimming apparatus for solving the above problems has a fusing resistor, trimming pad, diode and the first load, the trimming pad is located in the scribe lane outside the chip.
  • the first load is connected to one terminal of the trimming pad and the common terminal of the diode, and the other terminal of the first load is connected to the ground voltage GND.
  • the second load is connected to a common terminal between the diode and the fusing resistor, and the other terminal is connected to a power supply voltage.
  • the inverter inverts and outputs a voltage output from the common terminal of the diode, the fusing resistor, and the second load.
  • the trimming apparatus 400 illustrated in FIG. 4 includes a fuse resistor (RF) and a diode 410 inside the chip and a trim pad 420 outside the chip.
  • the chip has an internal circuit and a corresponding interface circuit, which may be designed for trimming purposes or for testing purposes. When designed for trimming purposes, the interface circuit has a fusing resistor.
  • the fusing resistor RF is located inside the chip, and one terminal is connected to the ground voltage GND.
  • the trimming pad 420 is connected to the anode terminal of the diode 410, and the other terminal of the fusing resistor RF is connected to the cathode terminal of the diode 410.
  • Trimming pad 420 is used to trim the fusing resistor RF using a sufficient voltage or current. When a sufficiently high voltage or current is applied, the diode 410 inside the chip may be turned on without additional adjustment circuits to trim the fusing resistor RF.
  • the trimming pad 420 is located in a scribe lane outside the chip.
  • the scribe lane is a space for separation of a predetermined gap formed between the chip and the chip, and is a part cut during the assembly process.
  • the semiconductor wafer substrate is connected to the ground voltage GND, the scribe lane is cut during the assembly process and the trimming pad is shorted to the wafer substrate (ground voltage GND).
  • the shorting of the trimming pad does not affect the internal circuit because the fusing pad and the internal interface circuit are not connected.
  • the present invention can be turned on and off according to the voltage applied to the fusing pad 420 automatically by the chip internal diode 410 without the need for a separate trimming mode pad as in the conventional trimming apparatus 300. Do.
  • the chip internal diode 410 of FIG. 4 may be variously configured as a MOS transistor.
  • FIG. 5 illustrates a trimming device 500 in which the diode 410 of FIG. 4 is implemented with an NMOS transistor 510 having a gate and a drain connected to a fusing pad 420 and a source connected to a fusing resistor RF.
  • FIG. 6 illustrates a trimming device 600 in which the diode 410 of FIG. 4 is implemented with a PMOS transistor 610 having a gate and a drain connected to a fusing resistor RF and a source connected to a fusing pad 420.
  • FIG. 7 shows a trimming device 700 according to another embodiment of the present invention.
  • the trimming apparatus 700 illustrated in FIG. 7 includes a fusing resistor RF, a trimming pad 420, a diode 410, and a first load 710.
  • the fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode.
  • the trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
  • the diode 410 has an anode terminal connected to the trimming pad 420 and a cathode terminal connected to the other terminal of the fusing resistor RF.
  • the diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
  • the first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND.
  • the first load 710 is a so-called pull-down resistor, and has a resistance value of several hundred kiloohms or more, and sufficient voltage and current are applied to the fusing pad 420 so as not to trim the fusing resistor RF.
  • the anode terminal of the diode 410 is connected to the ground voltage GND to prevent the diode 410 from turning on.
  • FIG. 8 shows a trimming device 800 according to another embodiment of the present invention.
  • the trimming apparatus 800 illustrated in FIG. 8 includes a fusing resistor RF, a trimming pad 420, a diode 410, a first load 710, a second load 810, and an inverter 820.
  • the fusing resistor RF, the trimming pad 420, the diode 410 and the first load 710 are connected in the same manner as shown in FIG. 7.
  • the fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode, the second load 810, and the inverter 820.
  • the trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
  • the diode 410 has an anode terminal connected to the trimming pad 420 and the first load 710, and a cathode terminal connected to the fusing resistor RF, the second load 810, and the inverter 820.
  • the diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
  • the first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND.
  • One terminal of the second load 810 is connected to the common terminal between the diode 410 and the fusing resistor RF, and the other terminal of the second load 810 is connected to a power supply voltage.
  • the inverter 820 inverts and outputs the voltage output from the common terminal of the diode 410, the fusing resistor RF, and the second load 810.
  • the voltage Va applied to the inverter 820 before trimming is turned off because the diode 410 is turned off because sufficient voltage and current are not applied to the fusing pad 420. Since the voltage is output from the common terminal of the fusing resistor RF and the second load 810 between the VDD and the ground voltage GND, it may be calculated according to Equation 1 as follows.
  • Rpu is a resistance value of the second load 820.
  • the second load 810 is a so-called pull-up resistor, has a resistance value of several hundred kiloohms or more, and maintains the inverter 820 output voltage at "HIGH” before trimming the fusing resistor (RF). It is used to
  • the sequence of operations of the trimming device 800 shown in FIG. 8 is as follows.
  • the diode 410 When a sufficiently high voltage and current are applied to the trimming pad 420, the diode 410 is turned on and the fusing resistor RF is disconnected by the voltage or current applied to the fusing pad 420, thereby inputting the inverter 820.
  • the voltage Va becomes the logic "HIGH".
  • the final output voltage of the inverter 820 is logic "LOW".
  • the diode 410 is turned off by the first load 710 so that the final output voltage of the inverter 820 remains logic "LOW”.
  • FIG. 9 shows a layout of a wafer to which a trimming device according to the present invention is applied.
  • the trimming pads 420 are located in a scribe lane outside the chip, and are connected to the inside of each chip by metal lines.
  • the technical idea of the trimming apparatus according to the present invention can be extended to the layout of the wafer.
  • a plurality of chips separated by a scribe lane are formed on a wafer, and at least one internal circuit and an interface circuit corresponding to the internal circuit are formed on each of the plurality of chips.
  • a plurality of pads corresponding to each interface circuit are formed in the scribe lane.
  • the plurality of pads are test pads for internal circuit testing or trimming pads for trimming. If the trimming pad 420 is used for trimming, as illustrated in FIG. 4, the interface circuit includes a fusing resistor RF. In addition, as described with reference to FIG. 4, the interface circuit may further include a diode 410.
  • the first load 710 one terminal is connected to the common terminal of the trimming pad 420 and the diode 410, one terminal described in Figures 7 and 8, the other terminal is connected to the ground voltage 410 and the common terminal of the second load 810 and the second load 810 and the fusing resistor RF, which are connected to the common terminal of the fusing resistor RF and the other terminal of which is connected to the power supply voltage VDD.
  • An inverter 820 may be further provided to invert the output voltage Va.
  • FIG. 10 shows a layout after sawing is completed on the wafer shown in FIG. 9.
  • Sawing of the wafer consists of cutting along a scribe lane formed outside the chip with a diamond knife or the like. When the trimming pad is placed in the scribe lane, a portion of the pad is cut during sawing.
  • the final output may be in an undesired state.
  • the trimming apparatus 800 shown in FIG. 8 is cut after cutting the wafer. Even if a portion of the pad 420 is shorted to the chip of the wafer, the anode of the diode 420 is brought to ground voltage by the first load 710 unless a sufficient voltage and current are applied to turn the diode on. Since it is connected and turned off, the final output voltage of the inverter 820 remains trimmed.
  • the diode 420 has a short circuit with a specific node inside or outside the chip that has a voltage enough to turn on, the final output may be an undesired state, but the conventional trimming device 300 Even in this case, the final output is trimmed.) Since a conventional wafer substrate is short-circuited with the ground voltage GND, even if a part of the trimming pad 410 is short-circuited with the wafer substrate, the diode ( 420 cannot be turned on.

Abstract

L'invention concerne un dispositif d'ajustement et une tranche sur laquelle ce dispositif est établi. Le dispositif selon l'invention a l'avantage de permettre une réduction de la superficie d'une puce par la constitution d'une plage d'ajustement, auparavant située à l'intérieur de la puce, dans l'espace d'une ligne de séparation entre deux puces. L'autre avantage selon l'invention est qu'il n'y a aucune incidence sur le circuit interne même si une partie de la place est détachée sur le substrat de la tranche après découpe, puisque le circuit interne est séparé de l'extérieur par le biais d'une diode. De plus, le fait qu'une diode soit utilisée à la place du commutateur MOS des dispositifs d'ajustement antérieurs, l'invention offre l'avantage de simplifier la conception et la configuration de circuit: en effet, contrairement à l'état antérieur de la technique, il n'est pas nécessaire d'utiliser une plage de mode d'ajustement supplémentaire pour l'ajustement de commutateur.
PCT/KR2010/000259 2009-01-19 2010-01-15 Dispositif de d'ajustement et tranche sur laquelle ce dispositif est établi WO2010082781A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0004012 2009-01-19
KR1020090004012A KR20100084726A (ko) 2009-01-19 2009-01-19 트리밍 장치 및 트리밍 장치가 형성된 웨이퍼

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WO2010082781A2 true WO2010082781A2 (fr) 2010-07-22
WO2010082781A3 WO2010082781A3 (fr) 2010-10-14

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112889151A (zh) * 2019-05-23 2021-06-01 富士电机株式会社 微调电路和微调方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112630628B (zh) * 2021-03-08 2021-05-18 上海伟测半导体科技股份有限公司 多晶硅工艺保险丝的熔断装置及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235908A (ja) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd 抵抗トリミング回路
KR100847011B1 (ko) * 2006-11-08 2008-07-17 주식회사 에이디텍 트리밍 장치 및 칩 외부에 패드가 형성된 웨이퍼

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235908A (ja) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd 抵抗トリミング回路
KR100847011B1 (ko) * 2006-11-08 2008-07-17 주식회사 에이디텍 트리밍 장치 및 칩 외부에 패드가 형성된 웨이퍼

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112889151A (zh) * 2019-05-23 2021-06-01 富士电机株式会社 微调电路和微调方法

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WO2010082781A3 (fr) 2010-10-14
KR20100084726A (ko) 2010-07-28

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