WO2010082781A2 - Trimming device and a wafer on which the trimming device is formed - Google Patents

Trimming device and a wafer on which the trimming device is formed Download PDF

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Publication number
WO2010082781A2
WO2010082781A2 PCT/KR2010/000259 KR2010000259W WO2010082781A2 WO 2010082781 A2 WO2010082781 A2 WO 2010082781A2 KR 2010000259 W KR2010000259 W KR 2010000259W WO 2010082781 A2 WO2010082781 A2 WO 2010082781A2
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trimming
diode
pad
chip
terminal
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PCT/KR2010/000259
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French (fr)
Korean (ko)
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WO2010082781A3 (en
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권성준
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(주)싸이닉솔루션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology

Definitions

  • the present invention relates to a trimming apparatus of a semiconductor manufacturing apparatus, and more particularly, to a trimming apparatus in which a trimming pad is located outside a chip, and a wafer on which a trimming apparatus is formed.
  • a technique of trimming a fusing resistor is used to finely adjust the characteristics of the circuit using a dummy resistor.
  • the fusing resistor is usually composed of a poly resistor, and the resistance is about tens of ohms, and has an electrical property that is disconnected when a momentary voltage or current is applied.
  • a trimming pad for applying a voltage or a current to the fusing resistor is required.
  • One trimming pad is needed for each fusing resistor. The trimming pad will no longer be used after trimming the fusing resistor.
  • the conventional trimming device 100 has a structure in which a fusing resistor RF is directly connected between the trimming pad 110 and the ground, and is applied by applying a high voltage or a large current to the trimming pad 110. Trim the resistor (RF).
  • the trimming pad 110 is positioned inside the semiconductor chip indicated by the dotted line in FIG. 1, and consequently occupies a considerable portion of the chip area. Therefore, there is a disadvantage in that the number of chips per wafer is reduced.
  • FIG. 1 Another prior art proposed to improve this problem of the prior art is shown in FIG.
  • the trimming apparatus shown in FIG. 2 reduces the size of the semiconductor chip by placing the trimming pad 210 in a scribe lane between the chip and the chip indicated by dotted lines.
  • the prior art of FIG. 2 there is a disadvantage that a malfunction may occur in the chip when the remaining portion of the trimming pad cut after the chip cutting is shorted to the wafer substrate.
  • FIG. 3 shows another prior art that solves the problems of the prior art shown in FIG. 3 shows a trimming apparatus 300 in which a MOS switch 310 is added between the trimming pad and the inside of the chip so that the trimming pad 320 does not affect the internal circuit even if the trimming pad 320 is shorted to the wafer substrate after chip cutting. To provide.
  • the device also has a separate trimming mode pad 330 for adjusting the MOS switch.
  • the problem to be solved by the present invention is to reduce the size of the chip by placing the trimming pad in the scribe lane between the chip and the chip, and does not affect the internal circuit even if the trimming pad is shorted to the wafer substrate after chip cutting It is to provide a trimming device.
  • Trimming apparatus of the present invention for solving the above problems, the fusing resistor; A trimming pad located in a scribe lane outside the chip and applying a voltage or current to trim the fusing resistor; And a diode for applying the forward current or voltage to the fusing resistor when a predetermined level or more forward current or voltage is applied from the trimming pad.
  • the trimming device may further include a first load having one terminal connected to the common terminal of the trimming pad and the diode and the other terminal connected to the ground voltage.
  • the trimming apparatus may further include a second load having one terminal connected to a power supply voltage and the other terminal connected to a common terminal of the diode and the fusing resistor; And an inverter for inverting and outputting a voltage output from the common terminal of the diode, the second load, and the fusing resistor.
  • the diode of the trimming apparatus described above may be implemented with an NMOS transistor having a gate and a drain connected to the trimming pad and a source connected to the fusing resistor.
  • the diode of the trimming apparatus described above may be implemented with a PMOS transistor having a gate and a drain connected to the fusing resistor and a source connected to the trimming pad.
  • trimming pads formed in the chip are formed in the space of the scribe lane between the chip and the chip, thereby reducing the area of the chip.
  • the present invention separates the internal circuit and the external by using a diode, even if a part of the pad is disconnected to the substrate of the wafer after sawing, the effect does not affect the internal circuit.
  • the present invention does not require an additional trimming mode pad for adjusting the switch as in the prior art by using a diode instead of the MOS switch of the trimming device of the prior art, thereby simplifying circuit design and layout.
  • 1 to 3 are diagrams illustrating trimming devices according to the prior art, respectively.
  • FIG. 4 is a diagram illustrating a trimming device according to a preferred embodiment of the present invention.
  • 5 and 6 are diagrams showing an example in which the diode shown in FIG. 4 is implemented with a MOS transistor.
  • FIG. 7 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
  • FIG. 8 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
  • FIGS. 9 and 10 are diagrams showing the layout of a wafer in which the trimming apparatus of the present invention is implemented.
  • Trimming apparatus for solving the above problems is provided with a fusing resistor, trimming pad and diode, the trimming pad is located in the scribe lane outside the chip.
  • the fusing resistor is located inside the chip.
  • the trimming pad applies a voltage or current to trim the fusing resistor.
  • the diode has an anode terminal connected to the trimming pad and a cathode terminal connected to the other terminal of the fusing resistor.
  • the diode may be implemented with a MOS transistor.
  • Trimming apparatus for solving the above problems has a fusing resistor, trimming pad, diode and the first load, the trimming pad is located in the scribe lane outside the chip.
  • the first load is connected to one terminal of the trimming pad and the common terminal of the diode, and the other terminal of the first load is connected to the ground voltage GND.
  • the second load is connected to a common terminal between the diode and the fusing resistor, and the other terminal is connected to a power supply voltage.
  • the inverter inverts and outputs a voltage output from the common terminal of the diode, the fusing resistor, and the second load.
  • the trimming apparatus 400 illustrated in FIG. 4 includes a fuse resistor (RF) and a diode 410 inside the chip and a trim pad 420 outside the chip.
  • the chip has an internal circuit and a corresponding interface circuit, which may be designed for trimming purposes or for testing purposes. When designed for trimming purposes, the interface circuit has a fusing resistor.
  • the fusing resistor RF is located inside the chip, and one terminal is connected to the ground voltage GND.
  • the trimming pad 420 is connected to the anode terminal of the diode 410, and the other terminal of the fusing resistor RF is connected to the cathode terminal of the diode 410.
  • Trimming pad 420 is used to trim the fusing resistor RF using a sufficient voltage or current. When a sufficiently high voltage or current is applied, the diode 410 inside the chip may be turned on without additional adjustment circuits to trim the fusing resistor RF.
  • the trimming pad 420 is located in a scribe lane outside the chip.
  • the scribe lane is a space for separation of a predetermined gap formed between the chip and the chip, and is a part cut during the assembly process.
  • the semiconductor wafer substrate is connected to the ground voltage GND, the scribe lane is cut during the assembly process and the trimming pad is shorted to the wafer substrate (ground voltage GND).
  • the shorting of the trimming pad does not affect the internal circuit because the fusing pad and the internal interface circuit are not connected.
  • the present invention can be turned on and off according to the voltage applied to the fusing pad 420 automatically by the chip internal diode 410 without the need for a separate trimming mode pad as in the conventional trimming apparatus 300. Do.
  • the chip internal diode 410 of FIG. 4 may be variously configured as a MOS transistor.
  • FIG. 5 illustrates a trimming device 500 in which the diode 410 of FIG. 4 is implemented with an NMOS transistor 510 having a gate and a drain connected to a fusing pad 420 and a source connected to a fusing resistor RF.
  • FIG. 6 illustrates a trimming device 600 in which the diode 410 of FIG. 4 is implemented with a PMOS transistor 610 having a gate and a drain connected to a fusing resistor RF and a source connected to a fusing pad 420.
  • FIG. 7 shows a trimming device 700 according to another embodiment of the present invention.
  • the trimming apparatus 700 illustrated in FIG. 7 includes a fusing resistor RF, a trimming pad 420, a diode 410, and a first load 710.
  • the fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode.
  • the trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
  • the diode 410 has an anode terminal connected to the trimming pad 420 and a cathode terminal connected to the other terminal of the fusing resistor RF.
  • the diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
  • the first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND.
  • the first load 710 is a so-called pull-down resistor, and has a resistance value of several hundred kiloohms or more, and sufficient voltage and current are applied to the fusing pad 420 so as not to trim the fusing resistor RF.
  • the anode terminal of the diode 410 is connected to the ground voltage GND to prevent the diode 410 from turning on.
  • FIG. 8 shows a trimming device 800 according to another embodiment of the present invention.
  • the trimming apparatus 800 illustrated in FIG. 8 includes a fusing resistor RF, a trimming pad 420, a diode 410, a first load 710, a second load 810, and an inverter 820.
  • the fusing resistor RF, the trimming pad 420, the diode 410 and the first load 710 are connected in the same manner as shown in FIG. 7.
  • the fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode, the second load 810, and the inverter 820.
  • the trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
  • the diode 410 has an anode terminal connected to the trimming pad 420 and the first load 710, and a cathode terminal connected to the fusing resistor RF, the second load 810, and the inverter 820.
  • the diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
  • the first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND.
  • One terminal of the second load 810 is connected to the common terminal between the diode 410 and the fusing resistor RF, and the other terminal of the second load 810 is connected to a power supply voltage.
  • the inverter 820 inverts and outputs the voltage output from the common terminal of the diode 410, the fusing resistor RF, and the second load 810.
  • the voltage Va applied to the inverter 820 before trimming is turned off because the diode 410 is turned off because sufficient voltage and current are not applied to the fusing pad 420. Since the voltage is output from the common terminal of the fusing resistor RF and the second load 810 between the VDD and the ground voltage GND, it may be calculated according to Equation 1 as follows.
  • Rpu is a resistance value of the second load 820.
  • the second load 810 is a so-called pull-up resistor, has a resistance value of several hundred kiloohms or more, and maintains the inverter 820 output voltage at "HIGH” before trimming the fusing resistor (RF). It is used to
  • the sequence of operations of the trimming device 800 shown in FIG. 8 is as follows.
  • the diode 410 When a sufficiently high voltage and current are applied to the trimming pad 420, the diode 410 is turned on and the fusing resistor RF is disconnected by the voltage or current applied to the fusing pad 420, thereby inputting the inverter 820.
  • the voltage Va becomes the logic "HIGH".
  • the final output voltage of the inverter 820 is logic "LOW".
  • the diode 410 is turned off by the first load 710 so that the final output voltage of the inverter 820 remains logic "LOW”.
  • FIG. 9 shows a layout of a wafer to which a trimming device according to the present invention is applied.
  • the trimming pads 420 are located in a scribe lane outside the chip, and are connected to the inside of each chip by metal lines.
  • the technical idea of the trimming apparatus according to the present invention can be extended to the layout of the wafer.
  • a plurality of chips separated by a scribe lane are formed on a wafer, and at least one internal circuit and an interface circuit corresponding to the internal circuit are formed on each of the plurality of chips.
  • a plurality of pads corresponding to each interface circuit are formed in the scribe lane.
  • the plurality of pads are test pads for internal circuit testing or trimming pads for trimming. If the trimming pad 420 is used for trimming, as illustrated in FIG. 4, the interface circuit includes a fusing resistor RF. In addition, as described with reference to FIG. 4, the interface circuit may further include a diode 410.
  • the first load 710 one terminal is connected to the common terminal of the trimming pad 420 and the diode 410, one terminal described in Figures 7 and 8, the other terminal is connected to the ground voltage 410 and the common terminal of the second load 810 and the second load 810 and the fusing resistor RF, which are connected to the common terminal of the fusing resistor RF and the other terminal of which is connected to the power supply voltage VDD.
  • An inverter 820 may be further provided to invert the output voltage Va.
  • FIG. 10 shows a layout after sawing is completed on the wafer shown in FIG. 9.
  • Sawing of the wafer consists of cutting along a scribe lane formed outside the chip with a diamond knife or the like. When the trimming pad is placed in the scribe lane, a portion of the pad is cut during sawing.
  • the final output may be in an undesired state.
  • the trimming apparatus 800 shown in FIG. 8 is cut after cutting the wafer. Even if a portion of the pad 420 is shorted to the chip of the wafer, the anode of the diode 420 is brought to ground voltage by the first load 710 unless a sufficient voltage and current are applied to turn the diode on. Since it is connected and turned off, the final output voltage of the inverter 820 remains trimmed.
  • the diode 420 has a short circuit with a specific node inside or outside the chip that has a voltage enough to turn on, the final output may be an undesired state, but the conventional trimming device 300 Even in this case, the final output is trimmed.) Since a conventional wafer substrate is short-circuited with the ground voltage GND, even if a part of the trimming pad 410 is short-circuited with the wafer substrate, the diode ( 420 cannot be turned on.

Abstract

Disclosed are a trimming device and a wafer on which the trimming device is formed. The trimming device of the present invention presents the advantage of reducing the surface area of a chip by forming a trimming pad, which used to be inside the chip, in the space of a scribe lane between one chip and another chip. Further, the present invention presents the advantage that there is no effect on the internal circuit even if part of the pad is severed on the substrate of the wafer after sawing, since the internal circuit is separated from the outside by means of a diode. Further, because a diode is used instead of the MOS switch found in trimming devices of the prior art, the present invention presents the advantage that circuit design and layout are simplified since, unlike the prior art, there is no need for an additional trimming mode pad for switch adjustment.

Description

트리밍 장치 및 트리밍 장치가 형성된 웨이퍼Wafer with Trimming Device and Trimming Device
본 발명은 반도체 제조장치 중 트리밍 장치에 관한 것으로, 더욱 상세하게는 트리밍 패드가 칩 외부에 위치하는 트리밍 장치 및 트리밍 장치가 형성된 웨이퍼에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trimming apparatus of a semiconductor manufacturing apparatus, and more particularly, to a trimming apparatus in which a trimming pad is located outside a chip, and a wafer on which a trimming apparatus is formed.
집적회로를 테스트하는 과정에서 더미(Dummy) 저항 등을 이용하여 회로의 특성을 정교하게 조정하기 위해서 퓨징(Fusing) 저항을 트리밍(Trimming)하는 기법을 사용한다. 퓨징 저항은 보통 폴리 저항으로 구성되며, 저항은 수십 옴(Ω) 정도이며, 순간적인 전압이나 전류를 인가하면 단선되는 전기적 성질을 가진다.In the process of testing an integrated circuit, a technique of trimming a fusing resistor is used to finely adjust the characteristics of the circuit using a dummy resistor. The fusing resistor is usually composed of a poly resistor, and the resistance is about tens of ohms, and has an electrical property that is disconnected when a momentary voltage or current is applied.
반도체 회로에서 퓨징 저항을 트리밍하기 위해서는, 퓨징 저항에 전압이나 전류를 인가하기 위한 트리밍 패드를 필요로 한다. 트리밍 패드는 퓨징 저항마다 하나씩 필요하게 된다. 트리밍 패드는 퓨징 저항을 트리밍을 한 후에는 더 이상 사용하지 않게 된다.In order to trim the fusing resistor in the semiconductor circuit, a trimming pad for applying a voltage or a current to the fusing resistor is required. One trimming pad is needed for each fusing resistor. The trimming pad will no longer be used after trimming the fusing resistor.
도 1은 종래의 트리밍 장치(100)를 나타낸다. 도 1을 참조하면, 종래의 트리밍 장치(100)는 퓨징 저항(RF)이 트리밍 패드(110)와 그라운드 사이에 직접 연결되는 구조이며, 트리밍 패드(110)에 높은 전압이나 큰 전류를 인가하여 퓨징 저항(RF)을 트리밍한다. 1 shows a conventional trimming device 100. Referring to FIG. 1, the conventional trimming device 100 has a structure in which a fusing resistor RF is directly connected between the trimming pad 110 and the ground, and is applied by applying a high voltage or a large current to the trimming pad 110. Trim the resistor (RF).
그러나, 종래의 트리밍 장치(100)에서 트리밍 패드(110)는 도 1에서 점선으로 표시된 반도체칩 내부에 위치하게 되어, 결과적으로, 칩 면적에서 상당히 큰 부분을 차지하게 된다. 따라서, 웨이퍼 당 칩 개수가 감소되는 단점이 있다. 이러한 종래기술의 문제점을 개선하기 위해 제안된 다른 종래기술이 도 2 에 도시되었다.However, in the conventional trimming apparatus 100, the trimming pad 110 is positioned inside the semiconductor chip indicated by the dotted line in FIG. 1, and consequently occupies a considerable portion of the chip area. Therefore, there is a disadvantage in that the number of chips per wafer is reduced. Another prior art proposed to improve this problem of the prior art is shown in FIG.
도 2에 도시된 트리밍 장치는, 트리밍 패드(210)를 점선으로 표시된 칩과 칩 사이의 스크라이브 레인(Scribe Lane)에 위치시킴으로써 반도체 칩의 사이즈를 감소시켰다. 그러나, 도 2 의 종래기술의 경우에, 칩 절단 후에 절단된 트리밍 패드의 남은 부분이 웨이퍼 기판에 단락되는 경우 칩에 오동작을 일으킬 수 있는 단점이 있다.The trimming apparatus shown in FIG. 2 reduces the size of the semiconductor chip by placing the trimming pad 210 in a scribe lane between the chip and the chip indicated by dotted lines. However, in the case of the prior art of FIG. 2, there is a disadvantage that a malfunction may occur in the chip when the remaining portion of the trimming pad cut after the chip cutting is shorted to the wafer substrate.
도 3 은 도 2 에 도시된 종래 기술의 문제점을 해결하는 다른 종래기술을 도시한다. 도 3 에 도시된 종래기술은, 칩 절단 후에 트리밍 패드(320)가 웨이퍼 기판에 단락되더라도 내부회로에 영향을 주지 않도록 트리밍 패드와 칩 내부 사이에 MOS 스위치(310)를 추가한 트리밍 장치(300)를 제공한다. 이 장치는 또한 MOS 스위치를 조정하기 위한 별도의 트리밍 모드 패드(330)를 더 구비한다.3 shows another prior art that solves the problems of the prior art shown in FIG. 3 shows a trimming apparatus 300 in which a MOS switch 310 is added between the trimming pad and the inside of the chip so that the trimming pad 320 does not affect the internal circuit even if the trimming pad 320 is shorted to the wafer substrate after chip cutting. To provide. The device also has a separate trimming mode pad 330 for adjusting the MOS switch.
그러나, 이러한 종래 기술은 MOS 스위치를 제어하기 위한 트리밍 모드 패드(330)를 추가적으로 설치하여야 하므로 회로 설계 및 레이아웃이 복잡해지고, 반도체 공정상 추가적인 공정이 수행되어 제조 비용이 상승하는 문제점이 존재한다.However, such a conventional technology requires an additional trimming mode pad 330 for controlling the MOS switch, which complicates the circuit design and layout, and increases the manufacturing cost due to the additional process performed in the semiconductor process.
본 발명이 해결하자 하는 과제는 트리밍 패드를 칩과 칩 사이의 스크라이브 레인(Scribe Lane)에 위치시켜 칩 사이즈를 줄일 수 있으며, 칩 절단 후에 트리밍 패드가 웨이퍼 기판에 단락되더라도 내부회로에 영향을 주지 않는 트리밍 장치를 제공하는 것이다.The problem to be solved by the present invention is to reduce the size of the chip by placing the trimming pad in the scribe lane between the chip and the chip, and does not affect the internal circuit even if the trimming pad is shorted to the wafer substrate after chip cutting It is to provide a trimming device.
상술한 과제를 해결하기 위한 본 발명의 트리밍 장치는, 퓨징 저항; 칩 외부의 스크라이브 레인(scribe lane)에 위치하고, 상기 퓨징 저항을 트리밍하기 위한 전압 또는 전류를 인가하는 트리밍 패드; 및 상기 트리밍 패드로부터 일정 레벨 이상의 순방향 전류 또는 전압이 인가되면, 상기 순방향 전류 또는 전압을 상기 퓨징 저항으로 인가하는 다이오드를 포함한다.Trimming apparatus of the present invention for solving the above problems, the fusing resistor; A trimming pad located in a scribe lane outside the chip and applying a voltage or current to trim the fusing resistor; And a diode for applying the forward current or voltage to the fusing resistor when a predetermined level or more forward current or voltage is applied from the trimming pad.
또한, 상술한 트리밍 장치는, 일 단자가 상기 트리밍 패드와 상기 다이오드의 공통단자에 연결되고, 다른 일 단자가 접지 전압에 연결되는 제 1 부하를 더 포함할 수 있다.The trimming device may further include a first load having one terminal connected to the common terminal of the trimming pad and the diode and the other terminal connected to the ground voltage.
또한, 상술한 트리밍 장치는, 일 단자가 전원 전압과 연결되고, 다른 일 단자가 상기 다이오드와 상기 퓨징 저항의 공통단자에 연결되는 제 2 부하; 및 상기 다이오드, 상기 제 2 부하 및 상기 퓨징 저항의 공통 단자로부터 출력되는 전압을 반전시켜 출력하는 인버터를 더 포함할 수 있다.The trimming apparatus may further include a second load having one terminal connected to a power supply voltage and the other terminal connected to a common terminal of the diode and the fusing resistor; And an inverter for inverting and outputting a voltage output from the common terminal of the diode, the second load, and the fusing resistor.
또한, 상술한 트리밍 장치의 다이오드는 게이트 및 드레인이 상기 트리밍 패드에 연결되고, 소스가 상기 퓨징 저항에 연결된 NMOS 트랜지스터로 구현될 수 있다.In addition, the diode of the trimming apparatus described above may be implemented with an NMOS transistor having a gate and a drain connected to the trimming pad and a source connected to the fusing resistor.
또한, 상술한 트리밍 장치의 다이오드는 게이트 및 드레인이 상기 퓨징 저항에 연결되고, 소스가 상기 트리밍 패드에 연결된 PMOS 트랜지스터로 구현될 수 있다.In addition, the diode of the trimming apparatus described above may be implemented with a PMOS transistor having a gate and a drain connected to the fusing resistor and a source connected to the trimming pad.
본 발명에 따른 트리밍 장치는 칩 내부에 있던 트리밍 패드를 칩과 칩 사이의 스크라이브 레인의 공간에 형성함으로써 칩의 면적을 줄이는 효과가 나타난다.In the trimming apparatus according to the present invention, trimming pads formed in the chip are formed in the space of the scribe lane between the chip and the chip, thereby reducing the area of the chip.
또한, 본 발명은 다이오드를 이용하여 내부 회로와 외부를 분리시킴으로써, 소우잉(sawing)후 패드의 일부가 웨이퍼의 기판에 단선되더라도, 내부회로에 영향을 주지 않는 효과가 나타난다.In addition, the present invention separates the internal circuit and the external by using a diode, even if a part of the pad is disconnected to the substrate of the wafer after sawing, the effect does not affect the internal circuit.
또한, 본 발명은 종래 기술의 트리밍 장치의 MOS 스위치 대신 다이오드를 사용하여 종래 기술과 같이 스위치를 조정하기 위한 추가적인 트리밍 모드 패드가 필요 없으므로, 회로 설계 및 레이아웃이 간편해 지는 효과가 있다.In addition, the present invention does not require an additional trimming mode pad for adjusting the switch as in the prior art by using a diode instead of the MOS switch of the trimming device of the prior art, thereby simplifying circuit design and layout.
도 1 내지 도 3 은 종래 기술에 따른 트리밍 장치들을 각각 도시하는 도면이다.1 to 3 are diagrams illustrating trimming devices according to the prior art, respectively.
도 4 는 본 발명의 바람직한 실시예에 따른 트리밍 장치를 도시한 도면이다.4 is a diagram illustrating a trimming device according to a preferred embodiment of the present invention.
도 5 및 도 6 은 도 4 에 도시된 다이오드를 MOS 트랜지스터로 구현한 예를 도시하는 도면이다.5 and 6 are diagrams showing an example in which the diode shown in FIG. 4 is implemented with a MOS transistor.
도 7 는 본 발명의 바람직한 다른 실시예에 따른 트리밍 장치를 도시한 도면이다.7 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
도 8 는 본 발명의 바람직한 다른 실시예에 따른 트리밍 장치를 도시한 도면이다.8 is a diagram illustrating a trimming device according to another exemplary embodiment of the present invention.
도 9 및 도 10 은 본 발명의 트리밍 장치가 구현된 웨이퍼의 레이아웃을 도시하는 도면이다. 9 and 10 are diagrams showing the layout of a wafer in which the trimming apparatus of the present invention is implemented.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예들을 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
상기 과제를 해결하기 위한 본 발명의 일실시예에 따른 트리밍 장치는 퓨징 저항, 트리밍 패드 및 다이오드를 구비하고, 트리밍 패드는 칩 외부의 스크라이브 레인에 위치한다. 상기 퓨징 저항은 칩 내부에 위치한다. 상기 트리밍 패드는 상기 퓨징 저항을 트리밍하기 위한 전압 또는 전류를 인가한다. 상기 다이오드는 애노드(Anode) 단자가 상기 트리밍 패드에 연결되고, 캐소드(Cathod) 단자가 상기 퓨징 저항의 다른 일단자에 연결된다. 상기 다이오드는 MOS 트랜지스터로 구현할 수 있다.Trimming apparatus according to an embodiment of the present invention for solving the above problems is provided with a fusing resistor, trimming pad and diode, the trimming pad is located in the scribe lane outside the chip. The fusing resistor is located inside the chip. The trimming pad applies a voltage or current to trim the fusing resistor. The diode has an anode terminal connected to the trimming pad and a cathode terminal connected to the other terminal of the fusing resistor. The diode may be implemented with a MOS transistor.
상기 과제를 해결하기 위한 본 발명의 다른 일실시예에 따른 트리밍 장치는 퓨징 저항, 트리밍 패드, 다이오드 및 제1부하를 구비하고, 상기 트리밍 패드는 칩 외부의 스크라이브 레인에 위치한다. 상기 제1부하는 일 단자가 트리밍 패드와 다이오드의 공통단자에 연결되고, 다른 일 단자가 접지전압(GND)에 연결된다.Trimming apparatus according to another embodiment of the present invention for solving the above problems has a fusing resistor, trimming pad, diode and the first load, the trimming pad is located in the scribe lane outside the chip. The first load is connected to one terminal of the trimming pad and the common terminal of the diode, and the other terminal of the first load is connected to the ground voltage GND.
상기 과제를 해결하기 위한 본 발명의 또 다른 일실시예에 따른 트리밍 장치는 퓨징 저항, 트리밍 패드, 다이오드, 제1부하, 제2부하 및 인버터를 구비하고 상기 트리밍 패드는 칩 외부의 스크라이브 레인에 위치한다.The trimming device according to another embodiment of the present invention for solving the above problems comprises a fusing resistor, a trimming pad, a diode, a first load, a second load and an inverter and the trimming pad is located in a scribe lane outside the chip. do.
상기 제2부하는 일 단자가 상기 다이오드 및 상기 퓨징 저항 사이의 공통단자에 연결되고, 다른 일 단자가 전원전압에 연결된다. 상기 인버터는 상기 다이오드, 상기 퓨징 저항 및 상기 제2부하의 공통단자로부터 출력되는 전압을 반전하여 출력한다.The second load is connected to a common terminal between the diode and the fusing resistor, and the other terminal is connected to a power supply voltage. The inverter inverts and outputs a voltage output from the common terminal of the diode, the fusing resistor, and the second load.
이하에서는 본 발명의 구체적인 실시예를 도면을 참조하여 상세히 설명하도록 한다.Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명의 일실시예에 따른 트리밍 장치(400)를 나타낸다. 도 4에 도시된 트리밍 장치(400)는 칩 내부의 퓨징 저항(RF) 및 다이오드(410)와 칩 외부의 트리밍 패드(420)를 구비한다. 칩은 내부회로와 이에 대응하는 인터페이스 회로를 구비하는데, 인터페이스 회로는 트리밍을 목적으로 설계할 수도 있고, 테스트 목적으로 설계할 수도 있다. 트리밍을 목적으로 설계한 경우에 인터페이스 회로는 퓨징 저항을 구비한다.4 shows a trimming device 400 according to an embodiment of the present invention. The trimming apparatus 400 illustrated in FIG. 4 includes a fuse resistor (RF) and a diode 410 inside the chip and a trim pad 420 outside the chip. The chip has an internal circuit and a corresponding interface circuit, which may be designed for trimming purposes or for testing purposes. When designed for trimming purposes, the interface circuit has a fusing resistor.
퓨징 저항(RF)은 칩 내부에 위치하며, 일 단자가 접지전압(GND)과 연결되어 있다. 트리밍 패드(420)는 다이오드(410)의 애노드 단자와 연결되어 있으며 퓨징 저항(RF)의 다른 일 단자는 다이오드(410)의 캐소드 단자와 연결되어 있다. The fusing resistor RF is located inside the chip, and one terminal is connected to the ground voltage GND. The trimming pad 420 is connected to the anode terminal of the diode 410, and the other terminal of the fusing resistor RF is connected to the cathode terminal of the diode 410.
트리밍 패드(420)는 충분한 전압이나 전류를 이용하여 퓨징 저항(RF)을 트리밍하기 위해 사용된다. 충분히 높은 전압이나 전류를 인가하면 칩 내부의 다이오드(410)가 별도의 추가 조정회로 없이 턴 온(Turn On)되어 퓨징 저항(RF)을 트리밍 하는 것이 가능하다. Trimming pad 420 is used to trim the fusing resistor RF using a sufficient voltage or current. When a sufficiently high voltage or current is applied, the diode 410 inside the chip may be turned on without additional adjustment circuits to trim the fusing resistor RF.
특히, 트리밍 패드(420)는 칩(Chip) 외부의 스크라이브 레인(Scribe lane)에 위치한다. 스크라이브 레인은 칩과 칩 사이에 형성된 일정한 간격의 분리를 위한 공간으로, 조립과정에서 절단되는 부분이다.In particular, the trimming pad 420 is located in a scribe lane outside the chip. The scribe lane is a space for separation of a predetermined gap formed between the chip and the chip, and is a part cut during the assembly process.
통상적으로 반도체 웨이퍼 기판은 접지전압(GND)과 연결되어 있기 때문에 조립과정에서 스크라이브 레인이 절단되고 트리밍 패드가 웨이퍼 기판(접지전압 GND)과 단락되어도, 칩 내부의 다이오드(410)에 의하여, 절단된 퓨징 패드와 내부 인터페이스 회로가 연결이 되지 않기 때문에 트리밍 패드의 단락이 내부 회로에 영향을 주지 않는다.In general, since the semiconductor wafer substrate is connected to the ground voltage GND, the scribe lane is cut during the assembly process and the trimming pad is shorted to the wafer substrate (ground voltage GND). The shorting of the trimming pad does not affect the internal circuit because the fusing pad and the internal interface circuit are not connected.
따라서, 본 발명은 종래의 트리밍 장치(300)와 같이 별도의 트리밍 모드 패드가 필요 없이 칩 내부 다이오드(410)에 의하여 자동적으로 퓨징 패드(420)에 인가되는 전압에 따라 턴 온, 턴 오프가 가능하다.Accordingly, the present invention can be turned on and off according to the voltage applied to the fusing pad 420 automatically by the chip internal diode 410 without the need for a separate trimming mode pad as in the conventional trimming apparatus 300. Do.
도 4의 칩 내부 다이오드(410)는 MOS 트랜지스터로 다양하게 구성될 수 있다. 도 5는 도 4의 다이오드(410)를 게이트와 드레인이 퓨징 패드(420)에 연결되고 소스는 퓨징 저항(RF)에 연결된 NMOS 트랜지스터(510)로 구현한 트리밍 장치(500)를 나타낸다.The chip internal diode 410 of FIG. 4 may be variously configured as a MOS transistor. FIG. 5 illustrates a trimming device 500 in which the diode 410 of FIG. 4 is implemented with an NMOS transistor 510 having a gate and a drain connected to a fusing pad 420 and a source connected to a fusing resistor RF.
도 6은 도 4의 다이오드(410)를 게이트와 드레인이 퓨징 저항(RF)에 연결되고 소스는 퓨징 패드(420)에 연결된 PMOS 트랜지스터(610)로 구현한 트리밍 장치(600)를 나타낸다.FIG. 6 illustrates a trimming device 600 in which the diode 410 of FIG. 4 is implemented with a PMOS transistor 610 having a gate and a drain connected to a fusing resistor RF and a source connected to a fusing pad 420.
도 7은 본 발명의 다른 일실시예에 따른 트리밍 장치(700)를 나타낸다. 7 shows a trimming device 700 according to another embodiment of the present invention.
도 7에 도시된 트리밍 장치(700)는 퓨징 저항(RF), 트리밍 패드(420), 다이오드(410) 및 제1부하(710)을 구비한다. The trimming apparatus 700 illustrated in FIG. 7 includes a fusing resistor RF, a trimming pad 420, a diode 410, and a first load 710.
퓨징 저항(RF)은 일 단자가 접지전압(GND)에 연결되고, 다른 일 단자는 다이오드의 캐소드 단자와 연결된다.The fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode.
트리밍 패드(420)는 다이오드의 애노드 단자와 연결되어, 퓨징저항(RF)을 트리밍 하기 위한 충분한 전압이나 전류를 퓨징저항(RF)에 인가한다. 트리밍 패드(420)는 칩 외부의 스크라이브 레인에 위치한다. The trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
다이오드(410)는 애노드 단자가 상기 트리밍 패드(420)와 연결되고, 캐소드 단자가 상기 퓨징 저항(RF)의 다른 일단자에 연결된다. 여기서 다이오드(420)는 도 5 및 도 6을 참조하여 설명한 바와 같이 MOS 트랜지스터로 구현할 수 있다. The diode 410 has an anode terminal connected to the trimming pad 420 and a cathode terminal connected to the other terminal of the fusing resistor RF. The diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
제 1 부하는 일 단자가 트리밍 패드(420)와 다이오드(410)의 공통단자에 연결되고, 다른 일 단자가 접지전압(GND)에 연결된다. 제 1 부하(710)는 이른바 풀다운(pull-down) 저항으로, 수백 킬로옴(㏀) 이상의 저항값을 가지며 퓨징 패드(420)에 충분한 전압 및 전류가 인가되어 퓨징 저항(RF)을 트리밍하지 않는 경우 다이오드(410)의 애노드 단자를 접지전압(GND)으로 연결하여 다이오드(410)가 턴 온 되지 않도록 막는 역할을 한다.The first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND. The first load 710 is a so-called pull-down resistor, and has a resistance value of several hundred kiloohms or more, and sufficient voltage and current are applied to the fusing pad 420 so as not to trim the fusing resistor RF. In this case, the anode terminal of the diode 410 is connected to the ground voltage GND to prevent the diode 410 from turning on.
도 8은 본 발명의 또 다른 일실시예에 따른 트리밍 장치(800)를 나타낸다.8 shows a trimming device 800 according to another embodiment of the present invention.
도 8에 도시된 트리밍 장치(800)는 퓨징 저항(RF), 트리밍 패드(420), 다이오드(410), 제 1 부하(710), 제 2 부하(810) 및 인버터(820)를 구비한다. The trimming apparatus 800 illustrated in FIG. 8 includes a fusing resistor RF, a trimming pad 420, a diode 410, a first load 710, a second load 810, and an inverter 820.
퓨징 저항(RF), 트리밍 패드(420), 다이오드(410) 및 제 1 부하(710)는 도 7 에 도시된 바와 동일한 방식으로 연결된다.The fusing resistor RF, the trimming pad 420, the diode 410 and the first load 710 are connected in the same manner as shown in FIG. 7.
즉, 퓨징 저항(RF)은 일 단자가 접지전압(GND)에 연결되고, 다른 일 단자는 다이오드의 캐소드 단자, 제 2 부하(810) 및 인버터(820)와 연결된다.That is, the fusing resistor RF has one terminal connected to the ground voltage GND, and the other terminal connected to the cathode terminal of the diode, the second load 810, and the inverter 820.
트리밍 패드(420)는 다이오드의 애노드 단자와 연결되어, 퓨징저항(RF)을 트리밍 하기 위한 충분한 전압이나 전류를 퓨징저항(RF)에 인가한다. 트리밍 패드(420)는 칩 외부의 스크라이브 레인에 위치한다. The trimming pad 420 is connected to the anode terminal of the diode and applies sufficient voltage or current to the fusing resistor RF to trim the fusing resistor RF. Trimming pad 420 is located in the scribe lane outside the chip.
다이오드(410)는 애노드 단자가 상기 트리밍 패드(420) 및 제 1 부하(710)와 연결되고, 캐소드 단자가 상기 퓨징 저항(RF), 제 2 부하(810) 및 인버터(820)와 연결된다. 여기서 다이오드(420)는 도 5 및 도 6을 참조하여 설명한 바와 같이 MOS 트랜지스터로 구현할 수 있다. The diode 410 has an anode terminal connected to the trimming pad 420 and the first load 710, and a cathode terminal connected to the fusing resistor RF, the second load 810, and the inverter 820. The diode 420 may be implemented as a MOS transistor as described with reference to FIGS. 5 and 6.
제 1 부하는 일 단자가 트리밍 패드(420)와 다이오드(410)의 공통단자에 연결되고, 다른 일 단자가 접지전압(GND)에 연결된다.The first load is connected to one terminal of the trimming pad 420 and the common terminal of the diode 410, and the other terminal of the first load is connected to the ground voltage GND.
제 2 부하(810)는 일 단자가 상기 다이오드(410) 및 상기 퓨징 저항(RF) 사이의 공통단자에 연결되고, 다른 일 단자가 전원전압에 연결된다. One terminal of the second load 810 is connected to the common terminal between the diode 410 and the fusing resistor RF, and the other terminal of the second load 810 is connected to a power supply voltage.
인버터(820)는 다이오드(410), 퓨징 저항(RF) 및 제 2 부하(810)의 공통단자로부터 출력되는 전압을 반전하여 출력한다.The inverter 820 inverts and outputs the voltage output from the common terminal of the diode 410, the fusing resistor RF, and the second load 810.
도 8 에 도시된 실시예에서, 트리밍 전에 인버터(820)에 인가되는 전압(Va)는, 퓨징 패드(420)에 충분한 전압 및 전류가 인가되지 않기 때문에 다이오드(410)가 턴 오프되어, 전원전압(VDD)과 접지전압(GND) 사이에서 퓨징 저항(RF) 및 제 2 부하(810)의 공통단자로부터 출력되는 전압이므로, 다음과 같이 수학식 1 에 따라서 계산될 수 있다.In the embodiment shown in FIG. 8, the voltage Va applied to the inverter 820 before trimming is turned off because the diode 410 is turned off because sufficient voltage and current are not applied to the fusing pad 420. Since the voltage is output from the common terminal of the fusing resistor RF and the second load 810 between the VDD and the ground voltage GND, it may be calculated according to Equation 1 as follows.
수학식 1
Figure PCTKR2010000259-appb-M000001
 Equation 1
Figure PCTKR2010000259-appb-M000001
여기서, Rpu는 제 2 부하(820)의 저항값이다. 제 2 부하(810)는 이른바 풀업(pull-up) 저항으로, 수백 킬로옴(㏀) 이상의 저항값을 가지며, 퓨징 저항(RF)의 트리밍 전에, 인버터(820) 출력 전압을 "HIGH"로 유지하는데 사용된다. Here, Rpu is a resistance value of the second load 820. The second load 810 is a so-called pull-up resistor, has a resistance value of several hundred kiloohms or more, and maintains the inverter 820 output voltage at "HIGH" before trimming the fusing resistor (RF). It is used to
도 8에 도시된 트리밍 장치(800)의 동작의 시퀀스는 다음과 같다. The sequence of operations of the trimming device 800 shown in FIG. 8 is as follows.
트리밍 패드(420)에 충분히 높은 전압 및 전류를 인가하게 되면 다이오드(410)는 턴 온 되어 퓨징 패드(420)에 인가된 전압 또는 전류에 의하여 퓨징 저항(RF)이 단선되어, 인버터(820) 입력전압(Va) 전압은 로직 "HIGH"가 된다. When a sufficiently high voltage and current are applied to the trimming pad 420, the diode 410 is turned on and the fusing resistor RF is disconnected by the voltage or current applied to the fusing pad 420, thereby inputting the inverter 820. The voltage Va becomes the logic "HIGH".
따라서, 인버터(820)의 최종 출력 전압은 로직 "LOW"가 된다. 이후 퓨징 패드(420)를 플로팅하면, 제 1 부하(710)에 의해 다이오드(410)는 턴 오프 되어 인버터(820)의 최종 출력 전압은 로직 "LOW"를 유지한다.Thus, the final output voltage of the inverter 820 is logic "LOW". When the fusing pad 420 is then floated, the diode 410 is turned off by the first load 710 so that the final output voltage of the inverter 820 remains logic "LOW".
도 9는 본 발명에 따른 트리밍 장치를 적용한 웨이퍼의 레이아웃을 나타낸다. 도 9를 참조하면, 복수의 트리밍 패드(420)는 칩(Chip) 외부의 스크라이브 레인에 위치하고, 메탈 라인에 의해 각각의 칩(Chip) 내부와 연결된다. 본 발명에 따른 트리밍 장치의 기술적 사상은 웨이퍼의 레이아웃에도 확대 적용할 수 있다. 9 shows a layout of a wafer to which a trimming device according to the present invention is applied. Referring to FIG. 9, the trimming pads 420 are located in a scribe lane outside the chip, and are connected to the inside of each chip by metal lines. The technical idea of the trimming apparatus according to the present invention can be extended to the layout of the wafer.
일반적으로 웨이퍼에는 스크라이브 레인으로 분리된 복수의 칩이 형성되어 있으며, 복수의 칩 각각에는 적어도 하나의 내부회로 및 내부회로에 대응하는 인터페이스 회로가 형성되어 있다. Generally, a plurality of chips separated by a scribe lane are formed on a wafer, and at least one internal circuit and an interface circuit corresponding to the internal circuit are formed on each of the plurality of chips.
본 발명에서는 스크라이브 레인에 각 인터페이스 회로에 대응하는 복수의 패드가 형성되어 있다. 여기서 복수의 패드는, 내부회로 테스트를 위한 테스트 패드 또는 트리밍을 위한 트리밍 패드이다. 만약, 트리밍을 위한 트리밍 패드(420)라면, 도 4에서 설명한 바와 같이 인터페이스 회로에는 퓨징 저항(RF)이 구비된다. 또한, 도 4에서 설명한 바와 같이 인터페이스 회로에는 다이오드(410)가 더 구비될 수 있다. In the present invention, a plurality of pads corresponding to each interface circuit are formed in the scribe lane. Here, the plurality of pads are test pads for internal circuit testing or trimming pads for trimming. If the trimming pad 420 is used for trimming, as illustrated in FIG. 4, the interface circuit includes a fusing resistor RF. In addition, as described with reference to FIG. 4, the interface circuit may further include a diode 410.
또한, 도 7과 도8에서 설명한 일 단자가 트리밍 패드(420)와 다이오드(410)의 공통단자에 연결되고, 다른 일 단자가 접지전압에 연결되는 제1부하(710), 일 단자가 다이오드(410)와 퓨징 저항(RF)의 공통단자에 연결되고, 다른 일 단자가 전원전압(VDD)에 연결되는 제2부하(810) 및 제2부하(810)와 퓨징 저항(RF)의 공통단자로부터 출력되는 전압(Va)를 반전시키는 인버터(820)를 더 구비될 수 있다.In addition, the first load 710, one terminal is connected to the common terminal of the trimming pad 420 and the diode 410, one terminal described in Figures 7 and 8, the other terminal is connected to the ground voltage 410 and the common terminal of the second load 810 and the second load 810 and the fusing resistor RF, which are connected to the common terminal of the fusing resistor RF and the other terminal of which is connected to the power supply voltage VDD. An inverter 820 may be further provided to invert the output voltage Va.
도 10은 도 9에 도시된 웨이퍼에 소우잉(sawing)이 완료된 후의 레이아웃을 나타낸다. 웨이퍼의 소우잉(sawing)은 다이아몬드 칼 등으로 칩 외부에 형성된 스크라이브 레인을 따라서 절단하는 것으로 이루어진다. 트리밍 패드가 스크라이브 레인에 위치하게 되면, 소우잉(sawing)시 패드의 일부가 절단된다. FIG. 10 shows a layout after sawing is completed on the wafer shown in FIG. 9. Sawing of the wafer consists of cutting along a scribe lane formed outside the chip with a diamond knife or the like. When the trimming pad is placed in the scribe lane, a portion of the pad is cut during sawing.
절단된 패드의 일부가 웨이퍼의 기판에 단락되면 최종출력이 원치 않는 상태로 될 수 있지만, 본 발명에서는, 도 8에 도시된 트리밍 장치(800)의 예를 들면, 웨이퍼를 절단한 후에 절단된 트리밍 패드(420)의 일부가 웨이퍼의 칩과 단락되더라도, 다이오드(420)의 애노드가 다이오드가 턴 온 될 수 있을 정도의 충분한 전압 및 전류가 인가되지 않는 한 제1부하(710)에 의해 접지전압으로 연결되어 턴 오프가 되어있으므로, 인버터(820)의 최종 출력 전압은 트리밍을 실시한 상태를 유지한다. If a part of the cut pad is shorted to the substrate of the wafer, the final output may be in an undesired state. However, in the present invention, for example, the trimming apparatus 800 shown in FIG. 8 is cut after cutting the wafer. Even if a portion of the pad 420 is shorted to the chip of the wafer, the anode of the diode 420 is brought to ground voltage by the first load 710 unless a sufficient voltage and current are applied to turn the diode on. Since it is connected and turned off, the final output voltage of the inverter 820 remains trimmed.
특히 다이오드(420) 스스로 애노드에 인가되는 전압에 따라 턴 온, 톤 오프가 되기 때문에 종래 기술의 트리밍 장치(300)와 달리 별도의 트리밍 모드 패드(320)가 필요 없는 장점이 있다. In particular, since the diode 420 is turned on and off depending on the voltage applied to the anode, there is an advantage that a separate trimming mode pad 320 is not required, unlike the trimming apparatus 300 of the prior art.
물론 다이오드(420)가 턴 온 될 수 있을 정도의 전압을 갖고 있는 칩 내부 또는 외부의 특정 노드와 단락이 되는 경우 최종출력이 원치 않는 상태가 될 수 있으나, (종래 기술의 트리밍 장치(300)는 이 경우에도 최종 출력을 트리밍을 실시한 상태를 유지한다.) 통상적인 웨이퍼 기판은 접지전압(GND)과 단락이 되어 있기 때문에 절단된 트리밍 패드(410)의 일부가 웨이퍼 기판과 단락이 된다 하더라도 다이오드(420)는 턴 온 될 수 없다.Of course, if the diode 420 has a short circuit with a specific node inside or outside the chip that has a voltage enough to turn on, the final output may be an undesired state, but the conventional trimming device 300 Even in this case, the final output is trimmed.) Since a conventional wafer substrate is short-circuited with the ground voltage GND, even if a part of the trimming pad 410 is short-circuited with the wafer substrate, the diode ( 420 cannot be turned on.
이제까지 본 발명에 대하여 그 바람직한 실시예들을 중심으로 살펴보았다. 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 본 발명이 본 발명의 본질적인 특성에서 벗어나지 않는 범위에서 변형된 형태로 구현될 수 있음을 이해할 수 있을 것이다. 그러므로 개시된 실시예들은 한정적인 관점이 아니라 설명적인 관점에서 고려되어야 한다. 본 발명의 범위는 전술한 설명이 아니라 특허청구범위에 나타나 있으며, 그와 동등한 범위 내에 있는 모든 차이점은 본 발명에 포함된 것으로 해석되어야 할 것이다.So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

Claims (6)

  1. 퓨징 저항;Fusing resistance;
    칩 외부의 스크라이브 레인(scribe lane)에 위치하고, 상기 퓨징 저항을 트리밍하기 위한 전압 또는 전류를 인가하는 트리밍 패드; 및A trimming pad located in a scribe lane outside the chip and applying a voltage or current to trim the fusing resistor; And
    상기 트리밍 패드로부터 일정 레벨 이상의 순방향 전류 또는 전압이 인가되면, 상기 순방향 전류 또는 전압을 상기 퓨징 저항으로 인가하는 다이오드를 포함하는 것을 특징으로 하는 트리밍 장치.And a diode for applying the forward current or voltage to the fusing resistor when a predetermined level or more forward current or voltage is applied from the trimming pad.
  2. 제 1 항에 있어서, The method of claim 1,
    일 단자가 상기 트리밍 패드와 상기 다이오드의 공통단자에 연결되고, 다른 일 단자가 접지 전압에 연결되는 제 1 부하를 더 포함하는 것을 특징으로 하는 트리밍 장치.And a first load connected at one terminal to a common terminal of the trimming pad and the diode and at the other terminal to a ground voltage.
  3. 제 1 항에 있어서,The method of claim 1,
    일 단자가 전원 전압과 연결되고, 다른 일 단자가 상기 다이오드와 상기 퓨징 저항의 공통단자에 연결되는 제 2 부하; 및A second load having one terminal connected to a power supply voltage and the other terminal connected to a common terminal of the diode and the fusing resistor; And
    상기 다이오드, 상기 제 2 부하 및 상기 퓨징 저항의 공통 단자로부터 출력되는 전압을 반전시켜 출력하는 인버터를 더 포함하는 것을 특징으로 하는 트리밍 장치.And an inverter for inverting and outputting a voltage output from the common terminal of the diode, the second load, and the fusing resistor.
  4. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3,
    상기 다이오드는 게이트 및 드레인이 상기 트리밍 패드에 연결되고, 소스가 상기 퓨징 저항에 연결된 NMOS 트랜지스터로 구현된 것을 특징으로 하는 트리밍 장치.And wherein the diode is implemented with an NMOS transistor having a gate and a drain connected to the trimming pad and a source connected to the fusing resistor.
  5. 제 1 항 내지 제 3 항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3,
    상기 다이오드는 게이트 및 드레인이 상기 퓨징 저항에 연결되고, 소스가 상기 트리밍 패드에 연결된 PMOS 트랜지스터로 구현된 것을 특징으로 하는 트리밍 장치.And wherein the diode is a PMOS transistor having a gate and a drain connected to the fusing resistor and a source connected to the trimming pad.
  6. 제 1 항 내지 제 3 항 중 어느 한 항의 트리밍 장치가 형성된 웨이퍼.A wafer on which the trimming device of any one of claims 1 to 3 is formed.
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CN112630628B (en) * 2021-03-08 2021-05-18 上海伟测半导体科技股份有限公司 Fuse device and method for polysilicon process fuse

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JP2000235908A (en) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd Resistance trimming circuit
KR100847011B1 (en) * 2006-11-08 2008-07-17 주식회사 에이디텍 Trimming unit and Wafer having pads out of a chip

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JP2000235908A (en) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd Resistance trimming circuit
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112889151A (en) * 2019-05-23 2021-06-01 富士电机株式会社 Trimming circuit and trimming method

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