WO2010082781A3 - Trimming device and a wafer on which the trimming device is formed - Google Patents

Trimming device and a wafer on which the trimming device is formed Download PDF

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Publication number
WO2010082781A3
WO2010082781A3 PCT/KR2010/000259 KR2010000259W WO2010082781A3 WO 2010082781 A3 WO2010082781 A3 WO 2010082781A3 KR 2010000259 W KR2010000259 W KR 2010000259W WO 2010082781 A3 WO2010082781 A3 WO 2010082781A3
Authority
WO
WIPO (PCT)
Prior art keywords
trimming device
trimming
chip
wafer
advantage
Prior art date
Application number
PCT/KR2010/000259
Other languages
French (fr)
Korean (ko)
Other versions
WO2010082781A2 (en
Inventor
권성준
Original Assignee
(주)싸이닉솔루션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)싸이닉솔루션 filed Critical (주)싸이닉솔루션
Publication of WO2010082781A2 publication Critical patent/WO2010082781A2/en
Publication of WO2010082781A3 publication Critical patent/WO2010082781A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

Abstract

Disclosed are a trimming device and a wafer on which the trimming device is formed. The trimming device of the present invention presents the advantage of reducing the surface area of a chip by forming a trimming pad, which used to be inside the chip, in the space of a scribe lane between one chip and another chip. Further, the present invention presents the advantage that there is no effect on the internal circuit even if part of the pad is severed on the substrate of the wafer after sawing, since the internal circuit is separated from the outside by means of a diode. Further, because a diode is used instead of the MOS switch found in trimming devices of the prior art, the present invention presents the advantage that circuit design and layout are simplified since, unlike the prior art, there is no need for an additional trimming mode pad for switch adjustment.
PCT/KR2010/000259 2009-01-19 2010-01-15 Trimming device and a wafer on which the trimming device is formed WO2010082781A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2009-0004012 2009-01-19
KR1020090004012A KR20100084726A (en) 2009-01-19 2009-01-19 Trimming device and the wafer in which trimming device is formed

Publications (2)

Publication Number Publication Date
WO2010082781A2 WO2010082781A2 (en) 2010-07-22
WO2010082781A3 true WO2010082781A3 (en) 2010-10-14

Family

ID=42340215

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/000259 WO2010082781A2 (en) 2009-01-19 2010-01-15 Trimming device and a wafer on which the trimming device is formed

Country Status (2)

Country Link
KR (1) KR20100084726A (en)
WO (1) WO2010082781A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7147970B2 (en) * 2019-05-23 2022-10-05 富士電機株式会社 Trimming circuit and trimming method
CN112630628B (en) * 2021-03-08 2021-05-18 上海伟测半导体科技股份有限公司 Fuse device and method for polysilicon process fuse

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235908A (en) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd Resistance trimming circuit
KR100847011B1 (en) * 2006-11-08 2008-07-17 주식회사 에이디텍 Trimming unit and Wafer having pads out of a chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235908A (en) * 1999-02-17 2000-08-29 New Japan Radio Co Ltd Resistance trimming circuit
KR100847011B1 (en) * 2006-11-08 2008-07-17 주식회사 에이디텍 Trimming unit and Wafer having pads out of a chip

Also Published As

Publication number Publication date
WO2010082781A2 (en) 2010-07-22
KR20100084726A (en) 2010-07-28

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