WO2010059359A1 - Systèmes et procédés utilisant des cellules de désactivation du signal d'horloge améliorées - Google Patents

Systèmes et procédés utilisant des cellules de désactivation du signal d'horloge améliorées Download PDF

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Publication number
WO2010059359A1
WO2010059359A1 PCT/US2009/062489 US2009062489W WO2010059359A1 WO 2010059359 A1 WO2010059359 A1 WO 2010059359A1 US 2009062489 W US2009062489 W US 2009062489W WO 2010059359 A1 WO2010059359 A1 WO 2010059359A1
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WO
WIPO (PCT)
Prior art keywords
circuit
clock
gating cell
clock gating
input
Prior art date
Application number
PCT/US2009/062489
Other languages
English (en)
Inventor
Animesh Datta
Martin Saint-Laurent
Varun Verma
Prayag B. Patel
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to EP09748912A priority Critical patent/EP2342822A1/fr
Priority to JP2011534739A priority patent/JP5175399B2/ja
Priority to KR1020117012355A priority patent/KR101255585B1/ko
Priority to CN200980143452.2A priority patent/CN102204096B/zh
Publication of WO2010059359A1 publication Critical patent/WO2010059359A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes

Definitions

  • the present description generally relates to clock gating cells and, more specifically, to clock gating cells with improved ability to handle slow-rising or slow- falling clock edges.
  • FIGURE 1 is an illustration of a conventional clock gating cell
  • CGC CGC 100.
  • CGCs are used in many applications to stop the propagation of a clock signal to an unused circuit to reduce the dynamic power by halting computation in the circuit.
  • a handheld device that includes MP3 functionality and phone functionality
  • one or more CGCs can be used to prevent the clock from propagating to parts of the processor (as well as to other chips) that are not used when the phone functionality is idle. Parts that do not receive the clock use much less power, so that battery life is extended.
  • the un-gated clock signal itself has a high activity factor, making it a major source of dynamic power usage.
  • the CGC 100 has a clock input and enable inputs.
  • the global clock source is the clock input, and it is labeled CIkJn.
  • a CGC such as CGC 100, can include any number of enable inputs, examples of which can include a clock enable (Clk_en), and a scan enable (test_en) that activates the clock during scan testing of the circuit.
  • FIGURE 1 shows the generic block diagram of a typical CGC standard cell circuit that includes an active low latch 101, a two-input AND gate 102, and enable logic 103.
  • the output of the CGC 100 is CIk, which is the gated clock pulse.
  • FIGURE 2 is an illustration of a more detailed view of a CGC 150 configured according to design of the CGC 100
  • FIGURE 3 illustrates a timing diagram of key nodes of the CGC 150 during some operations.
  • the active low latch 101 includes, among other things, an inverter chain ⁇ i.e., the inverters 107 and 108) and a pull-down stack (i.e., the NMOS transistors 104 and 106).
  • the pnl node When the active low latch 101 is enabled (either from test_en or CIk _en signal) initially the pnl node is set to logic 1 during the transparent phase of the latch 101. Under this condition the CGC 150 passes the input CIk Jn signal to the output CIk. Initially the CIk Jn is at logic 0, so the pn2 node is at logic 1. For a slow rising input CIk Jn signal, the voltage at the internally buffered Clkjiet node can rise quickly, even before CIk Jn rises halfway to Vdd/2 (where Vdd is system power), thereby turning on the pull-down NFET 104 (FIGURE 2) of the pnl node. This is undesirable.
  • the pnl node voltage can drop momentarily before being restored to logic 1. The drop in voltage at the pnl node leads to functional failures at low voltage operation of the chip.
  • CGCs are not limited to using active low latches. For instance,
  • FIGURE 4 is an illustration of a conventional CGC 400 which employs an active high latch and an OR gate at the output.
  • CGC 400 is, essentially, a dual of CGC 100. Potential functional failures can occur during slower CIk Jn transitions in the active high-latch based CGC 200 of FIGURE 400 when premature charging of the pnl node occurs (as opposed to the premature discharging issue of CGC 100 of FIGURE 1).
  • Prior art solutions to guard against the functional failure described above include over-designing the clock tree to maintain a good edge rate during low voltage operations or slower lots of the manufactured parts. However, over- designing the clock tree comes at a cost of burning more dynamic power and shorter battery life.
  • Another solution is to upsize a CGCs output logic to quickly propagate the input clock signal to the output node. This approach is conventionally followed in the industry for general purpose clock gating, but it comes at a cost of increasing the area needed for the output logic, burning more dynamic power resulting from the increased area.
  • upsizing of the output logic also increases setup time of enable logic, which is typically an important constraint for any high performance system, e.g., processors and DSP cores.
  • Various embodiments of the invention add safeguarding circuitry to the conventional CGC architecture that prevents the input node (e.g., pnl of FIGURES 1 and 2) of the output logic gate from discharging prematurely.
  • an additional transistor is placed between the input node of the output logic gate and ground.
  • An inverter which is in communication with enable circuitry, is placed at the gate of the additional transistor.
  • the feedback loop of the conventional CGC architecture is modified so that it does not include the output of the NAND gate, but rather includes an inverted signal taken from the input node of the NAND gate.
  • An additional transistor is added to the feedback loop as well.
  • the new feedback arrangement keeps the input node of the NAND gate from discharging during a slow rising edge.
  • embodiments add safeguarding circuitry to CGCs based on active high latches as well to prevent premature charging of the input node (e.g., pnl of FIGURE 4.
  • Various embodiments reduce or eliminate the scope of functional failure, even at lower voltage operations. Some embodiments also suppress large amounts of noise in the internal nodes, which might otherwise induce failures in other neighboring circuits. Other benefits of some embodiments include substantial power savings as well as improved timing. Consequently, some embodiments can operate at a higher global frequency and/or allow a given CGC to drive a larger load.
  • FIGURE 1 is an illustration of a conventional clock gating cell.
  • FIGURE 2 is an illustration of a more detailed view of the CGC of FIGURE 1.
  • FIGURE 3 illustrates a simulated timing diagram of key nodes of the CGC of FIGURE 1 during a particular mode of operation.
  • FIGURE 4 is an illustration of a conventional CGC which employs an active high latch and an OR gate at the output.
  • FIGURE 5 is a block diagram showing an exemplary wireless communication system in which an embodiment of the invention may be advantageously employed.
  • FIGURE 6 is an illustration of an exemplary CGC, adapted according to one embodiment of the invention.
  • FIGURE 7 is a simulated timing diagram for the CGC of
  • FIGURE 6 shows voltages of the key nodes therein.
  • FIGURE 8 is an illustration of an exemplary CGC, adapted according to one embodiment of the invention.
  • FIGURE 9 illustrates a simulated timing diagram of key nodes of the CGC of FIGURE 1 during some operations.
  • FIGURE 10 is an illustration of an exemplary CGC, adapted according to one embodiment of the invention.
  • FIGURE 11 is an illustration of an exemplary CGC, adapted according to one embodiment of the invention.
  • FIGURE 12 is an illustration of an exemplary process, adapted according to one embodiment of the invention.
  • FIGURE 5 shows an exemplary wireless communication system
  • FIGURE 5 shows three remote units 520, 530, and 540 and two base stations 550, 560. It will be recognized that conventional wireless communication systems may have many more remote units and base stations.
  • the remote units 520, 530, and 540 can include any of a variety of clock gating cells.
  • the remote units 520, 530, and 540 can also include any of a variety of other components, such as Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), processors, delta sigma data converters, and the like.
  • ADCs Analog to Digital Converters
  • DACs Digital to Analog Converters
  • Embodiments of the invention can find use in various components, and especially in synchronized circuits, such as processors, DACs, ADCs, and the like.
  • FIGURE 5 shows forward link signals 580 from the base stations 550, 560 to the remote units 520, 530, and 540 and reverse link signals 590 from the remote units 520, 530, and 540 to
  • remote units may include cell phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, fixed location data units such as meter reading equipment, and/or the like.
  • the remote unit 520 is shown as a mobile telephone
  • the remote unit 530 is shown as a portable computer
  • the remote unit 540 is shown as a fixed location remote unit in a wireless local loop system.
  • the base stations 550, 560 can be any of a variety of wireless base stations, including, e.g., cellular telephone base stations, wireless network access points (e.g., IEEE 802.11 compliant access points), and the like.
  • FIGURE 5 illustrates remote units according to the teachings of the invention, the invention is not limited to these exemplary illustrated units.
  • FIGURE 6 is an illustration of an exemplary CGC 600, adapted according to one embodiment of the invention.
  • the CGC 600 has an architecture similar to that of the CGC 100, but the CGC 600 adds circuitry 601 that prevents the pnl node from discharging during a slow rising clock edge.
  • the additional circuitry 601 includes a minimum sized inverter 602 driving an NFET 603 in the pull-down stack of the pnl node.
  • minimum sized refers to an inverter having a width of about 120 nm; however the scope of embodiments is not so limited, as a given application can employ any suitably sized inverter.
  • FIGURE 7 is a simulated timing diagram for the CGC 600 (of
  • FIGURE 6 shows voltages of the key nodes therein.
  • the pnl node is set to logic 1 during the transparent phase of the latch.
  • the CGC 600 simply passes the input CIk Jn signal to the output CIk.
  • the CIk Jn signal is at logic 0, so the pn2 node is at logic 1.
  • Clkjiet node goes high quickly, before CIk Jn rises halfway to Vdd/2, and turns on the pull-down NFET 604 of the pnl node.
  • the inverter 602 and the feedback NFET 603 stop the discharging of the pnl node when the pnl node is at logic 1.
  • circuitry 601 keeps node pnl from being discharged. Therefore, the pnl node does not exhibit premature voltage drop.
  • One advantage of the embodiment of FIGURE 6 is that it allows some downsizing of the output logic gate 607, which reduces the capacitive loading of the CIkJn, thereby reducing the dynamic switching power of the CGC 600 as a whole.
  • the output logic gate 607 can be downsized by up to forty percent.
  • the design of the CGC 600 helps to reduce functional reliability concerns for low voltage operation, thereby making low voltage operation possible. With low voltage operation available, the power consumption and battery life of a given chip can be effectively enhanced.
  • various embodiments allow the use of larger fan-out loading, thereby reducing the total number of CGCs in a large system, saving substantial area and power dissipation.
  • FIGURE 8 is an illustration of an exemplary CGC 800, adapted according to one embodiment of the invention.
  • the CGC 800 includes an additional PMOS transistor 802 and an inverter 801.
  • the architecture of the CGC 800 also has a feedback loop that includes, among other things, the output from the inverter 801 (in this case, node pnl) and the additional PMOS transistor 802.
  • CIk Jn is at logic 0 and the pnl node is driven by "en " logic through the transmission gate 804.
  • the transmission gate 804 When CIk Jn is at logic 1, the transmission gate 804 is off, and the pnl node is either driven by the pull-up circuit (which includes devices 802 and 805) or the pull-down circuit (which includes devices 806 and 807).
  • the pull-up circuit which includes devices 802 and 805)
  • the pull-down circuit which includes devices 806 and 807).
  • feedback devices 802 and 807 are each driven by an inverter output rather than by the output of NAND 803.
  • CGC 800 when CIk Jn transitions from logic 0 to logic 1, node pn2 does not change its state as long as the state of node pnl is maintained.
  • inverter 801 and the inverter formed by devices 802 and 805- 807 act as a cross-coupled inverter circuit, where one inverter has node pnl as an input &nd pn2 as an output, and the other inverter has node pn2 as an input and node pnl as an output.
  • the cross- coupled inverters act to preserve the states of nodes pnl and pn2 preventing premature charge or discharge of node pnl during the CIk Jn transition.
  • the feedback loop is turned off to allow the data to propagate through the latch, and the states of pnl and pn2 are not preserved.
  • the CGC 800 allows for use of a downsized output logic gate 803.
  • FIGURE 9 is a simulated timing diagram showing the failure mode that can occur in conventional CGCs, such as that shown in FIGURES 1 and 2.
  • FIGURE 9 shows that when CIk Jn falls with a slow transition rate, Clkjiet follows CIk after a short time, and node pn2 changes slowly from logic 0 to logic 1. During the transition, there is a timing window when both the transistors 104 and 106 (FIGURE 2) in the pull-down stack are turned on, thereby discharging node pnl.
  • the CGC 600 (of FIGURE 6) prevents the discharging of node pnl by cutting off the discharge path with the additional transistor 603, which remains off during the operation.
  • the CGC 800 (of FIGURE 8) prevents the discharging of node pnl in a similar way by cutting off the discharge path with the inverter 801 driving pull-down device 807 to an off state.
  • FIGURE 10 is an illustration of exemplary CGC 1000 adapted according to one embodiment of the invention.
  • System 1000 is an active high latch-based equivalent of the embodiment of FIGURE 6.
  • CGC 1000 prevents transistors 1003 and 1005 from charging node pnl prematurely.
  • nodes pnl and pn2 both start at logic 0.
  • transistor 1003 is on.
  • CIk Jn begins falling, the internally buffered signal at the input to transistor 1005 goes to logic 0 much faster than either node pnl or pn2, thereby turning on transistor 1005 before nodes pnl and pn2 change.
  • Safeguarding circuitry 1001 includes inverter 1002 and transistor
  • CGC 1000 its enable logic is typically also a dual of that of a CGC based on an active low latch.
  • one type of enable logic that can be used in the embodiments shown in FIGURES 10 and 11 includes a NOR gate.
  • FIGURE 11 is an illustration of exemplary CGC 1100 adapted according to one embodiment of the invention.
  • System 1100 is an active high latch- based equivalent of the embodiment of FIGURE 8.
  • System 1100 uses a cross-coupled inverter structure to preserve the states of nodes pnl &n ⁇ pn2 when the CIk Jn falls from one to zero. When CIk Jn transitions from logic 1 to logic 0, node pn2 does not change its state as long as the state of no ⁇ pnl is maintained.
  • inverter 1101 and the inverter formed by devices 1102 and 1105-1107 act as a cross-coupled inverter circuit.
  • the cross coupled inverters act to preserve the states of nodes pnl and pn2.
  • the state of node pnl is preserved by preventing premature charge or discharge during the CIk in transition.
  • the feedback loop is turned off because devices 1102 and 1106 are turned off to allow the data to propagate through the latch.
  • FIGURES 6, 8, 10, and 11 provide advantages over the prior art. For example, significant power savings can be achieved using the systems of FIGURES 6, 8, 10, and 11 versus the prior art system of FIGURES 1 and 2.
  • the proposed additional circuitry can, in some embodiments, increase the extent of downsizing that can be achieved in the output logic to reduce the capacitive loading of the CIk path.
  • the reduced capacitive loading on the input circuit also can improve the setup time of the enable logic. As setup times decrease, an engineer's options are increased, since higher frequency clocks can be chosen for use in the system.
  • Some embodiments of the invention include methods for use of improved CGCs.
  • a method is performed by a chip that includes one or more CGCs, such as the CGC 600 (of FIGURE 6) or the CGC 800 (of FIGURE 8).
  • FIGURE 12 is an illustration of an exemplary process 1200, adapted according to one embodiment of the invention.
  • the clock gating cell is enabled by asserting the enable logic.
  • there are two or more enable inputs such as a clock enable and a test enable.
  • the scope of embodiments is not limited by the number of enable inputs.
  • a clock signal with an edge is applied at the clock input. The edge can be a falling edge or a rising edge, and the clock signal will usually include an alternating pattern of rising and falling edges. Since the CGC is enabled, the input clock signal should be propagated through the CGC and into other circuitry.
  • safeguarding circuitry prevents the premature discharging or charging of the input node of the output logic circuit during the clock edge.
  • CGCs of FIGURES 6 and 8 prevent pull-down transistors from prematurely discharging the node pnl, which is one input node of the output NAND gate.
  • the CGCs of FIGURES 10 and 11 prevent pull-up transistors from prematurely charging the node pnl.
  • process 1200 is shown as a series of discrete steps, the scope of embodiments is not so limited.
  • Various embodiments may add, omit, modify, or rearrange one or more blocks. For instance, some embodiments may repeat the blocks 1202-1203 with each clock cycle, or even with each edge of the clock.
  • some embodiments include propagating the clock signal to various computational circuits, thereby allowing those computational circuits to be in an operational mode.

Abstract

L'invention porte sur une cellule de désactivation de signal d'horloge qui comprend un verrou en communication avec une logique de validation d'entrée et un circuit logique de sortie, le verrou comprenant un circuit d'excursion haute et/ou d'excursion basse au niveau d'un nœud d'entrée du circuit logique de sortie et des circuits empêchant une charge ou décharge prématurée du nœud d'entrée du circuit logique de sortie par le circuit d'excursion haute et/ou d'excursion basse lorsque la cellule de désactivation de signal d'horloge est validée.
PCT/US2009/062489 2008-10-30 2009-10-29 Systèmes et procédés utilisant des cellules de désactivation du signal d'horloge améliorées WO2010059359A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP09748912A EP2342822A1 (fr) 2008-10-30 2009-10-29 Systèmes et procédés utilisant des cellules de désactivation du signal d'horloge améliorées
JP2011534739A JP5175399B2 (ja) 2008-10-30 2009-10-29 改良クロック・ゲーティング・セルを用いるシステム、及び方法
KR1020117012355A KR101255585B1 (ko) 2008-10-30 2009-10-29 개선된 클럭 게이팅 셀들을 이용한 시스템들 및 방법들
CN200980143452.2A CN102204096B (zh) 2008-10-30 2009-10-29 使用改进式时钟门控单元的系统及方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/261,428 US8030982B2 (en) 2008-10-30 2008-10-30 Systems and methods using improved clock gating cells
US12/261,428 2008-10-30

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Publication Number Publication Date
WO2010059359A1 true WO2010059359A1 (fr) 2010-05-27

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US (1) US8030982B2 (fr)
EP (1) EP2342822A1 (fr)
JP (1) JP5175399B2 (fr)
KR (1) KR101255585B1 (fr)
CN (1) CN102204096B (fr)
TW (1) TW201032020A (fr)
WO (1) WO2010059359A1 (fr)

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Publication number Priority date Publication date Assignee Title
US9270270B2 (en) 2012-09-19 2016-02-23 Qualcomm Incorporated Clock gating circuit for reducing dynamic power
KR20210093757A (ko) * 2020-01-17 2021-07-28 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 클럭 게이팅 회로 및 그 동작 방법
KR102467280B1 (ko) 2020-01-17 2022-11-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 클럭 게이팅 회로 및 그 동작 방법
US11545965B2 (en) 2020-01-17 2023-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Clock gating circuit and method of operating the same

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JP5175399B2 (ja) 2013-04-03
US8030982B2 (en) 2011-10-04
TW201032020A (en) 2010-09-01
US20100109747A1 (en) 2010-05-06
KR20110089328A (ko) 2011-08-05
JP2012507953A (ja) 2012-03-29
EP2342822A1 (fr) 2011-07-13
CN102204096B (zh) 2014-11-05
KR101255585B1 (ko) 2013-04-16
CN102204096A (zh) 2011-09-28

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