Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/0203—Particular design considerations for integrated circuits
  • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
  • H01L23/5223—Capacitor integral with wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
  • H01L23/5225—Shielding layers formed together with wiring layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L27/0805—Capacitors only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
  • H01L28/40—Capacitors
  • H01L28/60—Electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Definitions

• the present invention relates to capacitors formed in integrated circuits ("ICs") commonly referred to as integrated capacitors.
• ICs integrated circuits
• Methods of fabricating ICs typically include a front-end sequence of processing, in which various electrical devices such as transistors are formed in a semiconductor substrate, and a back-end sequence of processing, generally including forming alternating layers of dielectric material and patterned conductive material (typically metal) with conductive vias or other techniques being used to interconnect the metal layers to form a three-dimensional wiring structure that connects electrical devices to other electrical devices and to terminals of the IC.
• a front-end sequence of processing in which various electrical devices such as transistors are formed in a semiconductor substrate
• a back-end sequence of processing generally including forming alternating layers of dielectric material and patterned conductive material (typically metal) with conductive vias or other techniques being used to interconnect the metal layers to form a three-dimensional wiring structure that connects electrical devices to other electrical devices and to terminals of the IC.
• Capacitors are used in IC systems for a variety of purposes. In many instances, it is desirable to incorporate (integrate) a capacitor in the IC chip. A simple approach is to form two conductive plates with an intervening dielectric; however, this consumes a relatively large area for the capacitance obtained.
• One technique for increasing the capacitance of a given area is to use multiple conductive plates, each conductive plate separated from the proximate plate(s) by dielectric. Further techniques use conducting strips, also called conductive lines, conductive fingers, or conductive traces, that are alternately connected to the first and second capacitor terminals (nodes). Sidewall coupling between the conductive strips provides capacitance. Layers of conducting strips, either offset or arranged in vertical congruency, can be added to further increase the capacitance of an integrated capacitor structure.
• One capacitor has a number of conductive strips in successive layers connected to the first node alternating with an equal number of conductive strips connected to the second node of the integrated capacitor.
• the conductive strips are offset a half cell on successive layers, so that a conductive strip connected to the first node has conductive strips connected to the second node above and on both sides of it.
• Providing an equal number of conductive strips in a layer for each node balances the coupling of each node to the substrate, which is desirable in some applications, but undesirable in others, such as switching applications where it is desirable to have less coupling at one node.
• a thick layer of silicon dioxide is used between the substrate and the first layer of conductive strips. This may be difficult to integrate in a standard CMOS fabrication sequence and might require additional steps to be added to the standard process flow.
• the overlapping parallel conductive strips are connected at their ends using buss strips that consume additional surface area.
• Another approach to providing an integrated capacitor is to have conductive strips in a layer connected to alternate nodes of the capacitor with overlapping conductive strips connected to the same node. This forms essentially a curtain of conductive strips and interconnecting vias connected to the first node of the capacitor with adjacent curtains of conductive strips and interconnecting vias connected to the second node. Overlapping conductive strips connected to the same node avoids the lost surface area associated with buss strips; however, inter-layer capacitance is reduced because the upper strip is connected to the same node as the lower strip. This effect is somewhat obviated because, as critical dimensions shrink, inter-strip capacitance becomes more dominant than inter-layer capacitance. In other words, the dielectric layer separation between successive metal layers becomes increasingly greater than the dielectric separation between conductive strips with decreasing critical dimension.
• a capacitor in an integrated circuit includes a core capacitor portion having a first plurality of conductive elements electrically connected to and forming part of a first node of the capacitor formed in a first conductive layer of the IC and a second plurality of conductive elements electrically connected to and forming part of a second node of the capacitor formed in the first conductive layer.
• the first plurality of conductive elements alternates with the second plurality of conductive elements in the first conductive layer.
• a third plurality of conductive elements electrically connected to and forming part of the first node is formed in a second conductive layer adjacent to the first conductive layer, at least portions of some of the second plurality of conductive elements overlying and vertically coupling to at least portions of some of the third plurality of conductive elements.
• the capacitor also includes a shield capacitor portion having a fourth plurality of conductive elements formed in at least the first conductive layer of the IC, the second conductive layer of the IC, a third conductive layer of the IC, and a fourth conductive layer.
• the first and second conductive layers are between the third and fourth conductive layers.
• the shield capacitor portion is electrically connected to and forms part of the second node of the capacitor and surrounds the first and third pluralities of conductive elements.
• FIG. 1 is a circuit diagram of a circuit using capacitors according to embodiments of the invention.
• FIG. 2A is an isometric view of a portion of a shielded integrated capacitor suitable for use in embodiments of the present invention.
• FIG. 2B is a side view of a integrated capacitor 220 in accordance with FIG. 2A.
• FIG. 2C is a side view of the integrated capacitor according to FIG. 2A with a ground shield according to an embodiment.
• FIG. 2D is a side view of the integrated capacitor according to FIG. 2A with an alternative ground shield according to another embodiment.
• FIG. 3A is a side view of an integrated capacitor with a bottom node shield according to an alternative embodiment.
• FIG. 3B is a partial cutaway plan view of the M5 and M4 layers showing a portion of the ground plate and underlying bottom node shield plate of FIG. 3A.
• FIG. 4A is side view of an integrated capacitor with a bottom node shield according to yet another alternative embodiment.
• FIG. 4B is a cross section of a shielded integrated thin-dielectric capacitor in an IC according to another embodiment,
• FIG. 5 is a plan view of an FPGA incorporating an integrated capacitor according to an embodiment.
• FIG. 1 is a circuit diagram of a circuit 100 using capacitors 102, 104 according to embodiments of the invention.
• the top node 108 of capacitor 104 is switchable to be connected to or disconnected from a high-impedance input 114 of amplifier 116.
• the top node 106 of the feedback capacitor 102 is also connected to the high-impedance input 114 of the amplifier 116 while the bottom node 110 is connected to output 118 of the amplifier 116.
• the feedback capacitor 102 is switchably shorted by closing switch 119.
• the coupling capacitor 104 has a top node 108 shielded by a bottom node shield 120 that essentially surrounds the top node 108 with conductive structures electrically connected to the bottom node and reduces parasitic capacitive coupling of the top node 108 to other nodes of the circuit 100. Connection to the top node 108 is made through a gap in the bottom node shield 120.
• the bottom node shield is shown as being contiguous, in some embodiments the bottom node shield is made up of several conductive elements, such as metal filaments, metal vias, and polysilicon or suicide plates or strips, to form a conductive cage around the top node, shielding the top node from electronic noise and from coupling to other nodes of the IC.
• the bottom node shield contributes to the overall capacitance of the integrated capacitor by coupling to the top node.
• a capacitor is generally thought of as a two terminal device, and the "top” and “bottom” nodes as described herein generally correspond to these two terminals of the capacitor.
• the structures described below may be thought of as connecting (e.g., electrically) to one or the other node, or forming portions or parts of a node.
• a node is not separate from the capacitive structures connected to it, but those structures may form portions of a node.
• the feedback capacitor 102 has a top node 110 shielded by a bottom node shield 122, and by an optional reference shield 124.
• the reference shield 124 is connected to a relatively stable reference voltage present in the IC, such as analog ground, digital ground, or V DD -
• the reference shield 124 essentially surrounds the bottom node shield 120 and shields the bottom node from substantially coupling to more than one voltage reference (e.g., the bottom node couples to V DD or ground, but not both).
• a reference shield partially surrounds a bottom node shield.
• the reference shield has a gap allowing electrical contact to be made to the bottom node, as described above.
• top node and bottom node do not necessarily relate to the physical orientation of the nodes relative to the IC or other structure, but are used as terms of convenience.
• the top node of a capacitor indicates the node that is connected to a high-impedance or high-gain port of an amplifier or other device.
• SoC system-on-chip
• ADC analog-to-digital converter
• top plate It is desirable to shield the top plate from ground currents or voltage supply fluctuations so that C tO p remains low.
• Using the bottom node to essentially surround the top node isolates the top node from coupling with other nodes in the circuit by essentially forming a portion of Faraday shell around the top node, and in some embodiments, distancing the top node from other conductive elements in the IC. It is understood by those of skill in the art that electrical connection to the top node is made through the bottom node shield, and therefore the bottom node shield does not completely surround the top node.
• some sides of the top node are left unshielded.
• an end of the top node that is physically distant from other nodes might be left unshielded.
• integrated capacitors are used as design cells, and adjacent integrated capacitors are connected in parallel to obtain a higher total capacitance.
• the portions of the bottom node shield of adjacent commonly-connected integrated capacitors are omitted, allowing higher packing density.
• CMOS complementary metal-oxide-semiconductor
• IMD inter-metal dielectric
• ILD inter-layer dielectric
• the vias are formed using any of several known techniques, such as contact plug, damascene, or dual damascene techniques.
• the conductive strips are formed using any of several known techniques, such as thin-film metal etch, thin-film metal lift-off, damascene, and dual damascene techniques.
• one of the conductive layers is a polysilicon or suicide layer.
• a conductive well in the semiconductor substrate forms a portion of a capacitor plate or a shield.
• FIG. 2A is an isometric view of a portion 200 of an integrated capacitor according to an embodiment of the present invention.
• a bottom plate conductive matrix 202 includes a first bottom plate layer B made up of a first plurality of conductive strips 204, 206 and a second bottom plate layer B' made up of a sheet of polysilicon or suicide, in what is commonly called a "poly" layer, all connected to the bottom node of the integrated capacitor.
• the bottom node in this embodiment is the capacitor node that is less susceptible to electronic noise than the top node when the capacitor is used in a particular circuit application.
• a top plate conductive matrix 212 is covered by the first bottom plate layer B and underlain by the second bottom plate layer B' , which forms a partial Faraday shield around the top node.
• the first bottom plate layer is made up of strips, rather than a continuous sheet, because of design layout rules familiar to those of skill in the art of IC fabrication. Generally, each metal layer has minimum and maximum metal line widths and minimum separations. Polysilicon and suicide layers typically have different design and process rules than patterned metal layers, which allows forming the bottom plate layer as a contiguous sheet of poly when the poly layer is used. Similarly, large conductive areas can be formed in the semiconductor substrate (e.g., an N-well or a P-well) to form a continuous conductive sheet. In an alternative embodiment, the second bottom plate layer is formed in a conductive well of the substrate.
• the conductive well is separated from the poly layer by a relatively thin dielectric layer, providing good electrical performance even though the N-well is generally less conductive than a metal layer or poly layer.
• a conductive well to form part of a shield is further desirable because a moat can be formed around the portion of the substrate in which the N-well or P-well is formed, which further isolates the N- or P-well from stray currents.
• Use of a conductive well in a shield is also desirable because the well is surrounded in a fairly symmetrical fashion by metal, leading to symmetrical current flow through the well portion of the shield.
• the conductive strips 204, 206 in the top plate layer B are electrically connected through vias (not shown, see, e.g., via 214) to transverse (i.e., generally orthogonal) conductive strips (e.g., B4) in the lower layer so that interconnection between conductive strips 204, 206 in the metal layer of the first bottom plate layer B is not necessary.
• conductive cross members cross-connects between strips in the metal layer
• a top plate layer T is made up of a plurality of conductive strips 216, 218 connected to the top node of the integrated capacitor.
• the conductive strips in the top plate layer T are transverse to conductive strips T1 , T2, T3, T4, T5 above the top plate layer T and transverse to conductive strips T6, T7, T8, T9, T10 below the top plate layer, and conductive strips in the top plate layer T are electrically connected to each other through vias and transverse conductive strips above and below the top plate layer T.
• the conductive strips e.g.
• T1 , B1 are made from a minimum-width metal line and are commonly referred to as "conductive filaments” or “metal filaments” and provide high line densities and high lateral capacitance. Lateral capacitance between conductive strips in the plate layers does not contribute to the specific capacitance of the integrated capacitor because the metal strips are connected to the same node, and conductive strips in the plate layers are often wider than minimum metal line width.
• the plate layers B, T, B' do not have alternating conductive strips, but rather all the conductive strips in these layers are connected to either the top node or the bottom node of the integrated capacitor.
• the configuration of a capacitor according to FIG. 2A provides bottom plates B, B' that shield the conductive elements of the top plate because they are embedded between the first and second bottom plate layers in the IC stack.
• Conductive curtains (see, FIG. 2B, ref. nums. 236, 238) on the right and left sides of the top plate conductive matrix are formed of vias and metal layers between the first bottom plate B and the second bottom plate B' and extend along a third direction (e.g., the Z direction as illustrated in FIG.
• FIG. 2B is a side view of a integrated capacitor 220 in accordance with
• FIG. 2A The side view is taken along the direction of the arrow A in FIG. 2A.
• the integrated capacitor has a core capacitor portion 201 and a shield capacitor portion 203.
• the shield capacitor portion 203 is basically a bottom node shield that has a first shield layer B formed in the fifth metal layer M5 of a backend stack 222 of an IC that includes metal layers M1 , M2, M3, M4, M5 and intervening dielectric layers that have vias (e.g., via 226) extending through the dielectric layers to connect metal layers.
• the dielectric layers are not shown with hatching for clarity of illustration, as they are well understood by those of skill in the art of IC processing.
• Integrated capacitors according to alternative embodiments include additional metal layers.
• the integrated capacitor includes an optional reference shield, which in this embodiment is a reference shield connected to V DD -
• the reference shield includes a shield plate 224 made up of a conductive well
• Nwell formed in the semiconductor substrate 226 of the IC, a top shield plate 225 formed in the M5 metal layer, and conductive curtains 240, 242.
• the shield capacitor portion 203 forms a conductive sheath around the core capacitor portion 201 , which has interleaved top and bottom node conductive filaments that provide high specific lateral capacitance in the M1 and M3 metal layers, and vertical capacitance between the bottom node elements in M1 and M3 and the top node elements in M2, which is adjacent to both M1 and M3.
• the shield capacitor portion adds additional capacitance by coupling to the top node conductive elements in M1 , M2, and M3.
• each layer of interleaved filaments will have hundreds of filaments and the lateral coupling between the filaments is a significant portion of the total capacitance of the integrated capacitor.
• the second bottom plate layer B' is formed in the poly layer of the IC.
• the second bottom plate layer is formed as strips in a metal layer, such as M1 or M2, in a backend stack that has additional metal layers. Utilizing the poly layer for the second bottom plate layer allows a shielded integrated capacitor (without the optional V DD shield) to be formed in a four-metal-layer IC.
• a conductive well formed in the semiconductor substrate is used as the second bottom plate layer, allowing an embodiment to be fabricated in three metal layers of an IC, or allowing additional metal layers for increasing the specific capacitance of a capacitor of a given area.
• the dielectric layer above the substrate and poly layer is commonly called an inter-layer dielectric ("ILD"), and the conductive element 228 connecting the poly layer to the N+ conductive area 230 of the substrate is commonly called a contact, as opposed to a via.
• ILD inter-layer dielectric
• a gate dielectric layer (not separately shown) between the poly and the N-well is typically much thinner than the ILD layer.
• FIG. 2B is not drawn to scale.
• the thicknesses of the IMD and ILD layers are greater than the spacing between the interleaved conductive strips (e.g., T1 and B1 ) in the interleaved layers M3 and M1.
• the ILD layer is about 300 nm thick silicon oxide, while the dielectric layer between the poly layer and M1 layer is about 100 nm thick and the higher layers are about 250 nm.
• the minimum separation between metal traces in a layer is typically much smaller, thus the sidewall capacitance between T1 and B1 , for example, is greater than the vertical capacitance between T1 and B.
• the sidewall capacitance between the ends of the top plate conductive matrix (e.g., T1 , T4, T5, T8, and both ends of T) and the conductive curtains 236, 238; and the end vias 250, 252 and curtain vias 254, 256 (and corresponding vias on other sides) provide additional capacitance that compensates for the lack of interleaving in the M4, M2 and poly layers.
• the relative contribution of sidewall capacitance between interleaved metal strips and vias to the overall capacitance increases.
• the optional reference shield includes a first shield layer 225 and the shield plate 224 formed in the N-well that are connected through a series of vias, metal, poly, and contacts.
• the vias, metal, poly, and contacts form a first shield curtain and a second shield curtain that are basically the right and left vertical portions of the reference shield.
• third and fourth conductive curtains of the bottom plate conductive matrix enclose the as-viewed front and back planes of the bottom node shield and core capacitor.
• the reference shield is connected to a stable voltage reference, such as V DD or ground, to reduce coupling of the bottom node to more than one voltage node.
• V DD stable voltage reference
• the bottom node matrix couples essentially only to the top node and to V DD - Negligible coupling of the other nodes of the IC to the bottom node occurs.
• the shield were connected to ground instead of V DD , the bottom node would only couple to the top node and ground. It is generally undesirable for the bottom node to couple to V DD and ground simultaneously because the bottom node would then act as a bridge between ground and V DD , and could couple undesirable switching currents between the two nodes, for example.
• limited coupling to both V DD and ground is acceptable, particularly if coupling of the bottom node shield to a reference shield is limited to conductive elements connected to an isolated portion of the substrate, or if the ground node is an analog ground node that is reasonably well isolated from a digital ground node.
• a gap or similar feature (not shown, see FIG. 1 ) is provided in the shield to allow circuit connection to the bottom node conductive matrix, and a second gap or similar feature is provided in the shield, and a third gap or similar feature is provided in the bottom plate conductive matrix to allow connection to the top node conductive matrix.
• electrical connections to the conductive matrices can be brought out in the directions orthogonal to the plane of the illustration sheet, for example.
• Bottom node shielding can also be brought out along the top node connection to a switch, for example, to further shield the top node.
• FIG. 2C is a side view of the integrated capacitor 250 with a ground shield 256 (represented as a dashed line) according to an embodiment.
• the integrated capacitor 250 includes a core capacitor portion 252 that includes conductive elements (e.g., filaments) within a metal layer (e.g., M1 , M3) alternatively connected to opposite nodes of the capacitor and a shield capacitor portion (bottom node shield) 254.
• conductive elements e.g., filaments
• M1 , M3 metal layer
• shield capacitor portion bottom node shield
• T1 , 12, T3, and T4 alternate with B1 , B2, and B3 in M3 and T5, T6, T7, and T8 alternate with B5, B6, and B7 in M1.
• Alternating conductive elements in the core capacitor portion 252 provides significant lateral capacitance, which improves as fabrication dimensions are reduced and the conductive elements become closer together.
• the shield capacitor portion 254 surrounds the core capacitor 252 to form a conductive cage that reduces coupling of the top node to other nodes of the IC.
• the integrated capacitor 250 produces good specific capacitance, which is essentially C SIG per unit area of silicon, from both the core capacitor portion 252 and also from coupling between top node elements in the core capacitor portion 252 and the shield capacitor portion 254.
• the integrated capacitor includes an optional ground shield 256 that partially surrounds the bottom node shield 254, basically forming a Faraday cup.
• the ground shield reduces electronic noise generated in the IC that might otherwise couple to the bottom node or top node of the integrated capacitor 250.
• a reference shield plate 257 is formed in the M5 layer, providing a low-resistance ground path for connecting the ground shield 256 to one or more ground terminals of the IC.
• the ground shield 256 is connected to the analog ground of the IC, rather than the digital ground to avoid high switching currents and electrical noise that can be present on the digital ground.
• a V DD shield cup 258 (represented as a dashed line) includes a shield plate 260 formed in an N-well in the semiconductor substrate 226.
• V DD bias is brought to the N-well V DD shield through conductive curtains 262, 264 or alternatively through conductive pillars.
• Providing the V DD shield cup 258 further shields the top node and the bottom node of the integrated capacitor from electrical noise.
• the M5 layer might only be a ground shield with no V DD interconnect allowed at M5.
• FIG. 2D is a view of an integrated capacitor 270 with a ground shield according to another embodiment.
• the capacitor 270 includes a core capacitor portion 252 and a bottom node shield forming a shield capacitor portion 254 as described above in reference to FIGs. 2A-2C.
• the shield capacitor portion 254 surrounds the core capacitor portion 252 and isolates the core capacitor portion from electronic noise similarly to how an outer conductive sheath of a cable isolates the inner wires from electronic noise.
• the bottom node shield extends over the ends of the capacitor core not shown in this view (i.e., the ends that are in the plane of the view).
• the ground shield is connected to analog ground, rather than to digital ground.
• FIG. 3A is a side view of an integrated capacitor 300 according to an alternative embodiment.
• a core capacitor portion 304 includes conductive elements (e.g., filaments) within a metal layer (e.g., M1 , M2, M3) alternatively connected opposite nodes of the capacitor.
• conductive elements e.g., filaments
• M1 , M2, M3 e.g., M1 , M2, M3
• T1 , T2, T3, and T4 alternate with B1 , B2, and B3 in M3, T5, T6, and T7 alternate with B4, B5, B6, and B7 in M2, and T8, T9, T10, T11 alternate with B8, B9, and B10 in M1.
• Top node elements T1 , T4, T8, and T11 also laterally couple with bottom node shield elements.
• B4 vertically couples with T1 and T8, providing vertical capacitance that increases the specific capacitance.
• Alternating conductive elements in the core capacitor portion 304 provides lateral capacitance, which improves as fabrication dimensions are reduced and the conductive elements become closer together. While it would be generally desirable that each end element in a metal layer laterally couple with a conductive filament electrically connected to the opposite node of the integrated capacitor, in an actual device there may be hundreds of parallel conductive filaments in each metal layer, and the few row ends that are not opposite polarity may have relatively little detrimental effect.
• a ground shield 306 includes ground shield conductive curtains 308, 310, that essentially surround the core capacitor portion 304 and shield capacitor portion 302 of the integrated capacitor.
• the ground shield conductive curtains 308, 310 include poly elements 312, 314 and contacts 316, 318 to P+ regions 320, 322 in the substrate 226.
• the ground plate 256 in the M5 layer is connected to an analog ground terminal of the IC.
• the substrate is relatively high resistance; however, the bottom node plate B' is still well-shielded from coupling to other nodes because the silicon below B' is relatively electrically quiet, particularly if that portion of the substrate is formed in a moat and the ground shield typically makes contact with the substrate around the perimeter of the ground shield.
• the ground node plate 256 has relatively low resistance to ground because it is a metal layer.
• the M5 layer is used as a ground shielding layer for an analog portion of the IC, and is composed of wide ground strips (see Fig. 3B) with many ground connection points, rather than occasional thin traces, as in other metal layers. It is particularly desirable in some IC applications to maintain the integrity of the analog ground shield layer; however, embodiments that include a V DD shield plate in the analog ground shield layer are useful in many ICs because the V DD shield is connected to a clean (i.e., relatively electrically quiet) supply, which blocks electrical noise from the analog circuitry below from affecting the remainder of the IC, similar to the effect of the ground plane. The small margin between a V DD shield plate and the ground plane in such embodiments provides relatively little area for unwanted electrical noise emissions to occur.
• FIG. 3B is a partial cutaway plan view of the M5 and M4 layers showing a portion of the ground plate 256 and underlying bottom node shield plate B of FIG. 3A.
• the ground plate 256 is made up of wide strips 350, 352, 354 that overlie conductive filaments 356, 358, 360, 366 of the upper bottom node shield plate B.
• the gaps 362, 364 between the ground plate strips 350, 352, 354 are defined over conductive filaments 360, 366 so that a conductor underlies the gap, which improves shielding of the top node of the integrated capacitor; however, this detail is not essential in all embodiments.
• FIG. 4A is side view of an integrated capacitor 400 with a bottom node shield capacitor portion 402 according to yet another alternative embodiment.
• the bottom node shield capacitor portion 402 sheathes a core capacitor portion 404 having a series of conductive curtains TC1 , TC2, TC3, TC4 electrically connected to the top node of the integrated capacitor 400, interleaved with a series of conductive curtains BC1 , BC2, BC3, BC4, BC5 electrically connected to the bottom node of the integrated capacitor.
• the conductive curtains are basically conductive filaments formed in successive metal layers connected with conductive vias to form essentially a conductive sheet extending perpendicular to and from the plane of illustration.
• top node conductive matrix is made through a gap in the bottom node shield, or by bringing a tap (conductive trace) out the end of one of the metal layers.
• the bottom node conductive curtains BC1 , BC2, BC3, BC4, BC5 are electrically connected through the upper bottom node plate B and lower bottom node plate B' , but alternatively could be connected through one or the other.
• the conductive curtains BC1 and BC5 connect the upper bottom node plate B with the lower bottom node plate B' , which is formed in the poly layer of the IC, and form part of the shield capacitor portion 404 of the integrated capacitor, as well as providing lateral capacitance to the adjacent top node conductive curtains TC1 , TC4 in the core capacitor portion 402.
• a ground shield cup 406 is formed from a ground shield plate 256 formed in the M5 layer and has conductive curtains Gi, Q 2 extending from the ground shield plate 256 toward the substrate 226.
• the conductive curtains extend through the poly layer to the substrate 406 (see, e.g., FIG. 3A).
• FIG. 4B is a cross section of a shielded integrated thin-dielectric capacitor 420 in an IC according to another embodiment.
• the thin-dielectric capacitor uses a conductive well 422 in the substrate 424 as a first plate 425 of the capacitor ("substrate plate").
• a second plate (“gate layer plate”) 426 of the thin- dielectric capacitor is formed in a polysilicon, suicide, or metal layer that is commonly the gate layer of the IC.
• the gate layer plate 426 is separated from the substrate plate 425 by a thin dielectric layer 428 that commonly forms a gate oxide layer or gate dielectric layer of the IC.
• Some ICs, such as particular FPGAs, have more than one allowable gate dielectric layer thickness, commonly referred to as thin-oxide, mid-oxide, or thick-oxide. While the thinnest gate dielectric layer would provide the highest specific capacitance, thicker gate dielectric, such as mid-oxide or thick oxide, provides superior reliability and yield at a given operating voltage.
• the maximum operating voltage for a thin- dielectric capacitor is typically less than the maximum gate voltage for an FET having the same dielectric gate layer.
• the gate dielectric material preferably has a relatively high dielectric constant to provide good coupling between the gate and channel of MOSFETs in the IC, which enhances the specific capacitance of the thin-dielectric capacitor 420.
• a capacitor shield portion is formed around the gate layer plate 426, which in a particular application is the top node of the integrated capacitor 420.
• the shield is a bottom node shield capacitor portion.
• the shield includes the substrate plate 425, contacts 432, 434, and upper bottom node shield plate 436 formed in a metal layer or a second poly layer of the IC.
• the contacts are generally spaced around the perimeter of the upper plate 436 to form essentially a Faraday cage around the gate layer plate 426.
• the upper plate is formed in a second poly layer that is overlain onto the substrate directly, without the use of contacts.
• the substrate plate 425 is an element of both the core capacitor portion
• the substrate plate is alternatively formed in a P-well or in the native substrate without a well.
• the upper bottom node shield plate 436 includes a gap 438 through which electrical contact to the top node (gate layer plate 426) is made, while electrical contact to the substrate can be made through the upper bottom node shield plate 436 and contacts 432, 434.
• the top node of the integrated capacitor 420 is shielded from electrical noise. Since the gate layer plate is formed in the poly layer, it can be a contiguous sheet of conductor and does not have to be formed of stripes or filaments, as in superior metal layers. Similarly, the substrate plate can be a contiguous sheet.
• the upper bottom node shield plate is typically formed from a series of maximum-width metal lines that are interconnected within the layer to approximate a contiguous sheet.
• the upper bottom node shield plate contributes substantially to the specific capacitance of the integrated capacitor while also shielding the top node from electrical noise.
• An estimated specific capacitance for a thin-dielectric capacitor according to an embodiment fabricated in an IC using a thick-oxide of about 250 nm thickness is about 7 fF/ ⁇ m 2 . Note that the types of and number of layers described are merely examples, and in some embodiments other suitable layers may be used, and any number of layers may be used.
• the layers used may depend on the types and numbers of layers that are available in the manufacturing process, and other arrangements will be apparent to those of skill in the art. In general, any suitable layer, and an arbitrary number of layers may be used in accordance with embodiments of the present invention.
• FIG. 5 is a plan view of an FPGA 500 semiconductor device incorporating an integrated capacitor according to an embodiment.
• the FPGA 500 includes CMOS portions in several of the functional blocks, such as in RAM and logic, and is fabricated using a CMOS fabrication process.
• One or more integrated capacitors 555 according to one or more embodiments of the invention are incorporated in any of several functional blocks of the FPGA, such as a clock circuit 505, a multi-gigabit transceivers 501 , or other functional block; within many functional blocks; or within a physical section or segment of the FPGA 500.
• Integrated capacitors 555 are particularly desirable in applications where one or both terminals of the capacitor are switched, and embodiments including top plate shielding are further desirable in applications wherein the top plate is connected to or switched to a high-impedance or high-gain node of a circuit in the FPGA 500.
• Capacitors are generally useful in a wide variety of integrated circuits and in a wide variety of applications. For instance, one or more capacitors may be useful for a switched capacitor network, such as in an analog- to-digital converter, or as a decoupling or filtering capacitor for AC signaling (e.g., in an MGT). In general, the capacitor structure described herein may be useful in any application requiring capacitance.
• the FPGA architecture includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs 501 ), configurable logic blocks (CLBs 502), random access memory blocks (BRAMs 503), input/output blocks (lOBs 504), configuration and clocking logic (CONFIG/CLOCKS 505), digital signal processing blocks (DSPs 506), specialized input/output blocks (I/O 507) (e.g., configuration ports and clock ports), and other programmable logic 508 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth.
• Some FPGAs also include dedicated processor blocks (PROC 510).
• each programmable tile includes a programmable interconnect element (INT 511 ) having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA.
• the programmable interconnect element (INT 511 ) also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of FIG. 5.
• a CLB 502 can include a configurable logic element (CLE 512) that can be programmed to implement user logic plus a single programmable interconnect element (INT 511 ).
• a BRAM 503 can include a BRAM logic element (BRL 513) in addition to one or more programmable interconnect elements.
• BRAM logic element BRAM logic element
• the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used.
• a DSP tile 506 can include a DSP logic element (DSPL 514) in addition to an appropriate number of programmable interconnect elements.
• An IOB 504 can include, for example, two instances of an input/output logic element (IOL 515) in addition to one instance of the programmable interconnect element (INT
• the actual I/O pads connected, for example, to the I/O logic element 515 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element 515.
• a columnar area near the center of the die is used for configuration, clock, and other control logic.
• Some FPGAs utilizing the architecture illustrated in FIG. 5 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA.
• the additional logic blocks can be programmable blocks and/or dedicated logic.
• the processor block PROC 510 shown in FIG. 5 spans several columns of CLBs and BRAMs.
• FIG. 5 is intended to illustrate only an exemplary FPGA architecture.
• the numbers of logic blocks in a column, the relative widths of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of FIG. 5 are purely exemplary.
• more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic.

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