Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/302—Contactless testing
  • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences

Definitions

• the present invention relates to detection of defects during the manufacture of flat panel displays, and more particularly during the array fabrication step of liquid crystal display panels.
• LCD flat panel liquid crystal displays
• TFT thin film transistor
• AMLCD active matrix LCD
• Flat panel displays may also be fabricated using OLED technologies and, though typically fabricated on glass may also be fabricated on plastic or other substrate plates.
• TFT pattern deposition is performed in a multitude of stages where in each stage, a particular material (such as a metal, indium tin oxide (ITO), crystalline silicon, amorphous silicon, etc.) is deposited on top of a previous layer (or glass) in conformity with a predetermined pattern.
• a particular material such as a metal, indium tin oxide (ITO), crystalline silicon, amorphous silicon, etc.
• ITO indium tin oxide
• crystalline silicon silicon
• amorphous silicon etc.
• Each stage typically includes a number of steps such as deposition, masking, etching, stripping, etc.
• defects include but are not limited to metal protrusions 110 into ITO 112, ITO protrusions 114 into metal 116, so-called mouse bites 118, open circuits 120, shorts 122 in transistors 124, foreign particles 126, and residue under pixel 128.
• Amorphous silicon (a-Si) residue under a pixel 128 may result from under-etchmg or lithography issues
• Other defects include mask problems, over etching, and the like.
• LC liquid crystal
• One sheet of glass contains the patterned two-dimensional TFT array of electrodes.
• Each electrode may be on the order of 100 micions in size and can have a unique voltage applied to it via driving circuits positioned along the edge of the panel
• the elect ⁇ c field created by each individual electrode couples into the LC material and modulates the amount of transmitted light in that pixelated region. This effect when taken in aggregate across the entire two-dimensional array results in a visible image on the finished flat-panel
• Photon Dynamics, Inc has developed an electro-optical inspection and test system, which is also referred to as an array tester or array checker (AC)
• the array tester may identify defects m LC displays through use of a voltage imaging sensor (VIOS) as desc ⁇ bed, for example, in US Patents 4,983,911, 5,097,201, and 5,124,635.
• VOS voltage imaging sensor
• the pixel electrodes within the panel to be tested are electrically d ⁇ ven using specific patterns, as desc ⁇ bed, for example, in US Patents 5,235,272 and 5,459, 410.
• Figures 2 and 3 A are perspective and front views of a camera 35 and modulator 15 moving over a glass plate 10 to detect the defects thereon.
• Figure 3B is a front view of camera 35 and modulator 15 positioned into place to sense the electric fields from the pixel electrodes on the panel.
• the imaging sensor head (developed by Photon Dynamics), which includes a modulator 15, is physically moved over a region of the panel under test (PUT) 20 to be inspected and then lowered to within a few microns of the panel's surface.
• the pixel electrodes array on the panel is electrically driven using specific drive patterns.
• the small air gap 25 between the panel pixel electrodes 30 and the modulator 15 allows the electric field from each driven pixel electrode 30 on the patterned glass plate 10 to couple to modulator 15 to create a temporary visible display (or voltage image) of the panel. This visible display is subsequently captured by the imaging sensor head's camera 35 for identification of defects.
• LC modulator 15 is moved to another region on the panel and the process is repeated. Through this step-and-repeat process, the entire PUT can be inspected and tested for defects.
• LC modulator 15 is shown as including an LC material 45 and a flat glass 50.
• a glass plate may be quite large (for example, generation 7 sized plates are nearly two meters on each side), and is often divided into a number of panels.
• glass plate 10 of Figure 2 is shown as including six panels 18.
• each panel contains thin film transistor (TFT) array circuitry that is required for driving liquid crystal displays. Testing of the panel is typically accomplished by observing the response of the TFT circuitry to the application of drive voltages, in particular patterns and sequences.
• the TFT responses are observed and recorded using an imaging sensor head such as Photon Dynamics' VIOS-which detects the TFT responses, or more specifically the electric fields on the pixel electrode, using an electro-optical modulator -or AKT' s sensor head which detects the TFT responses using an electron beam.
• FIG. 1 An imaging device such as a CCD camera (when using VIOS) or a detector (when using e-beam) is used to record the observed responses.
• an imaging sensor head is typically smaller than a panel under test (PUT). To test all the panels on the glass plate, the imaging sensor head must move with respect to the panel, taking images at each position, as described above.
• Photon Dynamic's VIOS system generates a voltage map (VM) image of the defects of the panel. The voltage map identifies the coordinates of each detected defect in the panel coordinate space so that they can be readily located again by other systems, such as repair and review systems.
• Figure 4 is a top schematic view of imaging sensor 35 positioned above an LCD panel 18.
• LCD panel 18 is shown as being positioned along the plane defined by X pan ei-Ypanei coordinate axes.
• Imaging sensor 35 is shown as being positioned along the plane defined by X senso rY se n s or coordinate axes.
• three degrees of freedom such as (i) the X and Y offsets between a known LCD pixel (such as pixel 70) and a known imaging sensor pixel (such as pixel 60), and (ii) the rotational angle a between the X-Y axes of the imaging sensor and the LCD panel are needed.
• FIG. 5 shows the flow of control and data between various components of a system for generating a voltage map, as known in the prior art.
• a pattern generator 100 provides a drive pattern to the PUT.
• a VIOS 102 generates a voltage image of the PUT using its CCD camera.
• the generated voltage image includes a measure image and a calibration image.
• a mechanical pixel map (MPM) is supplied to a computer which in response generates a dynamic pixel map 106.
• the MPM is derived from the alignment marks and geometric information of the panel and the plate.
• the dynamic pixel map (DPM) together with the measure image and the calibration image are subsequently used by an image processing computer 104 to generate the voltage map.
• DPM dynamic pixel map
• Figure 6 A is a top schematic view of a panel 150, as known in the prior art, that includes panel alignment marks 152 and 162 positioned in two diagonally opposed corners of the panel.
• the pixels in the active display area 160 are activated using the signals lines coupled to pads 200, 202, 204 and 206. Also shown in Figure 6 are panel scribe lines 156.
• the geometric information for the LCD pixel electrodes includes the pixel size and the pitch of the pixel array in both X and Y, and their positional relationship to the alignment marks.
• Figure 6B is an enlarged view of region 170 of active display area 160 shown as including eight pixels positioned at intersections of rows 172, 174 and columns 182, 184, 186, 188.
• Optical correction data are accumulated during the installation of the system. Such optical correction data includes, for example, (i) the imaging camera's rotation and position relative to the overall imaging sensor head, (ii) the home position and rotation of the imaging sensor head relative to its travel in the X- Y directions withm the test system, (in) other optics information such as distortion, and (iv) stage error A DPM is generated using this information
• the DPM provides a virtual coordinate system that guides the AC in finding the center location of each LCD pixel electrode thus enabling the VM image to represent the true voltage information
• the VM image may undergo additional image processing so as to determine the exact nature of the defects
• the accuracy of the DPM influences the voltage values, and therefore also the defect detection performance.
• a DPM must be accurate to withm the dimensions of an LCD pixel electrode, e g , within 100 micrometers to 10 micrometers.
• Conventional DPM processing sequences such as that shown in Figure 5, do not allow for automatic incorporation of position data extracted from measurements or images of the LCD pixel array itself
• the user manually adjusts an ideal DPM g ⁇ d to match a voltage image of the LCD pixel electrode array This method is tedious and time-consummg as it is repeated for every plate that is tested Often, due to time constraints, this method is performed once and the resulting map is re-used for subsequent plates, even though the p ⁇ or results may not apply Accuracy is also dependent on the user's consistency and judgment
• FIG. 6A is a top schematic view of a 1-gate-l-data (IGlD) panel 180 that includes a single shortmg bar for driving gate line 208 and a single shortmg bar for d ⁇ ving data input line 210.
• Other patterns, such as 1G2D are also possible.
• Figure 8A shows the voltage signals applied to a 2G2D panel, such as panel 150 shown m Figure 6A, to generate a checkerboard pattern.
• Figure 8B shows the contrast between neighbo ⁇ ng pixels in response to the checkerboard d ⁇ ving signals of Figure 8A Since in a 2G2D panel there are two independent data d ⁇ ve signals and two independent gate d ⁇ ve signals dnving alternating rows and columns of the array, one data/gate pair (for example, GO 202 and DO 204) may be driven in a different pattern and sequence than the second data/gate pair (GE 200 and DE 206). More specifically, odd rows and columns may be driven high while all the even rows and columns are driven low.
• GE 200 and DE 206 the second data/gate pair
• one LCD pixel electrode may be charged positively while its neighbors in the X and Y directions are charged negatively; each of the negatively charged pixels is likewise surrounded in X and Y by pixels that are charged positively. Accordingly, a peak average voltage for each imaging sensor site may be computed from the CCD voltage image thereby to provide results used to adjust the DPM. Consequently, in a checkerboard pattern, neighboring LCD pixel electrodes in both the X and Y directions may be distinguished from one another.
• One disadvantage of this approach is that (i) it is limited to certain types of LCD panels, and (ii) to achieve the desired accuracy, a large number of data samples and/or additional signal-to-noise filtering algorithms are required— both of which require more time.
• Figure 8C shows the voltages received by the pixels of Figure 8B along either the XX or YY directions.
• Figure 8D shows the associated camera pixels recording the responses of the panel pixels of Figure 8C.
• Figure 8E shows the output signals of the camera pixels of Figure 8D. With the various factors contributing to the degradation of signals, the net signal may be less distinct than shown in Figures 8B-8E, but still readable.
• an LCD pixel electrodes have relatively sharp physical boundaries, the support circuitry surrounding the pixels is quite narrow (e.g., approximately ten to twenty micrometer wide lines with approximately the same or less spacing). The distances between pixels is also short, i.e. a few tens of micrometer. Such short distances may cause the electrical charges in one pixel to bleed to the neighboring support circuitry.
• the LCD pixel electrode charges also give rise to local electric field effects at the edges of the electrode, which can distort the distribution of charges within the neighboring electrodes, thus resulting in non-uniform distribution of overall signal as may be viewed by the imaging camera.
• FIG. 9A shows the gate and data voltage signals applied to a IGlD panel.
• Figure 9B shows the contrast between the pixels in response to the driving signals of Figure 9A. As is seen from Figure 9B, the pixels cannot easily be distinguished from one another.
• Figure 9C shows the voltages received by the pixels of Figure 9B along either the XX or YY directions.
• Figure 9D shows the associated camera pixels recording the responses of the panel pixels of Figure 9C.
• Figure 9E shows the output signals of the camera pixels of Figure 9D.
• the accuracy of the information from the LCD pixel array is influenced by whether or not the resolution of the image or measurement allows for distinguishing the LCD pixel electrodes from each other.
• the resolution of the image or measurement further depends on several influencing factors.
• First is the optics of an aligned system.
• Second is the signal contrast between neighboring LCD pixel electrodes.
• Third is the distortion of the signal across a given pixel electrode and between pixel electrodes due to imperfect material and/or electrical effects.
• Fourth is the degradation of signal across a given pixel electrode and between pixel electrodes due to an imperfectly aligned system.
• a CCD pixel is typically approximately 10 to 15 micrometers in size, while its projected image is approximately 30 to 40 micrometers in size.
• An LCD pixel electrode is typically about 121 micrometers by about 363 micrometers in size. Thus, if the optics were aligned well, an LCD pixel electrode would be easily distinguishable from one another by the camera and its optics.
• both the LCD and camera pixel electrodes are regular arrays and because the two arrays have different pitches or periodicities, a moire, or interference, pattern may result, particularly if the pitches of the respective arrays are not integral with respect to each other. Furthermore, a slight rotation of one array relative to the other gives rise to an interference pattern. This result in non-uniform signal strengths from the LCD pixel electrodes within the array.
• One challenge in inspection and testing is determining the locations of the LCD pixel electrodes relative to the sensor's digital camera to enable the captured visible display or voltage image be further processed to extract defect information.
• the mapping information between the LCD pixel electrodes and the defects may be used to identify the positions of the defects for further use in other systems, such as review or repair systems. Extraction of detailed defect information from the voltage images requires accurate knowledge of the LCD pixel electrode positions.
• determining the locations of LCD pixel electrodes requires physical correlation or mapping of the imaging sensor head's camera array to a reference position on the imaging sensor head and subsequently correlating or mapping the position of the sensor head to a position on the panel.
• mapping of the system's imaging camera to the overall sensor head is typically part of the system's calibration procedure that is completed at the initial installation and thereafter occasionally checked, e.g. once every several months.
• determining the location of the sensor head relative to the plate must be completed p ⁇ or to testing of each plate
• a typical TFT pixel electrode is approximately 100 micrometers by 300 micrometers
• the accuracy of the positions of an LCD pixels must be determined to within, e g., 10 to 100 micrometers.
• commercial vendors of flat panel displays increasingly require high throughput or fast TACT time
• the time spent aligning or calibrating a panel should be ideally kept short
• a method of determining the position of a flat panel display relative to the position of a sensing head includes, in part, applying a first signal to a multitude of gate lines coupled to the pixels formed on the panel, capturing the response of the gate lines to the fust signal, applying a second signal to a multitude of date lines coupled to the pixels formed on the panel, captu ⁇ ng the response of the data lines to the second signal, combining the first and second responses to generate a combined response, and determining the intersections of the gate lines and data lines using the combined response The intersections represent the positions of the pixels
• the method further includes using the pixel positions to determine values of offset and rotation of the flat panel display relative the sensing head.
• An apparatus operative to determine pixel position of a flat panel display includes, in part, a signal generator, a sensing head, and a computer system.
• the signal generator is operative to supply signals to a multitude of gate lines and data lines coupled to the pixels formed on the panel, a sensing head operative to capture the response of the gate and data lines to the first signal, and a computer system
• the computer systems has a module that combines the responses of the gate and data lines to generate a combined response, and a module that determines the intersections of the gate lines and data lines using the combined response. The intersections represent the positions of the pixels
• the apparatus further includes a module that determines the values of offset and rotation of the flat panel display relative the sensing head using the pixel positions
• a method of identifying the positions of pixels formed in a multitude of panels of a flat panel display includes, in part, supplying a voltage to one of the panels such that pixels located along at least one of the edges of the panel exhibit an image contrast that is different from the image contrast of a subset of remaining pixels not positioned along that edge of the panel, and using the difference between the image contrasts to identify positions of the pixels of the panel.
• An apparatus operative to identify the positions of pixels formed on one or more panels of a flat panel display includes, in part, a signal generator, a sensing head and a computer system
• the signal generator supplies voltage signals to at least one of the panels
• the a sensing head captures one or more voltage images of the pixels located on the panel
• the captured voltage images exhibit a first contrast associated with pixels located along at least one of the edges of the panel.
• the captured voltage images exhibiting a second contrast associated with the remaining pixels of the panel
• the computer system uses the difference between the first and second contrasts to identify positions of the pixels of the panel
• Figure 1 shows a number of exemplary defects on a flat panel, as known in the p ⁇ or art
• Figure 2 shows an exemplary camera and an exemplary modulator moving ovei a patterned glass plate to detect defects, as known in the p ⁇ or art
• Figure 3A is a front view of the exemplary camera and exemplary modulator of Figure 2 moving over the patterned glass plate.
• Figure 3B shows the exemplary camera and exemplary floating modulator of Figure 2 positioned m proximity of the patterned glass plate to detect defects
• Figure 4 is a top schematic view of an imaging sensor positioned above an LCD panel
• Figure 5 shows flow of control and data between various components of a system for generating a voltage map, as known in the prior art.
• Figure 6A shows an exemplary panel that includes a TFT array, panel reference marks, and a 2G2D shorting bar used to test the array.
• Figure 6B is an enlarged view of a region of the panel of Figure 6A.
• Figure 7 shows an exemplary panel that includes a TFT array, panel reference marks, and a IGlD shorting bar used to test the array.
• Figure 8A shows exemplary voltages applied to the 2G2D panel of Figure 6A to generate a checkerboard pattern, as known in the prior art.
• Figure 8B shows the checkerboard pattern voltage map of the pixel electrodes resulting from the application of exemplary voltages shown m Figure 8A.
• Figure 8C shows the exemplary voltages received by the pixels of Figure 8B along either the XX or YY directions.
• Figure 8D shows the associated camera pixels recording the responses of the panel pixels of Figure 8C.
• Figure 8E shows the output signals of the camera pixels of Figure 8D.
• Figure 9A shows exemplary voltages applied to the IGlD panel shown in Figure 7, as known in the prior art.
• Figure 9B is a spatial voltage map of the pixel electrodes resulting from the application of exemplary voltages shown in Figure 9A.
• Figure 9C shows the voltages received by the pixels of Figure 9B along either the XX or YY directions.
• Figure 9D shows the associated camera pixels recording the responses of the panel pixels of Figure 9C.
• Figure 9E shows exemplary output signals of the camera pixels of Figure 9D.
• Figure 1OA is an exemplary timing diagram of the signals applied to determine the positions of the pixels of a flat panel display, in accordance with one exemplary of the present invention.
• Figure lOB-lOG are exemplary images of the gate lines and data lines that receive the voltages shown in Figure 1OA, in accordance with one embodiment of the present invention.
• Figure 1 IA is a screen shot of a portion of a flat panel having data and gate lines driven using voltage signals in accordance with one exemplary embodiment of the present invention.
• Figures 1 IB and 11C are intensity profiles of the image of Figure 1 IA taken along the X and Y directions.
• Figures 12A-2C show an exemplary process for determining the amount of offset between a flat panel plane and a camera plane, in accordance with one exemplary embodiment of the present invention.
• Figures 13A-13D show an exemplary process for determining the rotation angle between a flat panel plane and a camera plane, in accordance with one exemplary embodiment of the present invention.
• Figure 14 shows flow of control and data between various components of a system for generating a voltage map, in accordance with one exemplary embodiment of the present invention.
• Figure 15 shows an image processing computer 600 used in accordance with one embodiment of the present invention.
• the positions of pixels formed on a flat panel are relatively quickly determined in the coordinate space of a sensing head, such as a camera, being used to detect defects on the flat panel.
• a signal drive pattern designed to provide a sharper, more distinct signal representing the positions of the panel's pixels (or, more specifically, the positions of a characteristic point in the pixel, for instance, its center or a corner), is applied to the panel, notwithstanding the panel type which may be a 2G2D, IGlD, or otherwise.
• positional information about the flat panel pixel electrodes are extracted and evaluated in the coordinate space of the camera's pixels.
• Determination of offset and rotation of the LCD pixels relative to the camera's pixels are automated, thereby to improve TACT time.
• Defect information extracted from the panel using images captured by the sensing head as well as the panel's pixel positions are subsequently ported to other systems, such as review or repair systems.
• panel pixel electrode is used interchangeably with LCD pixel (or LCD pixel electrode) to refer to the TFT electrode circuitry formed on the panel undergoing a test.
• imaging sensor pixel, camera pixel, or CCD pixel are also used interchangeably and refer to a part of the imaging sensor's (also referred to as camera) array that captures images of the panel pixel electrodes.
• an LCD space is defined by the LCD's pixel electrode coordinates
• a CCD space is defined by an associated camera's CCD coordinates. It is further understood that while the following description is provide with reference to a CCD camera or CCD pixels, embodiments of the present invention equally apply to camera sensors that include any other array of sensors, such as CMOS or the like.
• signal drive patterns are applied to the gate lines and the data lines without exciting the pixels.
• the gate lines and data lines have the same periodicity or pitch as the panel pixels but because the gate and data lines have narrower dimensions than the camera pixels, they provide sharper and more distinct signals.
• the intersections of the gate and data lines provide information about the position of the pixels.
• the pixel positions are subsequently used to generate a dynamic pixel map (DPM).
• DPM dynamic pixel map
• Figure 1OA shows a drive pattern applied to gate and data lines of a panel, in accordance with one exemplary embodiment of the present invention.
• the timing of the various drive voltages is associated with the camera's recording of images at a selected frame rate.
• the data lines are driven to a positive voltage during Frame 1 while the gate lines are kept at the ground potential.
• the camera Prior to expiration of Frame 1 period, the camera is triggered and an image is recorded, as shown in Figure 1OB.
• the five dotted lines in Figure 1OE show five exemplary data lines that receive the voltage pattern shown in Figure 1OA.
• the gate and data drive patterns may be repeated several times to gather images similar to those shown in Figures 1OB and 1OC. These results are subsequently combined to form a composite image, as shown in Figure 10D.
• Figure 1OG shows the ten intersections of the data and gate lines of Figures 1OE and 1OF. These ten intersections define the positions of the corners of the LCD pixels (or alternatively they can be used to determine the center of the LCD pixels).
• Other gate/data line drive patterns which may have different sequencing between the drivers of the gate and data lines, different timing between the drivers of the gate and data lines, or different voltages may be used. In other embodiments, the gate and data lines may be driven concurrently so long as the pixels are not charged (excited).
• the composite image shown in Figure 1OD may be generated in a number of different ways. For example, in one embodiment, a multitude of data lines and gate lines are driven independently to enable the capture and processing of their associated images. Thereafter these images are combined to locate their intersections. In another embodiment, an image of the data lines is combined with an image of the gate lines to locate their intersections.
• Figure 1 IA is a screen shot of a portion of a flat panel having data and gate lines driven using voltage signals in accordance with one exemplary embodiment of the present invention.
• Figures 1 IB and 11C are the intensity profiles of the image of Figure 1 IA taken along the X direction (data lines) and Y directions (gate lines).
• the periodic maxima in Figures 1 IB and 11C respectively represent the data lines and gate line positions.
• the location of the intersection of data and gate lines can be identified by the position of the intensity maxima along the lines in a composite digital image since it is the sum of the data signal and the gate signal
• the data and gate line widths are smaller than the camera pixel widths, a significant portion of their signal is distributed within a single camera pixel, and thus any potential shift due to moire effects is relatively easily identified. Furthermore, because the gate and data lines have smaller overall cross sections and are farther apart from each other than the panel pixel electrodes, they have smaller charge density and reduced electric field interference effects. Therefore, fringe field effects that arise due to concentrated charges are significantly attenuated in accordance with embodiments of the present invention.
• enhanced computational techniques allow the determination of the magnification of the imaging sensor head (by comparing the pitch measured by the imaging sensor with the geometrical specifications of the panel) as well as the degree of rotation and offset of the panel pixel plane relative to the camera pixel plane using the panel pixel positions.
• the panel pixel positions determined as described above or using any other technique (e.g., the checkerboard or live driving patterning)may be used to correct for stage errors, errors due to optics, etc. This in turn allows for a relaxation of the stage and optics requirements.
• Figure 12A shows an LCD panel 300 having a multitude of exemplary ChevronTM- shaped pixels 302i, 302 2 , 302 3 whose positions are used to determine the degree of offset and rotation between the XY planes of panel 300 and an imaging camera.
• a template of a repeating feature of the panel, such as its pixels, is extracted from the image of a site.
• a site is understood to refer to a region of the panel whose image may be captured in a single shot by an imaging camera.
• An LCD pixel, such as pixel 302i positioned in, for example, a corner of the panel (e.g., where the imaging camera starts its scan) is selected as a reference pixel.
• the expected position of a corresponding camera pixel 312i is also shown in Figure 12A.
• an image template 350 of the repeating LCD pixel electrode is constructed, as shown in Figure 12B.
• Each square in Figure 12B represents a camera pixel.
• the position of camera pixel 312 2 is shown in Figure 12B using a dotted square.
• template 350 is positioned at its expected location (based on the position of the reference pixel) to compute a difference between the template's actual location and its expected location.
• the template is thereafter shifted in a systematic way until a condition is satisfied. This condition may be satisfied when, for example, the difference between the template's actual location and its expected location correspond to a minimum value defined by a threshold value.
• the template may be shifted in fixed steps in four directions from the starting point, or it may be shifted in increments and directions which are determined using calculations that seek convergence of the difference to a minimum, etc. It is understood that any other pixel shape may be used and any other pixel may be used as the reference pixel electrode.
• the difference between the template's actual location and its expected location (corresponding to the difference between the actual position 312] and expected position 312 2 of camera pixel as shown in Figure 12C) when such a condition is satisfied represents the offset between the LCD and the camera in the X-Y plane.
• the position of the reference LCD pixel electrode is often known within at least half a LCD pixel-size (50 to 100 micrometers typically).
• the XY offset may be determined to within a camera pixel size or smaller when two-dimensional interpolation is used.
• a number of sub-regions e.g. 5, are selected from a site on the panel. The average deviation between the measured positions and the expected positions of the pixels located m the selected regions are thereafter used to determine the offset.
• FIGs 13A-13D schematically show a method for determining the rotation angle between the LCD panel and the camera imaging array, in accordance with another exemplary embodiment of the present invention.
• the method uses the repeating pattern of the LCD pixel array
• an LCD image site 400 is captured, as shown in Figure 13A.
• a site sub-region such as sub-region 402 withm the captured image site
• the sub-region may be located, for example, m one corner of the site image and span an area that is, for example, 100x100 camera pixels by 100 camera pixels wide
• an image 404 of the reference sub-iegion image is placed laterally (e g , along the X axis of the camera) at a position at which image 404 is expected to be repeated.
• Figure 13C also shows the X-Y coordinates of the panel and the CCD camera. Thereafter, a difference between the reference sub-region 402 and the sub- region image 404 at its expected location is computed.
• the reference sub-region is thereafter shifted in a systematic way in a direction 90 degrees relative to the direction of the lateral movement (e g , along the Y axis of the camera) until a condition is satisfied.
• This condition may be satisfied when, for example, this difference corresponds to a minimum value defined by a threshold value
• the rotation angle shown as a m Figure 13D, is defined by the final location of the reference sub-region image 404 yielding a minimum value, the original location of the reference image 402, and the expected location of the reference image 404
• the accuracy of the rotation angle as desc ⁇ bed herein approach is determined, in part, by the distance between the two sub-regions, the size of the sub-region, and the interpolation resolution In one example, an accuracy of about 0.055 arc-mmutes or 2 micrometers is achieved.
• the minimum difference can be found m any of a number of ways
• the reference image may be shifted in fixed steps in, for example, four directions from the starting point, or it may be shifted m increments and direction which are determined using calculations that seek convergence of the difference to a minimum, or the like It is understood that the reference sub-regions may have different sizes and located in different sites.
• Figure 14 shows the flow of control and data between va ⁇ ous components of a system 500 for generating a voltage map, in accordance with one exemplary embodiment of the present invention
• a pattern generator 400 provides a pixel d ⁇ ve pattern and line drive pattern to the panel under test.
• a VIOS using its camera which may be CCD camera or otherwise, generates a voltage image, a calibration image and a measure image of the panel under test.
• An image processing computer 506 uses this data to determine the panel pixel positions, as well as the amount of offset and rotation of the panel relative to the camera's imaging plane in the X-Y plane
• a dynamic pixel map generator 508 receives this formation from image processing computer 506, and m response computes a mechanical pixel map (MPM), optical correction data, and alignment information.
• Image processing computer 506 receives the computed mechanical pixel map (MPM), optical correction data, and alignment information from dynamic pixel map generator 508 to generate a voltage map
• Compa ⁇ son of images for either determmmg offset or rotation may be performed by a cross-correlation algo ⁇ thm, sum of absolute differences algo ⁇ thm, or other similar algo ⁇ thms
• cross-correlation is a measure of simila ⁇ ty of two images I ⁇ (x,y), / 2 (x,y), as defined below
• n is the number of pixels in each image
• ⁇ i, ⁇ 2 , ⁇ i and ⁇ 2 are the means and standaid deviations of the two images
• Parameter r may vary between -1 and 1. If two images are the same, r - ⁇
• the cross-correlation between the two sub-regions is a maximum when there is no rotation. If there is a rotation, the peak cross-correlation will be shifted to a new location for the sub-region image 404. Therefore, the rotation angle may be detected by finding the offset of sub-region image 404. If cross-correlation is used to determine the offset and rotation, instead of finding minimum points maximum points are searched for.
• Performing cross-correlation may be time-consummg
• comparison of images for determining offset or rotation may be achieved using a sum of absolute differences (SAD) defined below:
• rotation errors may be detected by finding the minimal SAD location of sub-region 404. SAD algorithms are faster but less accurate than cross-correlation algorithms.
• FIG 15 shows an image processing computer 600 used in accordance with one embodiment of the present invention.
• Image processing computer 600 is shown as including at least one processor 602, which communicates with a number of pe ⁇ pheral devices via a bus subsystem 604.
• These pe ⁇ pheral devices may include a storage subsystem 606, including, in part, a memory subsystem 608 and a file storage subsystem 610, user interface input devices 612, user interface output devices 614, and a network interface subsystem 616.
• the input and output devices allow user interaction with data processing system 602.
• Network interface subsystem 616 provides an interface to other computer systems, networks, and storage resources 604
• the networks may include the Internet, a local area network (LAN), a wide area network (WAN), a wireless network, an intranet, a p ⁇ vate network, a public network, a switched network, or any other suitable communication network
• Network interface subsystem 616 serves as an interface for receiving data from other sources and for transmitting data to other sources from the computer (data processing device)
• Embodiments of network interface subsystem 616 include an Ethernet card, a modem (telephone, satellite, cable, ISDN, etc.), (asynchronous) digital subsc ⁇ ber line (DSL) units, and the like.
• User interface input devices 612 may include a keyboard, pointing devices such as a mouse, trackball, touchpad, or graphics tablet, a scanner, a barcode scanner, a touchscreen incorporated into the display, audio input devices such as voice recognition systems, microphones, and other types of input devices.
• pointing devices such as a mouse, trackball, touchpad, or graphics tablet
• audio input devices such as voice recognition systems, microphones, and other types of input devices.
• use of the term input device is intended to include all possible types of devices and ways to input information to processing device.
• User interface output devices 614 may include a display subsystem, a printer, a fax machine, or non-visual displays such as audio output devices.
• the display subsystem may be a cathode ray tube (CRT), a flat-panel device such as a liquid crystal display (LCD), or a projection device.
• CTR cathode ray tube
• LCD liquid crystal display
• output device is intended to include all possible types of devices and ways to output information from the processing device.
• Storage subsystem 606 may be configured to store the basic programming and data constructs that provide the functionality in accordance with embodiments of the present invention.
• software modules implementing the functionality of the present invention may be stored in storage subsystem 606. These software modules may be executed by processor(s) 602.
• Storage subsystem 606 may also provide a repository for storing data used in accordance with the present invention.
• Storage subsystem 606 may include, for example, memory subsystem 608 and file/disk storage subsystem 610.
• Memory subsystem 608 may include a number of memories including a main random access memory (RAM) 618 for storage of instructions and data during program execution and a read only memory (ROM) 620 in which fixed instructions are stored.
• File storage subsystem 610 provides persistent (non-volatile) storage for program and data files, and may include a hard disk drive, a floppy disk d ⁇ ve along with associated removable media, a Compact Disk Read Only Memory (CD-ROM) drive, an optical drive, removable media cartridges, and other like storage media.
• CD-ROM Compact Disk Read Only Memory
• Bus subsystem 604 provides a mechanism for enabling the various components and subsystems of the processing device to communicate with each other. Although bus subsystem 604 is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple busses.
• the processing device may be of varying types including a personal computer, a portable computer, a workstation, a network computer, a mainframe, a kiosk, or any other data processing system. It is understood that the description of the computer system 600 is intended only as one example Many other configurations having more or fewer components than the system shown in Figure 15 are possible.
• Embodiments of the present invention provide a number of advantages
• Third, comparison of the pixel pitch, as measured by the imaging sensor head, to the panel's geometric specifications provides a measuie of the imaging sensor head's optical magnification. This, in turn, allows for relaxation of the sensor head optics requirements
• panel edges are detected.
• all the LCD pixels m the panel are charged with a voltage that generates a high contrast between the outermost periphery of the panel and the active aiea (see e.g. Figures 6A, 6B and 7) of the panel itself.
• Driving the panel in such a fashion enables a clear delineation of the edges of the panel (i.e., the borders of the active area)
• image processing algo ⁇ thms and the mechanical pixel map such embodiments may be used to determine the location of pixel centers in cases where a checker board pattern cannot be used (e.g. IGlD panels).
• the contact pads to which the probe frame supplies the d ⁇ ving voltages are positioned close to the active area. If the entire active area is not be viewable on one side of the panel, the remaining edges of the panel may be used to determine the pixel map.
• embodiments of the present invention are equally applicable to testing of TFT arrays using electron beam technology which requires complex and expensive calibration plates.
• embodiments of the present invention may be used for voltage sensitivity calibration in electron beam testers, VIOS testers, and the like.
• the mapping process can be sufficiently fast and may be applied on a per panel basis without significant degradation of the overall TACT time Unlike conventional methods according to which the mapping process is performed at most per plate and usually less often, embodiments of the present invention provide for automatic dynamic adjustments in the mapping In other words, embodiments of the present invention provide for adjustments that happen withm a plate Conventional methods require approximately, e g 4 to 5 seconds to complete calculations of offset and rotation and the final DPM, while embodiments of the present invention can perform more accurate computation m, e g one second oi less

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• 2009
  • 2009-09-24 KR KR1020147020200A patent/KR20140108694A/ko not_active Application Discontinuation
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