WO2010035785A1 - Dispositif afficheur et système de télévision - Google Patents

Dispositif afficheur et système de télévision Download PDF

Info

Publication number
WO2010035785A1
WO2010035785A1 PCT/JP2009/066654 JP2009066654W WO2010035785A1 WO 2010035785 A1 WO2010035785 A1 WO 2010035785A1 JP 2009066654 W JP2009066654 W JP 2009066654W WO 2010035785 A1 WO2010035785 A1 WO 2010035785A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
output
self
signal
display device
Prior art date
Application number
PCT/JP2009/066654
Other languages
English (en)
Japanese (ja)
Inventor
伸介 安西
好博 中谷
宏晃 藤野
裕文 松井
利男 渡部
雅美 森
浩一 細川
昌史 勝谷
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2010035785A1 publication Critical patent/WO2010035785A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to a display device using a drive circuit that performs self-detection and self-repair of a defect in a DA converter output circuit.
  • FIG. 43 is a block diagram showing a configuration of a conventional semiconductor integrated circuit for driving liquid crystal.
  • the liquid crystal driving semiconductor integrated circuit 101 shown in the figure can output m gray scale output voltages from n liquid crystal driving signal output terminals.
  • a liquid crystal driving semiconductor integrated circuit 101 includes an external clock input terminal 102, a gradation data input terminal 103 having a plurality of signal input terminals, a LOAD signal input terminal 104, and V0 terminals 105 and V1 terminals which are reference power supply terminals. 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109.
  • the liquid crystal driving semiconductor integrated circuit 101 includes n liquid crystal driving signal output terminals 111-1 to 111-n (hereinafter, the liquid crystal driving signal output terminals are referred to as signal output terminals. Terminals 111-1 to 111-n are collectively referred to as signal output terminal 111).
  • the liquid crystal driving semiconductor integrated circuit 101 includes a reference power correction circuit 121, a pointer shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 126 and an output buffer 127.
  • the pointer shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n.
  • the latch circuit unit 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n hold circuits 125-1 to 125-n.
  • the DAC circuit 126 is composed of n DAC circuits 126-1 to 126-n.
  • the output buffer 127 includes n output buffers 127-1 to 127-n, and each output buffer includes an operational amplifier.
  • the pointer shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-n based on the clock input signal input from the clock input terminal 102.
  • the latch circuit 124 selected by the pointer shift register circuit 123 stores the gradation output data from the gradation data input terminal 103.
  • the gradation output data corresponds to each latch circuit 124, in other words, corresponds to each signal output terminal 111 and is data synchronized with the clock input signal. Accordingly, each of the latch circuits 124-1 to 124-n can store gradation output data having different values corresponding to each signal output terminal 111.
  • the gradation output data stored in the latch circuits 124-1 to 124-n is transferred to the corresponding n number of hold circuits 125-1 to 125-n by the data LOAD signal. Further, the hold circuits 125-1 to 125-n output the gradation output data input from the latch circuits 124-1 to 124-n to the DAC circuits 126-1 to 126-n as digital data.
  • the DAC circuits 126-1 to 126-n select one voltage value among m kinds of gradation voltages based on the gradation output data from the hold circuit 125, and output buffers 127-1 to 127- output to n.
  • the DAC circuit 126 can output m types of gradation voltages depending on voltages input from the reference power supply terminal V0 terminal 105 to the V4 terminal 109.
  • the output buffer 127 buffers the gradation voltage from the DAC circuit 126 and outputs it as a liquid crystal panel drive signal to the signal output terminals 111-1 to 111-n.
  • the same number of shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 as the liquid crystal drive signal output terminals 111 are required, and the liquid crystal drive signal output terminals 111 are 1000 in number. If it is a terminal, 1000 of each of the circuits 124 to 127 is required.
  • the display driving semiconductor integrated circuit needs to give a signal of gradation voltage of R, G, B for each data line.
  • the number of outputs of one display driving semiconductor integrated circuit is 720, eight display driving semiconductor integrated circuits are required.
  • a semiconductor integrated circuit for display driving is tested at a wafer stage, is subjected to a shipping test after being packaged, and a display test is performed after being mounted on a liquid crystal panel. Furthermore, semiconductor integrated circuits that may cause initial failures are removed by screening tests such as burn-in and stress tests. Therefore, a display device on which a display driving semiconductor integrated circuit in which display failure occurs is not shipped to the market. However, a display defect rarely occurs while using the display device due to a very small defect or a foreign matter adhering and mixing that has not been determined to be defective during a pre-shipment test or a screening test.
  • the display defect occurrence rate is 57.6 ppm (57.6 / 1,000,000). That is, about one in about 17361 units will cause display defects, and the larger the size and the higher definition, the higher the rate of occurrence of display defects.
  • the display driving semiconductor integrated circuit is provided with a spare circuit provided for the defective circuit, and the defective circuit is switched to the spare circuit, so that the defect of the display driving semiconductor integrated circuit is eliminated. Avoidance is disclosed.
  • the display driving semiconductor integrated circuit includes a spare parallel circuit at each stage of the shift register, and performs a self-inspection of the shift register.
  • a technique for avoiding display defects caused by a defective shift register by selecting one having no defect is disclosed.
  • a selector is provided at the input and output of the DAC circuit, and the selector is switched based on the RAM information in which the position of the defective DAC circuit is stored, and a DAC circuit without a defect is selected. A method of using the same is disclosed.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 6-208346 (published July 26, 1994)” Japanese Patent Publication “Japanese Patent Laid-Open No. 8-278771 (published on October 22, 1996)”
  • the result of self-detection is stored in a memory built in the drive circuit.
  • the memory built in the drive circuit is practically difficult to make a nonvolatile memory from the viewpoint of cost, and a volatile memory is usually used, but the power supply is also common to the drive circuit. Therefore, in the case where the defect detection information is stored in the volatile memory inside the drive circuit, the defect detection information is lost when the power supply of the drive circuit is shut off.
  • Patent Document 1 and Patent Document 2 do not disclose any self-detection method for detecting a defect in an output circuit such as a DAC circuit.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a self-detecting and self-repairing drive circuit capable of self-detecting and self-repairing output blocks around the output circuit.
  • An object of the present invention is to provide a display device that does not need to perform self-detection every time it is repaired.
  • a display device is a display panel and a drive circuit that drives the display panel, and detects and repairs a defect in the drive circuit.
  • a storage device for storing defect detection information indicating a detection result of the failure of the drive circuit by the self-detection / self-repair means the storage device comprising the drive circuit It is characterized by being provided outside.
  • the drive circuit drives the display panel.
  • the drive circuit can detect a failure of the drive circuit itself and has self-detection / self-repair means for repairing the detected failure.
  • the storage device stores defect detection information indicating a detection result of the defect of the drive circuit by the self-detection / self-repair means.
  • storage device which memorize
  • the storage device may be a non-volatile memory such as a flash memory, or may be a volatile RAM having a circuit configuration to which a power supply voltage is always applied.
  • the defect detection information can be stored in the storage device provided independently of the drive circuit, the defect detection information can be stored even after the power of the drive circuit is shut off. Can be held. Therefore, when performing self-repair, it is not necessary to perform self-detection every time, and the self-repair operation can be performed in a short time.
  • the drive circuit includes an output circuit that outputs an output signal for driving the display panel, and the self-detection / self-repair means determines whether the output circuit is defective.
  • the drive circuit includes the output circuit that outputs an output signal for driving the display panel.
  • the output circuit converts, for example, video data into a gradation voltage and outputs it as an output signal for driving the display panel.
  • the self-detecting / self-repairing unit includes the determining unit that determines whether or not the output circuit is defective.
  • the display panel The drive circuit is self-repaired so that a normal output signal is output.
  • the display device can detect a defect in the output circuit of the drive circuit and can self-repair when the output circuit is defective.
  • the drive circuit includes a preliminary output circuit capable of outputting the output signal to the display panel, and the self-detection / self-recovery means has a poor determination result of the determination means.
  • the self-detection / self-recovery means has a poor determination result of the determination means.
  • switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit.
  • the drive circuit includes a spare output circuit that can output an output signal to the display panel. Similar to the output circuit, the preliminary output circuit can convert, for example, video data into a gradation voltage and output it as an output signal for driving the display panel.
  • the self-detecting / self-repairing means includes the switching means for switching the output circuit determined to be defective by the determining means to the spare output circuit.
  • the drive circuit when the output circuit is defective, the drive circuit can be easily repaired by switching the defective output circuit to the spare output circuit.
  • the determination unit includes a comparison unit that compares the output signal from the output circuit and the output signal from the preliminary output circuit, and based on the comparison result of the comparison unit, It is preferable to determine whether or not the output circuit is defective.
  • the determination means includes the comparison means.
  • the comparing means compares the output signal from the output circuit with the output signal from the standby output circuit. Then, the determination unit determines whether or not the output circuit is defective based on the comparison result of the comparison unit.
  • the output circuit failure can be determined by comparing the output of the output circuit and the output of the standby output circuit, so the output circuit failure can be easily detected with a simple configuration. can do.
  • the display device further includes control means for controlling an input signal input to the output circuit and the spare output circuit, and the control means has different sizes for the output circuit and the spare output circuit.
  • control means controls the input signals input to the output circuit and the standby output circuit, and inputs the input signals having different magnitudes. Further, the control means outputs an expected value of the comparison result from the comparison means corresponding to the input signals having different sizes. Then, the determination means determines that the output circuit is defective when the actual comparison result from the comparison means is different from the expected value from the control means.
  • an input signal of gradation m is input to the output circuit, and an input signal of gradation m + 1 is input to the standby output circuit.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the comparison means outputs a signal indicating that the gradation voltage input from the auxiliary output circuit is higher.
  • the comparator means that the gradation voltage input from the output circuit is higher. The signal shown is output.
  • the comparison means compares the grayscale voltages output from the output circuit and the spare output circuit, and outputs signals having different values depending on whether the output circuit is defective or not. Output.
  • the determining means determines whether or not the output circuit is defective based on the signal output from the comparing means. Specifically, as described above, when an input signal of gradation m is input to the output circuit and an input signal of gradation m + 1 is input to the standby output circuit, the gradation voltage from the output circuit is high. When the signal shown is input from the comparison means, the output circuit is determined to be defective. On the other hand, when a signal indicating that the gradation voltage from the preliminary output circuit is high is input from the comparison unit, the determination unit determines that the output circuit is not defective.
  • the display device includes specific means for easily detecting a defect in the output circuit, and can self-repair when the output circuit is defective.
  • the determination unit includes a comparison unit that compares output signals from at least two output circuits among the plurality of output circuits, and the output circuit is based on a comparison result of the comparison unit. It is preferable to determine whether or not is defective.
  • the determination means includes the comparison means.
  • the comparing means compares output signals from at least two output circuits among the plurality of output circuits. Then, the determination unit determines whether or not the output circuit is defective based on the comparison result of the comparison unit.
  • the output circuit defect can be determined by comparing the output of the output circuit, the output circuit defect can be easily detected with a simple configuration.
  • the display device further includes control means for controlling an input signal inputted to at least two output circuits among the plurality of output circuits, and the control means has different sizes for the at least two output circuits.
  • control means for controlling an input signal inputted to at least two output circuits among the plurality of output circuits, and the control means has different sizes for the at least two output circuits.
  • the control means controls the input signals input to at least two output circuits among the plurality of output circuits, and inputs the input signals having different sizes. Further, the control means outputs an expected value of the comparison result from the comparison means corresponding to the input signals having different sizes. Then, the determination means determines that the output circuit is defective when the actual comparison result from the comparison means is different from the expected value from the control means.
  • the input signal of gradation m is input to the first output circuit
  • the input signal of gradation m + 1 is input to the output circuit 2.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the comparison means outputs a signal indicating that the gradation voltage input from the second output circuit is higher.
  • the comparison means is input from the first output circuit. A signal indicating that the gradation voltage is higher is output.
  • the comparison unit compares the gradation voltages output from at least two output circuits among the plurality of output circuits, and the case where the output circuit is defective or not is determined. , Output signals of different values.
  • the determining means determines whether or not the output circuit is defective based on the signal output from the comparing means. Specifically, when different input signals are input to the two output circuits of the first output circuit and the second output circuit as described above, the input signal of the gradation m is input to the first output circuit. Then, when an input signal of gradation m + 1 is input to the second output circuit, when a signal indicating that the gradation voltage from the first output circuit is high is input from the comparison means, the determination means It is determined that at least one of the first output circuit and the second output circuit is defective. At this time, the first output circuit and the second output circuit are switched to a spare output circuit. On the other hand, when a signal indicating that the gradation voltage from the second output circuit is high is input from the comparison unit, the determination unit determines that the output circuit is not defective.
  • the display device includes specific means for easily detecting a defect in the output circuit, and can self-repair when the output circuit is defective.
  • the output circuit includes an operational amplifier as an output buffer, and the comparison means is a comparator including the operational amplifier.
  • the output circuit includes the operational amplifier as the output buffer.
  • the comparison means is a comparator constituted by an operational amplifier.
  • an output signal from an output circuit that drives a display panel is buffered and output to an output terminal.
  • the operational amplifier becomes a voltage follower circuit by negatively feeding back its output to its negative input terminal, and has a function as a buffer circuit.
  • the operational amplifier serves as both the buffer circuit for buffering the output signal from the output circuit and the comparator means. become. Therefore, the drive circuit according to the present invention does not need to include a separate buffer circuit for buffering the output signal from the output circuit, and has an effect of reducing cost.
  • the operational amplifier preferably operates as a voltage follower when driving the display panel.
  • the storage device is preferably a nonvolatile memory.
  • the display device may further include a writing control means for writing the defect detection information in the storage device before turning off the power when receiving an instruction to turn off the power of the display device itself. preferable.
  • the writing control means when receiving an instruction to turn off the power of the display device itself, the writing control means writes the defect detection information in the storage device before turning off the power. That is, when the power is turned off by a user operation or timer setting, the result of the self-diagnosis is transferred to and stored in a storage device outside the drive circuit, and then the power is turned off.
  • the defect detection information indicating the result of self-detection performed during the startup of the display device can be reliably stored in the storage device before shutting off the power supply of the display device. It is not necessary to detect a defective output circuit again.
  • the self-detecting / self-recovering means detects a failure of the driving circuit before turning off the power when receiving an instruction to turn off the power of the display device itself.
  • the self-detecting / self-recovering means detects a failure of the drive circuit before turning off the power when receiving an instruction to turn off the power of the display device itself. That is, when the power is turned off due to a user operation or timer setting, a self-diagnosis is performed, and the determination result is transferred to a storage device outside the drive circuit and stored, and then the power is turned off.
  • the self-detection is performed after the user finishes viewing the display device, that is, while the user is not aware, the user is not disturbed by the self-detection operation of the drive circuit, and convenience is improved. To do.
  • the self-detecting / self-repairing means receives the instruction to turn on the power of the display device itself, and based on the defect detection information read from the storage device, It is preferable to repair the defect.
  • the self-detection / self-repair means when the self-detection / self-repair means receives an instruction to turn on the power of the display device itself, the self-detection / self-repair means reads the failure detection information from the storage device, and based on the read failure detection information, Repair the defect.
  • the self-repair operation is performed before the user starts viewing the display device, that is, without the user's awareness, the user is not hindered by the self-repair operation of the drive circuit.
  • the self-repair operation is performed based on the self-detection result already stored in the storage device, it does not take a long time to complete the self-repair, and the convenience for the user is improved.
  • the television system according to the present invention may be configured to include any of the display devices described above.
  • the display device includes a display panel, a drive circuit for driving the display panel, a drive circuit having self-detection / self-repair means for detecting and repairing a defect in the drive circuit, and the self-detection.
  • a display device including a storage device that stores failure detection information indicating a detection result of the failure of the drive circuit by self-repair means, wherein the storage device is provided outside the drive circuit; It is a feature.
  • the defect detection information can be retained even after the power supply of the drive circuit is shut off, when performing self-repair, it is not necessary to perform self-detection every time.
  • the repair operation can be performed in a short time.
  • FIG. 1 is a block diagram illustrating a configuration of a liquid crystal television according to an embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus based on one Embodiment of this invention. It is a figure which shows the external appearance of the liquid crystal television based on one Embodiment of this invention. It is a figure which shows an example of a display when abnormality generate
  • FIG. 1 It is a figure which shows the example of the self-detection and self-repair operation in the liquid crystal television based on one Embodiment of this invention
  • (a) is a figure which shows the liquid crystal television before the start of self-detection and self-repair operation
  • (B) is a figure which shows the liquid crystal television in self-detection and self-repair operation
  • (c) is a figure which shows the liquid crystal television after completion of self-detection and self-repair operation
  • FIG. 1 It is a figure which shows the example of the self-detection and self-repair operation in the liquid crystal television based on one Embodiment of this invention
  • (a) is a figure which shows the liquid crystal television before the start of self-detection and self-repair operation
  • (B) is a figure which shows the liquid crystal television in self-detection and self-repair operation
  • (c) is a figure which shows the liquid crystal television after completion of self-detection and self-repair operation
  • FIG. 1 It is a figure which shows the example which mounted the TFT-LCD module which comprises the liquid crystal television based on one Embodiment of this invention, ie, the source driver and spare source driver which drive a display panel in a display part. It is the schematic showing the state which mounted in parallel the source driver provided with the self-detection and self-repair function and spare source driver on the glass substrate using the tape carrier based on one Embodiment of this invention. It is a figure which shows the state which opened the tape carrier shown in FIG. It is the top view which looked at the tape carrier with which the source driver shown in FIG. FIG.
  • FIG. 3 is a diagram showing an example in which a memory is mounted on a printed circuit board to which an input of a source driver is connected in a TFT-LCD module constituting a liquid crystal television, that is, a display unit, according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing another example in which a memory is mounted on a printed circuit board to which an input of a source driver is connected in a TFT-LCD module constituting a liquid crystal television, that is, a display unit, according to an embodiment of the present invention. is there. 4 is a flowchart illustrating a procedure for performing self-detection of a source driver when the display unit is powered off according to an embodiment of the present invention.
  • FIG. 1 It is a figure which shows an example of the self-detection and self-repair operation in the liquid crystal television based on one Embodiment of this invention, (a) is a figure which shows the liquid crystal television before a self-detection and self-repair operation, b) is a diagram showing a liquid crystal television during self-detection and self-repair operations, and (c) is a diagram showing a liquid crystal television after completion of self-detection and self-repair operations.
  • FIG. 1 It is a figure which shows an example of the self-detection and self-repair operation in the liquid crystal television based on one Embodiment of this invention
  • (a) is a figure which shows the liquid crystal television before a self-detection and self-repair operation
  • b) is a diagram showing a liquid crystal television during self-detection and self-repair operations
  • (c) is a diagram showing a liquid crystal television after completion of self-detection and self-repair operations.
  • It is explanatory drawing which shows the structure of the semiconductor integrated circuit for a display drive based on one Embodiment of this invention.
  • FIGS. 5A to 5F are time chart diagrams showing scanning signals, video signals, and pixel electrode voltage values input to a display device according to an embodiment of the present invention.
  • FIGS. It is a block diagram which shows the structure of the operation
  • Embodiment 1 A first embodiment of the present invention will be described below with reference to FIGS.
  • liquid crystal television 400 As a typical display device using a display driving circuit, a thin-screen television typified by a liquid crystal television can be given.
  • a liquid crystal television (liquid crystal display device) performs display by mounting a plurality of drive circuits created with a semiconductor integrated circuit (LSI) on a display panel.
  • LSI semiconductor integrated circuit
  • the user recognizes it as a direct display defect.
  • it is necessary to repair the defective part promptly, and it is desirable that the repair be completed in a short time at the place where the user is using if possible.
  • the present applicant has proposed a display driving circuit having a self-diagnosis self-repair function (self-detection and self-repair function) for a failure of the display drive circuit itself (for example, Japanese Patent Application No. 2008-130848, Application Nos. 2008-048640, Japanese Patent Application No. 2008-048639, and Japanese Patent Application No. 2008-054130: all unpublished at the time of confirmation prior to the filing of this application.
  • FIG. 1 shows a block diagram showing a configuration of a liquid crystal television 400 according to the present invention.
  • the liquid crystal television 400 includes a TFT-LCD module (display unit) 90, a switch button 401, a DVD device 402, an HDD device 403, and a DVD / HDD control device 404.
  • the display unit 90 includes a source driver (driving circuit, integrated circuit) 10a, a spare source driver 10b, a TFT-LCD panel (display panel) 80, a gate driver 99, and a controller 100.
  • the source driver 10a that is, the integrated circuit 10a is a display driving circuit having the above-described self-detection and self-repair functions.
  • the spare source driver 10b that is, the spare integrated circuit 10b may also be configured to have a self-detection and self-repair function.
  • the integrated circuits 10a and 10b that is, the generic names of the source drivers 10a and 10b are represented.
  • FIG. 2 is a block diagram illustrating a schematic configuration of the display unit 90.
  • the display unit 90 includes a display panel 80 and a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit or a source driver) that drives the display panel 80 based on gradation data input from the outside. ) 10.
  • the source driver that is, the integrated circuit 10 (driving circuit) includes a switching circuit 60 (self-detection / self-repairing means, switching means), a switching circuit 61 (self-detection / self-repairing means, switching means), and an output circuit block 30 (output).
  • the display panel 80 includes a pixel 70 to which the gradation voltage from the integrated circuit 10 is applied.
  • the display unit 90 has two basic operations as basic operations. Specifically, in the display unit 90, the integrated circuit 10 converts gradation data input from the outside into a gradation voltage (output signal), and displays an image on the display panel 80 based on the gradation voltage. A normal operation and a self-detection / repair operation in which the integrated circuit 10 detects whether or not the output circuit block 30 included in the integrated circuit 10 is defective and the output circuit block 30 is defective. It has two basic operations.
  • gradation data for operation confirmation is input to the output circuit block 30 and the spare output circuit block 40 from the outside via the switching circuit 61.
  • Each of the output circuit block 30 and the spare output circuit block 40 converts the input gradation data into a gradation voltage and outputs the gradation voltage to the comparison determination circuit.
  • the comparison determination circuit 50 compares the gradation voltage from the output circuit block with the gradation voltage from the standby output circuit block, and determines whether or not the output circuit block is defective based on the comparison result.
  • the comparison / determination circuit 50 outputs a determination result (failure detection information) indicating whether or not the output circuit block is defective to the switching circuit 61 and the switching circuit 60.
  • the switching circuit 61 switches the output destination of the gradation data from the outside based on the determination result from the comparison determination circuit 50.
  • the switching circuit 60 receives the gradation voltage from each of the output circuit block 30 and the spare output circuit block 40, and displays the display panel from the inputted gradation voltages based on the determination result from the comparison determination circuit.
  • the gradation voltage to be output to 80 is selected.
  • the switching circuit 61 when the determination result indicating that the output circuit block 30 is defective is input, the switching circuit 61 has the same level as the gradation data output to the output circuit block 30 determined to be defective. The tone data is also input to the spare output circuit block 40.
  • the switching circuit 60 when a determination result indicating that the output circuit block 30 is defective is input to the switching circuit 60, instead of the gradation voltage from the output circuit block 30 determined to be defective, the switching circuit 60 outputs from the standby output circuit 40. The gradation voltage is output to the display panel 80. As a result, even if the output circuit block 30 becomes defective, the integrated circuit 10 can output a normal gradation voltage to the display panel 80 using the spare output circuit block instead.
  • the integrated circuit 10 includes the comparison determination circuit 50, the switching circuit 60, and the switching circuit 61, so that it can detect its own defect and can self-repair itself. It becomes.
  • the integrated circuit 10 includes a self-healing circuit (self-repairing means) that detects its own fault and further self-heals the fault.
  • the configuration of the source driver 10, that is, the integrated circuit 10, and details of self-detection and self-repair operations will be described later.
  • FIG. 3 is a view showing the appearance of the liquid crystal television 400.
  • the liquid crystal television 400 includes a switch button 401 (instruction means) for starting a self-detection operation.
  • the switch button 401 will be described in detail.
  • FIG. 4 is a diagram showing an example of display when an abnormality occurs in the output circuit block 30 constituting the integrated circuit 10 included in the liquid crystal television 400. As shown in FIG. 4, when there is an abnormality in the output circuit block 30, a vertical line appears on the display.
  • the liquid crystal television 400 is provided with a switch button 401 for instructing the start of self-detection and self-repair. Thereby, the user can start self-detection and self-repair in the liquid crystal television 400 at an arbitrary timing.
  • FIG. 5 is a diagram illustrating an example of self-detection and self-repair operation in the liquid crystal television 400
  • (a) is a diagram illustrating the liquid crystal television 400 before the start of the self-detection and self-repair operation
  • (b) is a diagram showing the liquid crystal television 400 during the self-detection and self-repair operations
  • FIG. 6C is a diagram showing the liquid crystal television 400 after the self-detection and self-repair operations are completed.
  • the switch button 401 when the switch button 401 is pressed, that is, when the start switch is turned on, the display once disappears as shown in FIG. For this reason, if there is a possibility that the user will mistake the failure, this phenomenon is clearly described in the instruction manual, and the display panel 80 (notification means) indicates that the display disappears for a while during the self-detection and self-repair operations. May be displayed on the screen, or may be configured to turn off the display after notifying by voice guidance or the like through a speaker (notification means).
  • the liquid crystal television 400 does not need to perform self-detection and self-repair every time the power is turned on. This saves time and saves power consumed for self-detection.
  • the switch button 401 can be used as a maintenance switch for the liquid crystal television 400 itself.
  • the controller 100 causes the display panel 80 to display a maintenance menu for the liquid crystal television 400 (for example, an operation menu such as clock setting, screen color adjustment, screen adjustment, etc.). ) Is displayed.
  • FIG. 6 is a diagram showing a display example of the maintenance menu in the liquid crystal television 400.
  • a menu for self-detection and self-repair is provided in this maintenance menu, and can be selected when a display failure occurs.
  • a menu for starting self-detection and self-repair operation (“3. Screen adjustment” in the example shown in FIG.
  • the source driver 10a Self-detection and self-repair operations begin. Further, when self-detection and self-repair are selected, the self-detection and self-repair operations are started after notifying that the display disappears for a while by means of screen display or voice guidance.
  • the switch button 401 is provided in the liquid crystal television 400, but the switch button 401 may be provided in the remote control. That is, when the switch button 401 provided on the remote control is pressed, a signal instructing self-detection and self-repair is transmitted to the liquid crystal television 400, and the liquid crystal television 400 transmits a signal of the drive circuit based on the received signal. Self-detection and self-repair are performed.
  • FIG. 7 is a diagram showing an example of self-detection and self-repair operations in the liquid crystal television 400
  • (a) is a diagram showing the liquid crystal television 400 before the start of the self-detection and self-repair operations
  • FIG. 4 is a diagram showing the liquid crystal television 400 during the self-detection and self-repair operations
  • FIG. 6C is a diagram showing the liquid crystal television 400 after the completion of the self-detection and self-repair operations.
  • the liquid crystal television 400 displays a screen indicating that the self-detection and the self-repair is in progress and informs the user of the current situation. it can.
  • the liquid crystal television 400 is shown in FIG. 7B by the integrated circuit 10 in order to electrically disconnect the source driver, that is, the integrated circuit 10 and the liquid crystal panel during the self-detection and self-repair operations. It is not possible to display a screen indicating that self-detection or self-repair is in progress. For this reason, the liquid crystal television 400 includes a spare source driver for performing the screen display shown in FIG. 7B. During the self-detection and self-repair operations, the liquid crystal television 400 uses the spare source driver. A screen is displayed indicating that detection and self-repair are in progress.
  • FIG. 8 is a diagram showing an example in which a TFT-LCD module constituting the liquid crystal television 400, that is, a source driver 10a for driving the display panel 80 in the display unit 90 is mounted.
  • the display unit 90 includes a source driver 10a, a gate driver 99, an FPC (film cable) 98, a PWD (printed circuit board) 97, a glass substrate 96, a source line 95, and a gate line 94.
  • a source line 95, a gate line 94, a TFT 93, a pixel 92, and a counter electrode 91 are formed to constitute a liquid crystal panel 80.
  • the source driver 10a and the gate driver 99 are mounted on one side of the glass substrate 96 of the liquid crystal panel 80, respectively.
  • the source driver 10 a supplies a display voltage, that is, a gradation voltage representing an image, to the pixel 92 via the source line 95.
  • the gate driver 99 supplies a gate signal indicating the ON timing of the TFT 93, that is, the timing of applying the gradation voltage to the pixel, through the gate line 94.
  • Inputs of the source driver 10a and the gate driver 99 are connected to the printed circuit board 97, and a control signal, a power supply voltage, and GND are given through the wiring of the printed circuit board 97.
  • Control signals, power supply voltages, GND, and the like are supplied from a control board (not shown), that is, a controller 100 connected via a film cable 98.
  • the display unit 90 may be configured to include a spare source driver.
  • FIG. 9 is a diagram showing an example in which the TFT-LCD module constituting the liquid crystal television 400, that is, the source driver 10a and the spare source driver 10b for driving the display panel 80 in the display unit 90 are mounted.
  • the source driver 10 a first drive circuit
  • the spare source driver 10b second drive circuit
  • FIG. 10 is a schematic diagram showing a state in which a source driver 10 a having a self-detection and self-repair function and a spare source driver 10 b are mounted in parallel on a glass substrate 96 using a tape carrier 89.
  • the source driver 10a and the spare source driver 10b are connected to the printed circuit board 97 on the input side, and are connected to the glass substrate 96 constituting the display panel 80 on the output side.
  • both the source driver 10 a and the source driver 10 b can be connected to the printed circuit board 97, and input signals can be supplied from the common circuit board 97.
  • FIG. 11 is a view showing a state where the tape carrier 89 shown in FIG. 10 is opened.
  • the source driver 10 a is connected to the input-side wiring 88 and the output-side wiring 86 at the device hole portion 115 where the film base 83 of the tape carrier 89 is removed.
  • the spare source driver 10b is connected to the input-side wiring 88 and the output-side wiring 86 of the film base 83 so as to face away from the source driver 10a.
  • the output terminals can be commonly connected on the tape carrier 89.
  • the source driver 10 a and the source driver 10 b can be mounted on the same side of the glass substrate 96 constituting the display panel 80.
  • FIG. 12 is a plan view of the tape carrier 89 on which the source drivers 10a and 10b shown in FIG. As shown in FIG. 11, an input terminal 84 and an operation switching input terminal 82 connected to the input side wiring 88 are formed at both ends of the tape carrier 89. Normally, an “L” signal is input to the operation switching input terminal 82, and the source driver 10 a operates and normal display is performed on the display unit 90. At this time, the spare source driver 10b does not operate.
  • the controller inputs a signal “H” to the operation switching input terminal 82.
  • the display unit 90 displays that the self-detection and self-repair operations are being performed.
  • the spare source driver 10b only needs to be able to perform simple display, and may be configured with an inexpensive driver having a small number of gradations.
  • an 8-gradation driver may be used as the spare source driver 10b.
  • the display control of the spare driver 10b can be performed by a control signal or a display data signal sent from the controller, similarly to the control by the source driver 10a.
  • a display memory is provided inside the spare source driver 10b. If the display contents are stored in advance, there is no need to constantly supply display data to the spare source driver 10b. If the display data is stored in the display memory before the display by the spare source driver 10b, the display data in the memory can be used. If the display content is determined, if the display content is fixed by setting the display memory to ROM (Read Only Memory) or OTP (One Time Prom), there is no need to give display data to the spare source driver 10b from the outside. Thus, display control can be easily performed with a simple configuration.
  • the failure determination of the output circuit block 30 is performed by the comparison determination circuit 50, and the determination result is stored as a determination flag (failure detection information) in the memory in the source driver.
  • the display unit 90 performs self-repair based on this determination flag, but it is necessary to store the determination flag even when power is not supplied to the source driver. That is, if the determination flag is lost, a defective output circuit cannot be identified, so that it is necessary to perform self-detection again, and each self-repair operation takes a long time.
  • the source driver memory is non-volatile, there is no problem. However, incorporating the non-volatile memory in the source driver leads to an increase in cost. Therefore, the memory in the source driver is usually volatile memory. is there. For this reason, when the power is shut off, the determination flag stored in the memory inside the source driver is erased.
  • the contents of the determination flag of the source driver are transferred to the external memory 81 (storage device) when the power is shut off, and conversely, when the power is turned on, the external memory 81 transfers the contents to the memory in the source driver. It has a mechanism for reading judgment flags.
  • FIG. 13 is a diagram showing an example in which the memory 81 is mounted on the printed circuit board 97 to which the input of the source driver 10a is connected in the TFT-LCD module constituting the liquid crystal television 400, that is, in the display unit 90.
  • the source driver 10a sets a serial I / O terminal for inputting / outputting a value of a volatile memory for storing a determination flag provided in each internal output circuit block as serial data, and writing of data to the memory 81. And a terminal for setting the reading of data from the memory 81.
  • the serial I / O terminal is connected to the memory 81, and data can be read and read between the volatile memory inside the source driver 10a and the external memory 81.
  • a signal instructing the reading of data from the memory 81 is supplied from the controller 100 to a terminal for setting the reading of data from the memory 81, and the source driver 10 a receives the data from the memory 81. Is set to a state in which reading is performed. Thereby, the data of the determination flag is read from the external memory 81 to the source driver 10a, and the volatile memory inside the source driver 10a stores the determination flag. This operation is performed for each source driver 10a, and determination flags are stored in the memories inside all the source drivers. Then, the switching circuits 60 and 61 switch between the defective output circuit block 30 and the spare output circuit block 40 based on the read determination flag, and perform self-repair of the source driver 10a.
  • FIG. 14 is a diagram showing another example in which the memory 81 is mounted on the printed circuit board 97 to which the input of the source driver 10a is connected in the TFT-LCD module constituting the liquid crystal television 400, that is, the display unit 90. .
  • the terminal for inputting / outputting the determination flag data of the source driver 10a is connected to the source driver, whereby the entire determination flag of the mounted source driver is serially written or read. can do.
  • the memory 81 uses a flash memory that is a non-volatile memory, but may be a volatile RAM.
  • a flash memory that is a non-volatile memory, but may be a volatile RAM.
  • a circuit configuration in which a voltage is always applied to the power source of the RAM it is necessary to provide a backup capacitor or battery in preparation for unexpected power shutoff.
  • the memory 81 is provided on the printed circuit board 97. However, the memory 81 is provided on another board such as a control board and connected via the film cable 98. May be.
  • FIG. 15 is a flowchart showing a procedure for performing self-detection of the source driver 10a when the display unit 90 is powered off.
  • this configuration instead of performing only self-repair and not performing self-detection when the power is turned on, self-detection is performed when the power is off.
  • the display unit 90 transfers the determination flag from the external memory 81 storing the determination flag to the memory inside the source driver 10a (S1502). Then, the source driver 10a performs self-repair based on this determination flag (S1503), and starts a normal operation such as displaying an image on the display panel 80 (S1504).
  • the display unit 90 determines whether or not a power-off command has been received at regular time intervals during normal operation (S1505). Then, the display unit 90 repeats the determination of whether or not the power-off command is received while the power-off command is not sensed (S1505: No).
  • the display unit 90 When the display unit 90 senses that a power-off command is sent from the switch or remote control to the liquid crystal television 400 (or the display unit 90) (S1505: Yes), the display unit 80 displays an image on the display panel 80. Is turned off (S1506). At this time, the display unit 90 itself and the power supply of the entire system including the display unit 90 are not turned off.
  • the comparison determination circuit 50 determines whether or not each output circuit constituting the source driver 10a is defective. That is, the display unit 90 performs self-detection of the source driver 10a, and stores a determination flag indicating the content of the determination result in a memory inside the source driver 10a (S1507).
  • the display unit 90 turns off the power supply to the source driver 10a and peripheral circuits (S1510).
  • the display unit 90 when an abnormality occurs in the output circuit block included in the source driver 10a and a display malfunction occurs, the display is restored by turning off the power and turning on the power again.
  • FIG. 16 is a diagram illustrating an example of the self-detection and self-repair operation in the liquid crystal television 400.
  • FIG. 16A is a diagram illustrating the liquid crystal television 400 before the self-detection and self-repair operation
  • FIG. It is a figure which shows the liquid crystal television 400 in detection and self-repair operation
  • (c) is a figure which shows the liquid crystal television 400 after completion of self-detection and self-repair operation
  • the liquid crystal television 400 is equipped with a DVD (Digital Versatile Disc or Digital Video Disc) device 402.
  • the DVD device 402 has functions such as DVD playback and recording.
  • the DVD / HDD control unit 404 controls various operations of the DVD device 402 (video playback device) in accordance with instructions from the user.
  • the cleaning disk is inserted to clean the pickup.
  • the DVD device 402 starts a cleaning operation based on a control signal from the DVD / HDD control unit 404 according to a user instruction.
  • the liquid crystal television 400 has a problem that vertical lines appear on the display screen.
  • the liquid crystal television 400 is characterized in that it is configured to perform self-detection of the source driver 10a at the timing of cleaning the DVD device 402 provided integrally. More specifically, when the DVD / HDD control unit 404 receives a signal indicating that cleaning has started from the DVD device 402, the DVD / HDD control unit 404 starts self-detection and self-repair of the source driver 10 a to the controller 100. A signal representing the indication is supplied. Then, according to an instruction from the controller 100, the source driver 10a starts self-detection and self-repair operations. Note that the DVD device 402 may be provided independently from the liquid crystal television 400.
  • FIG. 17 is a diagram illustrating an example of the self-detection and self-repair operations in the liquid crystal television 400.
  • FIG. 17A is a diagram illustrating the liquid crystal television 400 before the self-detection and self-repair operations
  • FIG. It is a figure which shows the liquid crystal television 400 in detection and self-repair operation
  • (c) is a figure which shows the liquid crystal television 400 after completion of self-detection and self-repair operation
  • the liquid crystal television 400 has a built-in HDD (Hard Disk Drive) device 403.
  • the HDD device 403 has functions such as playback and recording by the HDD.
  • the DVD / HDD control unit 404 controls various operations of the HDD device 403 (video playback device) in accordance with instructions from the user.
  • the HDD needs to perform maintenance such as organization of storage areas (for example, optimization of storage areas such as defragmentation and disk error check), and the HDD apparatus 403 is a DVD / HDD control unit in accordance with a user instruction. Based on the control signal from 404, the maintenance operation is started. Recording and playback are not possible during maintenance. Therefore, it is necessary to perform maintenance of the storage area of the HDD device 403 at a time when the user is not using it.
  • maintenance such as organization of storage areas (for example, optimization of storage areas such as defragmentation and disk error check)
  • the HDD apparatus 403 is a DVD / HDD control unit in accordance with a user instruction. Based on the control signal from 404, the maintenance operation is started. Recording and playback are not possible during maintenance. Therefore, it is necessary to perform maintenance of the storage area of the HDD device 403 at a time when the user is not using it.
  • the liquid crystal television 400 is configured to allow the user to designate an unused time (for example, midnight) and perform maintenance at the designated time. That is, the HDD device 403 has a timer function capable of performing maintenance at a preset time. Further, as shown in FIG. 17A, the liquid crystal television 400 has a problem that vertical lines appear on the display screen.
  • the liquid crystal television 400 is characterized in that it is configured to perform self-detection of the source driver 10a at the timing of maintenance of the HDD provided integrally.
  • the DVD / HDD control unit 404 when the DVD / HDD control unit 404 receives a signal indicating that the storage area optimization has started from the HDD device 403, the DVD / HDD control unit 404 causes the controller 100 to perform self-detection and self-detection of the source driver 10a. A signal representing an instruction to initiate repair is provided. Then, according to an instruction from the controller 100, the source driver 10a starts self-detection and self-repair operations.
  • the HDD device 403 may be provided independently from the liquid crystal television 400.
  • the self-detection is performed at a time when the user does not use it, it is not necessary to display that the HDD is being maintained, and the display may be off as shown in FIG. For example, it may be possible to forget that the maintenance is in progress and to perform display, so that the above-described spare source driver 10b may be mounted to perform simple display.
  • FIG. 17C shows a screen state when the display is performed again after the maintenance is completed, and reports that the maintenance is completed to the user. As shown in FIG. 17 (c), the problem that vertical lines appear on the display screen of FIG. 17 (a) is eliminated.
  • the determination flag stored in the internal memory of the source driver 10a is stored in the external memory.
  • the determination flag is read again into the memory in the source driver 10a to reproduce self-repair.
  • the configuration of the source driver 10a according to the present invention will be described with reference to FIG.
  • the spare source driver 10b can have a simpler configuration than the source driver 10a, but can also have the same configuration as the source driver 10a.
  • a circuit capable of performing self-detection and self-recovery operations similar to those of the source driver 10a will be referred to as an integrated circuit 10 and will be described.
  • FIG. 18 is an explanatory diagram showing the configuration of the integrated circuit 10 (drive circuit).
  • the integrated circuit 10 includes n liquid crystal driving signal output terminals OUT1 to OUTn (hereinafter referred to as output terminals OUT1 to OUTn) via a data bus from a grayscale data input terminal (not shown).
  • N sampling circuits 6-1 to 6-n hereinafter collectively referred to as sampling circuit 6
  • n hold circuits 7-1 to 7-n hereinafter collectively referred to as a hold circuit 7
  • n DAC circuits 8-1 to 8-n hereinafter collectively referred to as “hold circuit 7” that convert gradation data into gradation voltage signals.
  • DAC circuit 8 n operational amplifiers 1-1 to 1-n (hereinafter collectively referred to as operational amplifier 1) having a role of a buffer circuit for the gradation voltage signal from the DAC circuit 8, n judgment circuits 3-1 3-n (hereinafter collectively referred to as determination circuit 3), n determination flags 4-1 to 4-n (hereinafter collectively referred to as determination flag 4), n number of determination flags Pull-up / pull-down circuits 5-1 to 5-n (hereinafter collectively referred to as pull-up / pull-down circuits 5) are provided.
  • the integrated circuit 10 includes a plurality of switches 2 a that are turned on and off by a test signal, a plurality of switches 2 b that are turned on and off by a test B signal, and an output signal from the determination flag 4.
  • switches 2c connection switching means
  • 2d connection switching means
  • the switches 2a, 2b, and 2d are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned off when an “H” signal is inputted, and is turned on when an “H” signal is inputted.
  • the integrated circuit 10 includes a spare sampling circuit 26, a spare hold circuit 27, a spare DAC circuit 28 (spare output circuit), and a spare operational amplifier 21, one for each circuit.
  • the sampling circuit 6, the hold circuit 7, and the DAC circuit 8 correspond to the output circuit block 30 shown in FIG. 2, and the sampling circuit 26, the hold circuit 27, and the DAC circuit 28 are shown in FIG.
  • the operational amplifier 1, the determination circuit 3, and the determination flag 4 correspond to the preliminary circuit block 40 shown, the comparison determination circuit 50 shown in FIG. 2, and the switches 2d and 2c connected to the output terminals OUT1 to OUTn. 2 corresponds to the switching circuit 60 shown in FIG. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in FIG.
  • the integrated circuit 10 shown in FIG. 18 is connected to the display panel 80 shown in FIG. 2 via the output terminals OUT1 to OUTn, and the display panel 80 is not shown in FIG.
  • the test signal is “L” and the test B signal is “H”.
  • the switch 2a is turned off and the switch 2b is turned on.
  • the corresponding sampling circuits 6 input STR1 to STRn signals (hereinafter collectively referred to as STR signals), which are signals from a pointer shift register (not shown).
  • STR signals are signals from a pointer shift register (not shown).
  • the sampling circuit 6 acquires gradation data corresponding to itself from the gradation data input terminal via the data bus.
  • the hold circuit 7 inputs the gradation data acquired by the sampling circuit 6 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 (output circuit) inputs gradation data from the hold circuit 7.
  • the DAC circuit 8 converts the input gradation data into a gradation voltage signal, and outputs the gradation voltage signal to the positive input terminal of the operational amplifier 1 (comparing means).
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 serves as a buffer circuit for the grayscale voltage from the DAC circuit 8, and the grayscale voltage signal input to its positive input terminal is used as the corresponding output terminals OUT1 to OUTn. Output to.
  • the switch 2c is ON and the switch 2d is OFF. The operation of the switches 2c and 2d will be described later.
  • the output circuit block has gradation
  • An object of the present invention is to convert gradation data input from a data input terminal into a gradation voltage for driving the display panel 80, and to output the converted gradation voltage to the display panel 80 via an output terminal.
  • test signal and the test B signal are output from a control circuit (not shown) that controls switching of the operation check test and operation of the operation check test.
  • the control circuit is also a circuit for controlling gradation data and a data LOAD signal input via the data bus in the operation check test. Further, the control circuit may be the same as or different from the control circuit that controls the gradation data, the data LOAD signal, and the shift clock input signal during normal operation.
  • FIG. 19 is a flowchart showing a first procedure of the operation check test according to the first embodiment.
  • step S21 (hereinafter abbreviated as S21) shown in the figure, the test signal is set to “H” and the test B signal is set to “L”.
  • the operational amplifier 1 serves as a comparator by S21.
  • a counter m provided in a control circuit (not shown) is initialized to zero. Further, the control circuit activates the gradation data corresponding to the value of the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR1 signal, and the spare sampling circuit 26 via the data bus. To store. Further, the control circuit samples the gradation data of gradation m + 1 obtained by adding 1 to the value of the counter m, the gradation data of gradation 1 here, the TSTR2 signal active, and the data via the data bus. Store in circuit 6. Next, the spare hold circuit 27 acquires gradation data of gradation 0 from the sampling circuit 26 based on the data LOAD signal.
  • the DAC circuit 28 receives the gradation data from the hold circuit 27 and outputs a gradation voltage of gradation 0 to the negative input terminal of the operational amplifier 1 (S23).
  • the hold circuit 7 acquires gradation data of gradation 1 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 inputs gradation data from the hold circuit 7.
  • Each DAC circuit 8 outputs a gradation voltage of gradation 1 to the positive input terminal of each operational amplifier 1 connected in series with itself (S23).
  • the integrated circuit 10 of the present invention outputs an n gradation voltage, the gradation voltage of gradation 0 is the lowest voltage value, and the gradation voltage of gradation n is the lowest. It is assumed that the voltage value is high.
  • the operational amplifier 1 compares the gradation voltage from the DAC circuit 8 input to the positive input terminal and the gradation voltage from the DAC circuit 28 input to the negative input terminal (S24). Specifically, the operational amplifier 1 inputs a gradation voltage of gradation 1 to its own positive input terminal, and inputs a gradation voltage of gradation 0 to its own negative input terminal. If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs an “H” level signal. Here, if the output of the operational amplifier is an “L” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 (determination means) receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. Note that the expected value stored by the determination circuit 3 is given by the control circuit. In this operation check test 1, the determination circuit 3 stores the expected value as the “H” level.
  • the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is at the “H” level, which is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “L” level, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory. (S25) The determination circuit 3 receives the output signal from the operational amplifier 1 and outputs an “L” flag to the determination flag 4 if the input signal is “H” level, and the input signal is “L” level.
  • the configuration may be such that the “H” flag is output to the determination flag 4.
  • the determination flag 4 holds the “H” flag even if the “L” flag is input from the determination circuit 3 thereafter. Continue.
  • the subsequent determination operation may not be performed.
  • n is the number of gradations that the integrated circuit 10 can output.
  • FIG. 20 is a flowchart showing a second procedure of the operation check test according to the first embodiment.
  • the determination circuit 3 outputs an “L” flag indicating normality.
  • the operation check test 2 is performed by inputting a gradation voltage lower than that of the negative input terminal to the positive input terminal of the operational amplifier 1.
  • the control circuit activates the TSTR1 signal for the gradation data of gradation m + 1, in this case, the gradation data of gradation m + 1 by adding 1 to the value of the counter m, and reserves the data via the data bus. Is stored in the sampling circuit 26.
  • the control circuit activates the gradation data corresponding to the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR2 signal to the sampling circuit 6 via the data bus. Store.
  • the DAC circuit 28 inputs the gradation data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 outputs the gradation voltage of gradation m + 1 corresponding to the inputted gradation data, here, the gradation voltage of gradation 1 to the negative input terminal of the operational amplifier 1.
  • the DAC circuit 8 inputs the gradation data stored by the sampling circuit 6 via the hold circuit 7. Further, each DAC circuit 8 has a gradation voltage of gradation m corresponding to the inputted gradation data, here a gradation voltage of gradation 0, of each operational amplifier 1 connected in series to itself. Output to the positive input terminal (S32).
  • the operational amplifier 1 compares the gradation voltage of gradation 0 from the DAC circuit 8 input to the positive input terminal with the gradation voltage of gradation 1 from the DAC circuit 28 input to the negative input terminal. (S33). If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs a signal of the “L” flag. Here, if the output of the operational amplifier is an “H” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. In this operation check test 1, the determination circuit 3 stores the expected value as the “L” level. Here, the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is the “L” level that is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “H”, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory (S34). The above steps S33 to S34 are repeated until the value of m becomes n ⁇ 1 (S35, S36).
  • FIG. 21 is a flowchart showing a third procedure of the operation check test according to the first embodiment.
  • the operational amplifier 1 when there is a problem that the output is open, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 by the executed confirmation test, and the malfunction is confirmed in the operation confirmation tests 1 and 2. It may not be detected.
  • the operation check test 3 a pull-down circuit is connected to the positive input terminal of the operational amplifier 1.
  • a low voltage is input to the positive input terminal of the operational amplifier 1.
  • the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 according to the executed confirmation test. Can be prevented.
  • the specific procedure of the operation check test 3 is as follows. First, the counter m is initialized to 0 (S41). Next, the pull-up / pull-down circuit 5 pulls down the positive input terminal of the operational amplifier 1 (S42). Steps S43 to S47 from here are the same as the steps S23 to S27 of the operation check test 1 already described above, and the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling down the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 1, the operational amplifier 1 outputs the “L” level signal. Will be output. As a result, the determination circuit 3 determines from the inputted “L” level signal that the DAC circuit 8 is defective, and the determination flag 4 stores the “H” flag.
  • FIG. 22 is a flowchart showing a fourth procedure of the operation check test according to the first embodiment.
  • the operation check test 4 is for dealing with a problem that the output of the DAC circuit 8 is open.
  • the counter m is initialized to 0 (S51).
  • the pull-up / pull-down circuit 5 pulls up the positive input terminal of the operational amplifier 1 (S52).
  • the subsequent steps S53 to S57 are the same as the steps S32 to S36 of the operation check test 2 already described above, and therefore the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling up the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 2, the operational amplifier 1 outputs the “H” level signal. Will be output. As a result, the determination circuit 3 determines that the DAC circuit 8 has a problem from the input “H” level signal, and the determination flag 4 stores “H”.
  • FIG. 23 is a flowchart showing the fifth procedure of the operation check test according to the first embodiment.
  • the DAC circuit 8 there may be a problem that two adjacent gradations in itself are short-circuited. As described above, when two adjacent gradations are short-circuited, the DAC circuit 8 outputs an intermediate voltage between the two short-circuited gradations. In the case of this defect, the gradation voltage output from the DAC circuit 8 does not cause a voltage shift of one gradation or more compared to a normal case. Therefore, this malfunction cannot be detected in the operation confirmation tests 1 to 4.
  • the purpose of the operation check test 5 is to detect a problem in which the two adjacent gradations in the DAC circuit 8 are short-circuited.
  • the counter m is initialized to 0 (S61).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m and here gradation data of gradation 0 are input to sampling circuit 26 and sampling circuit 6 via a data bus.
  • the DAC circuits 28 and 8 acquire gradation data of gradation 0 from the sampling circuits 26 and 6 via the hold circuits 27 and 7. Further, the DAC circuits 28 and 8 output a gradation voltage of gradation 0 to the positive input terminal and the negative input terminal of the operational amplifier 1 (S62).
  • the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited by a switch (not shown). If it is determined in the operation check tests 1 and 2 that the DAC circuit 8 is not defective, the difference between the gradation voltages input to the positive input terminal and the negative input terminal is equal to or greater than one gradation. There is no voltage difference. Therefore, there is no problem that a large current flows by short-circuiting the positive input terminal and the negative input terminal.
  • the two input terminals of the operational amplifier 1 input the same gradation voltage.
  • the operational amplifier 1 since the operational amplifier 1 originally has an input / output offset voltage, the output of the operational amplifier 1 is “H” or “L” even if the same gradation voltage is input to its two input terminals. Either of these will be output.
  • the determination circuit 3 stores the output level of the operational amplifier 1 when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S63).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the gradation voltage of gradation 0 from the DAC circuit 8 is input to the positive input terminal of the operational amplifier 1
  • the gradation voltage of gradation 0 from the DAC circuit 28 is input to the negative input terminal. Is done.
  • the determination circuit 3 compares the output from the operational amplifier 1 with the expected value stored by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs the “H” flag to the determination flag 4 (S65).
  • the gradation voltage from the DAC circuit 28 is input to the positive input terminal of the operational amplifier 1 and the gradation voltage from the DAC circuit 8 is input to the negative input terminal by a switch (not shown).
  • the input is switched (S66).
  • the same processing as S64 is performed (S67).
  • the determination circuit 3 if the output from the operational amplifier 1 is different from the expected value stored in the determination circuit 3, the determination circuit 3 outputs an “H” flag to the determination flag 4 (S68). In this way, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the expected value stored in the determination circuit 3 is either the “H” level or the “L” level, the problem of the DAC circuit 8 is prevented. It can be detected.
  • FIG. 24 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuit 28 and performing self-repair.
  • the determination circuit 3 determines that the DAC circuit 8 is defective, the determination circuit 3 outputs an “H” flag to the determination flag 4. Further, the determination flag 4 receives the “H” flag from the determination circuit 3 and stores it in the inside thereof.
  • the control circuit detects whether or not the determination flag 4 records “H” (S71). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S75. On the other hand, when the control circuit detects that the determination flag 4 stores “H”, the control circuit checks the number of “H” flags stored in each of the determination flags 4-1 to 4-n. Here, when the number of “H” flags stored in the determination flag 4 is plural, the process proceeds to S73. On the other hand, when the number of “H” flags stored in the determination flag 4 is one, the process proceeds to S74 (S72).
  • Judgment flag 4-1 outputs an output signal of Flag1 which becomes “H” level to the switches 2c and 2d.
  • the switch 2c to which the “H” level signal is input is turned OFF and the switch 2d is turned ON by the output signal of Flag1.
  • the switch 2c cuts off the connection between the output from the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1.
  • the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit 26.
  • the gradation data corresponding to the liquid crystal driving signal output terminal OUT1 also stores the sampling circuit 26.
  • the switch 2d connects the output of the operational amplifier 21 and the liquid crystal driving signal output terminal OUT1.
  • the switches 2c and 2d are switched by the output signal of Flag1 from the determination flag 4-1, so that the defective DAC circuit 8-1 is switched to the spare DAC circuit 28.
  • the integrated circuit 10 can switch the defective DAC circuit to the spare DAC circuit 28 by performing the operation check tests 1 to 5 and the self-repair process. Further, in the first embodiment, a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28 are provided. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 25 is a flowchart showing a processing procedure from when the display device is turned on until the operation check test is performed and the normal operation is started.
  • FIG. 26 is an explanatory diagram showing the configuration of the operational amplifier 1 and peripheral circuits for checking the operation of the operational amplifier 1.
  • the positive input terminal of the operational amplifier 1 is connected to a switch S5 for switching input between an output from the DAC circuit 8 and a predetermined voltage. Further, a switch S3 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S5. On the other hand, the negative input terminal of the operational amplifier 1 is connected to a switch S6 for switching input between an output of the operational amplifier 1 for performing negative feedback from the operational amplifier 1 and a predetermined voltage. Further, a switch S4 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S4.
  • the operational amplifier 1 operates as a voltage follower circuit by setting the switch S5 to the A side (output side of the DAC circuit 8) and the switch S6 to the A side.
  • the switches S1 and S2 are switched to the B side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 operates as a comparator.
  • the switches S3 and S4 are switched to the A side.
  • Vref1 is input to the positive input terminal of the operational amplifier 1
  • Vref2 is input to the negative input terminal.
  • Vref1 and Vref2 are voltages generated in advance, and the voltage value of Vref1 is larger than the voltage value of Vref2.
  • the difference in voltage value between Vref1 and Vref2 is set to a value larger than the input / output offset value of the operational amplifier 1.
  • the operational amplifier 1 outputs a signal of “H” level because the voltage of Vref1 input to the positive input terminal is higher than Vref2 input to the negative input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “H” stored by itself. Here, when the output of the operational amplifier 1 is at the “L” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the expected value stored by the determination circuit 3 is given by the control circuit.
  • the switches S3 and S4 are switched to the B side, Vref2 is input to the positive input terminal of the operational amplifier 1, and Vref1 is input to the negative input terminal.
  • the operational amplifier 1 outputs the “L” level because the voltage value of Vref1 input to the negative input terminal is higher than Vref2 input to the positive input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “L” stored by itself. Here, when the output of the operational amplifier 1 is at the “H” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the switches S3 to S6 are switched by the control circuit.
  • the operational amplifier 1 compares the output of the DAC circuit 8 with the output of the spare DAC circuit 28.
  • two adjacent DAC circuits 8 are set as one set, and the outputs from the DAC circuits 8 are compared in the operational amplifier 1.
  • FIG. 27 is an explanatory diagram showing a configuration of the integrated circuit 20 (integrated circuit for driving the display device).
  • the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier 1 to its positive input terminal. Furthermore, the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier adjacent to the operational amplifier 1 to its negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8-1 to its positive input terminal, and outputs the output from the DAC circuit 8-2. It inputs to its own negative input terminal via the switch 2a. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8-2 to its own positive input terminal, and outputs the output from the DAC circuit 8-1 through its switch 2a to its own negative input terminal. To enter.
  • the integrated circuit 20 also includes spare sampling circuits 26A and 26B, spare hold circuits 27A and 27B, spare DAC circuits 28A and 28B, operational amplifiers 21A and 21B, and pull-up / pull-down circuits 25A and 25B.
  • the output from the DAC circuit 28A is input to its own positive input terminal, and the output from the DAC circuit 28B is input to its own negative input terminal via the switch 2a.
  • the output from the DAC circuit 28B is input to its own positive input terminal, and the output from the DAC circuit 28A is input to its own negative input terminal via the switch 2a.
  • the control circuit sets the test signal to the “L” level and the test B signal to the “H” level.
  • the DAC circuit 8 converts the grayscale data input from the hold circuit 7 into a grayscale voltage signal and outputs the grayscale voltage to the positive input terminal of the operational amplifier 1.
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 buffers the gradation voltage from the DAC circuit 8 and outputs it to the corresponding output terminals OUT1 to OUTn.
  • the control circuit sets the test signal to the “H” level and sets the test B signal to the “L” level.
  • the switch 2a is turned ON, the TSTR1 signal is sent to the sampling circuit 26A and the odd-numbered sampling circuits 6 (sampling circuits 6-1, 6-3,..., 6- (n ⁇ 1)). Entered. Further, the TSTR2 signal is input to the sampling circuit 26B and the even-numbered sampling circuits 6 (sampling circuits 6-2, 6-3,..., 6-n).
  • the switch 2a when the switch 2a is turned ON, the output from the adjacent even-numbered DAC circuit 8 is input to the negative-polarity input terminal of the odd-numbered operational amplifier 1, and the negative-polarity input terminal of the even-numbered operational amplifier 1 is input. Are supplied with outputs from adjacent odd-numbered DAC circuits 8. Further, when the test B signal becomes “L” level, the switch 2b is turned OFF. As a result, negative feedback of the output of the operational amplifier 1 to the negative input terminal is cut off. As a result, the operational amplifier 1 becomes a comparator that compares the output from the DAC circuit 8 connected in series with the operational amplifier 1 with the output from the adjacent DAC circuit 8.
  • FIG. 28 is a flowchart showing a first procedure of the operation check test according to the second embodiment.
  • the control circuit sets the test signal to the “H” level and the test B signal to the “L” level (S101). As a result, the operational amplifier 1 operates as a comparator (S102). Next, the control circuit sets the expected value of the odd-numbered determination circuit 3 (determination circuits 3-1, 3-3,..., 3- (n ⁇ 1)) to the “L” level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuit 3 (determination circuits 3-2, 3-4,..., 3-n) to the “H” level.
  • control circuit initializes a counter m included in the control circuit to 0 (S103). Further, the control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m through the data bus. In addition, the control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m + 1 through the data bus (S104).
  • the odd-numbered operational amplifier 1 has an odd-numbered DAC in which a gradation voltage of gradation 0 is connected in series to its positive polarity input terminal. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from its adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 becomes “L”.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent odd-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “H”.
  • the determination circuit 3 determines whether the level of the output signal from the operational amplifier 1 matches the expected value stored by itself (S105).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 (S106).
  • the above processing from S104 to S106 is repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S107, S108).
  • FIG. 29 is a flowchart showing a second procedure of the operation check test according to the second embodiment.
  • the operation check test 2 in the second embodiment is an operation check in which the voltage relationship of the odd-numbered and even-numbered gradations is reversed in the operation check test 1 in the second embodiment. This is the same as the operation check test in the embodiment.
  • control circuit sets the expected value of the odd-numbered determination circuit 3 to “H”, while setting the expected value of the even-numbered determination circuit 3 to “L”. Further, the control circuit initializes a counter m included in the control circuit to 0 (S111).
  • control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m + 1 via the data bus.
  • control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m via the data bus (S112).
  • the odd-numbered operational amplifier 1 is connected to the positive-polarity input terminal of the grayscale voltage of grayscale 1 in series with the odd-numbered DAC. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the output of the odd-numbered operational amplifier 1 becomes “H” level.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from the adjacent odd-numbered DAC circuit 8 to its negative polarity input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “L” level.
  • the determination circuit 3 compares the level of the output from the operational amplifier 1 with the expected value stored in itself (S113).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value.
  • the above processes of S112 to S114 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S115, S116).
  • FIG. 30 is a flowchart showing a third procedure of the operation check test according to the second embodiment.
  • the gradation voltage input to the operational amplifier 1 by the executed check test is used as the operational amplifier. 1 may continue to be held, and in the operation check tests 1 and 2 of the second embodiment, there may be a case where a failure cannot be detected.
  • the control circuit initializes the value of the counter m included therein to 0 (S121).
  • the pull-up / pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8.
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled down (S122).
  • the output of the even-numbered DAC circuit 8 is open, a low voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 31 is a flowchart showing a fourth procedure of the operation check test according to the second embodiment.
  • the control circuit initializes the value of the counter m included in the control circuit to 0 (S131).
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull down the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled up (S122).
  • the output of the even-numbered DAC circuit 8 is open, a high voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 32 is a flowchart showing a fifth procedure of the operation check test according to the second embodiment.
  • the DAC circuit 8 may have a problem that two adjacent gray scales in itself are short-circuited.
  • the purpose of the operation check test 5 of the second embodiment is to detect such a problem.
  • the control circuit initializes the value of the counter m included in itself to 0 (S141).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 through the data bus.
  • the odd-numbered DAC circuit 8 and the even-numbered DAC circuit 8 output the gradation voltage of the same gradation m (S142).
  • the control circuit short-circuits the positive input terminal and the negative input terminal of the operational amplifier 1 through a switch (not shown).
  • the determination circuit 3 stores the output level of the operational amplifier when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S143).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the positive polarity input terminal of the odd-numbered operational amplifier 1 is input with the grayscale voltage of grayscale m from the odd-numbered DAC circuit 8 connected in series to itself, Are supplied with the gradation voltage of gradation m from the even-numbered DAC circuit 8 adjacent thereto.
  • the gradation input of the gradation m from the even-numbered DAC circuit 8 connected in series to the positive-polarity input terminal of the even-numbered operational amplifier 1 is input to the negative-polarity input terminal.
  • the gradation voltage of gradation m from the adjacent odd-numbered DAC circuit 8 is input.
  • the determination circuit 3 compares the expected value stored by itself with the output from the operational amplifier 1 (S144). Further, the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value stored by itself. Further, the determination flag 4 stores therein the “H” flag input from the determination circuit 3.
  • control circuit switches the signal input to the positive input terminal of the operational amplifier 1 and the signal input to the negative input terminal from the DAC circuit 8 using a switch (not shown) (S146). Thereafter, the same processing as S147 is performed (S147). Similarly to S145, when the output from the operational amplifier 1 is different from the expected value stored in the operational amplifier 1, the determination circuit 3 outputs “H” to the determination flag 4 (S148).
  • FIG. 33 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuits 28A and 28B and performing self-repair.
  • the control circuit detects whether or not the determination flag 4 stores “H” (S151). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S153. On the other hand, when the control circuit detects the determination flag 4 storing “H”, the DAC circuit 8 corresponding to the determination flag 4 storing “H” is switched to the spare DAC circuit 28A or 28B.
  • the operation confirmation is performed with the two DAC circuits 8 as one set, even if the determination flag 4 stores the “H” flag, It cannot be determined whether the DAC circuit is defective.
  • the following description assumes that the DAC circuit 8-1 has a problem.
  • the determination circuits 3-1 and 3-2 output “H” to the determination flags 4-1 and 4-2 by the operation check tests 1 to 5. Will do. Further, the determination flags 4-1 and 4-2 output the “H” flag input from the determination circuits 3-1 and 3-2 to the switches 2c and 2d, thereby turning the switch 2c OFF and turning the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 signal, and the sampling circuit 26B inputs the STR2 signal.
  • the sampling circuit 26A acquires gradation data corresponding to the liquid crystal driving signal output terminal OUT1 from the data bus
  • the sampling circuit 26B acquires the gradation data corresponding to the liquid crystal driving signal output terminal OUT2.
  • Data is acquired from the data bus.
  • the switch 2c is turned OFF, the connection between the output of the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1 is cut off, and the output of the operational amplifier 1-2 and the liquid crystal driving signal output terminal OUT2 are disconnected. The connection is also cut off.
  • the switch 2d is turned on, the output of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2.
  • the defective DAC circuit 8 is switched to the spare DAC circuit 28A and 28B by taking the defective DAC circuit 8 and the DAC circuit 8 paired therewith as a set, thereby switching the defective DAC circuit 8 to the spare DAC circuit. It can be switched to 26A or 26B.
  • control circuit sets the test signal to “L” and the test B signal to “H”, and shifts to normal operation (S153).
  • the gradation voltage from the output circuit block 30 (see FIG. 2) and the gradation voltage from the standby output circuit block 40 (see FIG. 2) are switched.
  • the switching circuit 60 (see FIG. 2) is configured to be provided in the integrated circuits 10 and 20, the present invention is not limited to this, and the switching circuit 60 is configured to be provided on the display panel side. Also good.
  • the configuration and operation of the display unit 90 ′ including the switching circuit 60 on the display panel side will be described as a third embodiment according to the present invention.
  • a different part from Embodiment 1 is demonstrated and the description is abbreviate
  • FIG. 34 is a block diagram showing a schematic configuration of the display unit 90 ′.
  • the display unit 90 ' includes a display panel 80' and an integrated circuit 10 '(drive circuit) that drives the display panel 80' based on gradation data input from the outside.
  • the integrated circuit 10 ′ is different from the integrated circuit 10 of the first embodiment in that the switching circuit 60 is not provided, and the other configuration is the same as that of the integrated circuit 10.
  • the display panel 80 ′ is different from the display panel 80 of the first embodiment in that it includes a switching circuit 60, and other configurations are the same as the display panel 80.
  • FIG. 35 is a block diagram showing a configuration of the integrated circuit 10 ′.
  • the integrated circuit 10 ′ receives n grayscale data corresponding to each of the n output terminals OUT1 to OUTn via a data bus from a grayscale data input terminal (not shown).
  • the integrated circuit 10 ′ includes a plurality of switches 2a that are turned ON / OFF by a test signal, a plurality of switches 2b that are turned ON / OFF by a test B signal, and an ON, OFF by an LF signal. And a plurality of switches 2f for switching OFF.
  • the switches 2a, 2b, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • each of the integrated circuit 10 'spare sampling circuit 26, spare hold circuit 27, spare DAC circuit 28, spare operational amplifier 21, and spare output terminal OUT0 is provided.
  • the display panel 80 ′ includes a connection terminal (not shown) connected to each of the output terminals OUT1 to OUTn included in the integrated circuit 10 ′ and determination flags 9-1 to 9-n ( Hereinafter, when collectively referred to as a determination flag 9), a switch 2 f that is switched ON / OFF by an LF signal from a control circuit (not shown), and an ON / OFF by an LFB signal that is an inverted signal of the LF signal. Switch 2e, and switches 2c and 2d that are turned on and off by Flag1 to Flagn that are output signals from the determination flag 9.
  • the switches 2d, 2e, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned on when an “L” signal is input, and is turned off when an “H” signal is input.
  • the display panel 80 ′ in the present embodiment is a liquid crystal display panel, and, as shown in FIG. 35, the data signal line SL ⁇ is connected to each of the output terminals OUT of the integrated circuit 10 ′ via the switches 2e and 2c. 1 to SL-n (hereinafter collectively referred to as data signal lines SL) are connected. Further, the same number of pixels P as the number of scanning signal lines GL are connected to each of the data signal lines SL. In FIG. 35, the pixel P connected to the data signal line SL-1 is a pixel P-1, and the pixel P connected to the data signal line SL-n is a pixel Pn.
  • the test signal is “H” and the test B signal is “L”. Therefore, the connection between the operational amplifier 1 and the output terminal OUT is disconnected by the switch 2b.
  • the control circuit outputs an “H” LF signal and also outputs an “L” LFB signal.
  • the switch 2 f is turned on, and each determination flag 4 is connected to each determination flag 9 via each output terminal OUT. Further, each of the determination flags 4 outputs the “H” flag or “L” flag stored therein as Flag1 to Flagn to each determination flag 9 via each output terminal OUT.
  • Each determination flag 9 stores Flag1 to Flagn output from the determination flag 4 in its own internal memory and outputs it to the switches 2c and 2d connected to itself.
  • Each switch 2e is turned OFF when the LFB signal becomes “L” during the period when the LF signal is “H”. This prevents Flag1 to Flagn output from the determination flag 4 from being output to the data signal lines SL-1 to SL-n. As a result, Flag1 to Flagn output from the determination flag 4 affects the pixel P. Will not affect.
  • the determination flag 4-1 corresponding to the output terminal OUT1 stores the “H” flag, in other words, when the DAC circuit 8-1 is defective, the determination flag 9-1 is determined by the determination flag 4 The “H” flag is then output, and the output “H” flag is recorded in the internal memory of the device. In this example, it is assumed that the determination flags 4-2 to 4-n record the “L” flag.
  • the determination flag 9-1 outputs Flag1 of the “H” flag to the switches 2c and 2d connected to the determination flag 9-1.
  • the switch 2c connected to the determination flag 9-1 disconnects the output terminal OUT1 from the data signal line SL-1, and the switch 2d connected to the determination flag 9-1
  • the terminal OUT0 and the data signal line SL-1 are connected.
  • each of the determination flags 9-2 to 9-n is connected to the determination flags 9-2 to 9-n in order to output the Flag 2 to Flagn of the “L” flag to the switches 2c and 2d connected thereto.
  • the switch 2c is turned on, and the switch 2d connected to the determination flags 9-2 to 9-n is turned off.
  • each of the data signal lines SL-2 to SL-n is connected to each of the output terminals OUT2 to OUTn via the switch 2e.
  • each determination flag 9 switches the switches 2c and 2d connected to itself based on Flag1 to Flagn from the determination flag 4, the control circuit outputs an “L” LF signal and outputs “H”. LFB signal is output. As a result, each of the output terminals OUT2 to OUTn is connected to each of the data signal lines SL-2 to SL-n.
  • the data signal line SL-1 is connected to the output terminal OUT0.
  • the data signal lines SL-2 to SL-n are connected to the operational amplifiers 1-2 to 1-n via the output terminals OUT2 to OUTn. Since the switch 2d connected to the sampling circuit 6-1 is turned on by Flag1 from the determination flag 4-1, the grayscale data (corresponding to the data signal line SL-1) input to the sampling circuit 6-1. Gradation data to be input) is also input to the sampling circuit 26.
  • gradation data corresponding to the data signal line SL-1 is input to the data signal line SL-1 from the output terminal OUT0 instead of the output terminal OUT1.
  • switching of the gradation data input to each of the sampling circuit 6 and the spare sampling circuit 26 is the same as the operation in the first embodiment, and thus detailed description thereof is omitted here.
  • the display unit 90 ′ performs a self-repair operation, so that the normal grayscale voltage is applied to the data signal line SL using the spare DAC circuit 28 instead of the DAC circuit 8 detected as defective. Can be output. Similar to the first embodiment, this embodiment also includes a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 36 is a flowchart showing a processing procedure from when the display unit 90 ′ is turned on to when an operation check test is performed and the normal operation is started.
  • the display unit 90 ′ initializes the integrated circuit 10, thereby setting all the flags stored in the determination flag 4 to the “L” flag. (S161).
  • the control circuit sets the test signal to “H”, the test B signal to “L”, and switches the integrated circuit 10 ′ to the operation check test state (S 162).
  • the control circuit and the integrated circuit 10 perform the above-described operation check test (S163). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed (S164).
  • the display unit 90 ′ in the present embodiment is configured to include the determination flag 4 and the determination flag 9 as a circuit for storing a flag that is a determination result in the determination circuit 3-1, but the display unit 90 ′ is a modified example.
  • the determination flag 9, the switch 2f, and the switch 2e may not be provided, and the determination flag 4 may control the switches 2c and 2d.
  • the LF signal and the LFB signal for controlling the switches 2f and 2e are also unnecessary, while the determination flag 4 and wiring and connection terminals for connecting the switches 2c and 2d are required.
  • the integrated circuit and the display panel are connected via the output terminal OUT.
  • the integrated circuit and the display panel are not connected via the output terminal OUT.
  • An integrated display device is also included in the scope of the present invention.
  • a display unit 90 ′′ in which an integrated circuit and a display panel are integrated will be described as a fourth embodiment with reference to FIG. 37.
  • the display unit 90 ′′ according to the present embodiment is described in the embodiment. 1 is a modification of the display unit 90 according to the first embodiment. In the present embodiment, portions different from those of the first embodiment will be described, and descriptions of overlapping portions will be omitted.
  • FIG. 37 is a block diagram showing the configuration of the display unit 90 ′′.
  • the display unit 90 ′′ has no distinction between the integrated circuit 10 and the display panel 80 shown in the first embodiment, and the outputs of the operational amplifiers 1 and 21 are connected via the switches 2b, 2c, and 2d.
  • the display unit 90 ′′ of the present embodiment is different from the display unit 90 of the first embodiment in whether or not the output terminal OUT is provided.
  • Other configurations are the same as those of the display unit 90 of the first embodiment.
  • FIG. 38 is a block diagram showing the configuration of the television system 300.
  • the television system 300 is described as including the display unit 90 according to the first embodiment.
  • the television system according to the present invention is not limited to this, and instead of the display unit 90, The display device according to Embodiments 2 to 4 may be provided.
  • a television system 300 includes an antenna 301 that receives a broadcast wave, a tuner unit 302 that demodulates the received broadcast wave into a video / audio signal, and the demodulated video / audio signal as a video signal and an audio.
  • a signal separation unit 303 that separates the signal into a signal
  • a video signal processing unit 304 that decodes the separated video signal into a digital video signal, and obtains the decoded digital video signal as gradation data.
  • a display unit 90 that displays video on the display panel 80 (see FIG. 2), an audio signal processing unit 305 that decodes the separated audio signal into a digital audio signal, and the decoded digital audio signal as an analog signal.
  • An audio signal output unit 306 is provided that outputs the converted analog audio signal as audio from a speaker after conversion into the audio signal.
  • the antenna 301 receives a broadcast wave from a broadcast station, and outputs the received broadcast wave to the tuner unit 302.
  • the tuner unit 302 demodulates the output broadcast wave into a video / audio signal, and outputs it to the signal separation unit 303.
  • the signal separation unit 303 separates the output video / audio signal into a video signal and an audio signal, and outputs them to the video signal processing unit 304 and the audio signal processing unit 305, respectively.
  • the video signal processing unit 304 decodes the output video signal into a digital video signal, and outputs the decoded digital video signal to the display unit 90 as gradation data.
  • the display unit 90 displays the output gradation data using the display panel 80 provided therein.
  • the audio signal processing unit 305 decodes the audio signal separated by the signal separation unit 303 into a digital audio signal and outputs it to the audio output unit 306.
  • the audio signal output unit 306 converts the output digital audio signal into an analog audio signal, and then outputs the analog audio signal as audio using a speaker provided therein.
  • the television system 300 is configured to acquire from a broadcasting station using the antenna 301 and the tuner unit 302 as means for acquiring a video / audio signal, but the present invention is not limited to this.
  • the content data recorded on the recording medium may be read from the recording medium, and may be acquired via a PC (personal computer) from a content reading device such as a DVD player or the Internet.
  • the operation check test and the self-repair processing operation described in the first and fourth embodiments are performed immediately after power is supplied to the liquid crystal driving semiconductor integrated circuit 10, but the present invention is not limited to this. Instead, it may be configured by inputting a control signal to the liquid crystal driving semiconductor integrated circuit 10 and may be performed at an arbitrary timing. For example, a signal indicating a display blanking period may be input to the liquid crystal driving semiconductor integrated circuit 10 from the controller of the display device, and an operation check test and self-repair may be performed at this timing.
  • the liquid crystal driving semiconductor integrated circuit 10 is configured to detect a malfunction of the liquid crystal driving semiconductor integrated circuit 10, and the liquid crystal driving semiconductor integrated circuit 10 has an abnormality. Sometimes you can go. For example, the current of the signal output from the liquid crystal driving semiconductor integrated circuit 10 may be detected, and when the detected current exceeds the set current, an operation check test and a self-repair processing operation may be performed.
  • the operation check test and the self-repair processing operation may be performed periodically. For example, it may be performed every vertical blanking period in which no display is performed, or may be performed every preset total display time.
  • the operation check test and the self-repair processing operation may be performed during a part of the display period. For example, since a pixel stores a display voltage in a liquid crystal display device, there is no problem in display even if the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance after charging of the display voltage is completed. During a part of the display period, the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance, and an operation check test and a self-repair processing operation are performed.
  • one pattern is determined in a part of the display period of one line, and it is performed in a display period of one screen or a period of displaying several screens. You can also.
  • the integrated circuit 10 (see FIG. 18) according to the present invention needs to stop the output signal for driving the display panel 80 (see FIG. 2) in order to self-detect its own defect (operation check test). There is. That is, the integrated circuit 10 cannot drive the display panel 80 during the self-detection period. Therefore, the timing at which the integrated circuit 10 performs self-detection needs to be performed in a period that does not affect the display of video on the display device.
  • the case where the integrated circuit 10 performs self-detection and self-repair is described as the period during which the integrated circuit 10 performs self-detection during the startup process when the display device is turned on. This is because the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device because the display device does not display video during the startup process of the display device. Because.
  • the integrated circuit 10 in the present embodiment performs self-detection to detect its own defect during the startup process when the display device is turned on.
  • the present invention is not limited to this.
  • Self-detection and self-repair can be performed in a period other than during the startup process of the display device.
  • Example 1 (Self-detection and self-repair in the vertical blanking period)
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device. Become. The reason will be described below.
  • FIG. 39 (a) to 39 (f) are time chart diagrams showing timings of signals input to the liquid crystal display device.
  • FIG. 39A shows the scanning signal line SCN1 that is output from the scanning side driving circuit that drives the scanning line of the display device and is given to the first scanning signal line of the display device
  • FIG. FIG. 6 shows a scanning signal line SCN2 output from the scanning side drive circuit and applied to the second scanning signal line of the display device
  • FIG. 8C shows the video signal inversion circuit from the integrated circuit 10 (see FIG. 18).
  • a video signal DSj corresponding to the j-th data signal line of the display device is shown
  • FIG. 6D shows the j-th data signal line of the display device supplied from the video signal inversion circuit to the data side driving circuit.
  • (E) shows the video signal DATAj applied to the jth data signal line of the display device, and (f) shows the first scanning signal line in the display device.
  • jth data signal It shows a driving voltage VD1j applied to pixels connected to and. 39
  • a period TV from time t1 to t5 is a vertical scanning period of the display device
  • a period TV1 is a vertical blanking period
  • a period TH from time t1 to t3 is a horizontal scanning period
  • a period TH1 from t2 to t3 is a horizontal blanking period.
  • the video signal inversion circuit inverts the polarity of the video signal DSj from the integrated circuit 10 in order to invert the polarity of the display electrode in each pixel of the display device every horizontal scanning period TH and vertical scanning period TV. Circuit.
  • the scanning side driving circuit sequentially delays the timing by the horizontal scanning TH from the first scanning signal line for each scanning signal line of the display device. , Scan signal SCN1, scan signal SCN2,..., Scan signal SCNm. Further, the scanning side driving circuit repeatedly outputs each scanning signal SCN1 to scanning signal SCNm to each scanning signal line of the display device every vertical scanning period TV. Note that here, the display device has m scanning signal lines.
  • the video signal DSj from the integrated circuit 10 is input to the video signal inversion circuit.
  • the video signal inverting circuit inverts the polarity of the video signal DSj every horizontal scanning period TH and also the polarity every vertical scanning period TV, and outputs the video signal DRVj shown in FIG. Generate.
  • the video signal inversion circuit inputs the generated video signal DRVj to the data side driving circuit.
  • the data side driving circuit samples the video signal DRVj from the video signal inverting circuit every horizontal scanning period TH, delays the sampled signal value by one horizontal scanning period TH, and (e) of FIG. Is output to the jth data signal line of the display device.
  • the scanning signal SCN1 in the horizontal scanning period TH from time t1 to t2 is used.
  • the TFT in the pixel 1j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t1 to t2 is applied to the display electrode in the pixel 1j via the jth data signal line as the drive voltage VD1j. Is done.
  • the drive voltage VD1j applied to the display electrode of the pixel 1j continues to hold the voltage level during the time t1 to t2 even when the TFT in the pixel 1j is cut off during the time t2 to t5.
  • the scanning signal SCN2 in the horizontal scanning period TH from time t3 to t4.
  • the TFT in the pixel 2j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t3 to t4 is applied to the display electrode in the pixel 2j via the jth data signal line as a drive voltage.
  • the drive voltage applied to the display electrode of the pixel 2j continues to hold the voltage level between times t3 and t4 even when the TFT in the pixel 2j is turned off.
  • the scanning-side driving circuit does not output the scanning signals SCN1 to SCNm for conducting the TFTs of the respective pixels to the scanning signal line, in other words, the period in which the conduction of the TFTs of the respective pixels is cut off.
  • the display device does not need to apply a voltage to the display electrode of each pixel. That is, it is not necessary for the integrated circuit 10 to output the video signal DSj that is the basis of the drive voltage, and even if the integrated circuit 10 and the display device are electrically disconnected, the display of the video on the display device is affected. There is no.
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device.
  • the integrated circuit 10 performs a self-detection process for detecting a defect in an output circuit block included in the integrated circuit 10 for each output circuit block corresponding to each data signal line and for all the output circuit blocks. It is targeted. Therefore, this self-detection process takes time.
  • the integrated circuit 10 does not need to perform self-detection processing when there is no possibility of malfunction in each output circuit block included in the integrated circuit 10. In other words, the integrated circuit 10 only needs to perform self-detection processing only when there is a possibility of malfunction in each output circuit block.
  • the integrated circuit 10 includes an operation determination circuit that determines whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10, and there is an operation failure somewhere in the integrated circuit 10 by the operation determination circuit. If the self-detection process is performed only when it is determined, it is possible to prevent performing a useless self-detection process.
  • the power supply current supplied to the integrated circuit 10 is compared with that during normal operation, in other words, compared with the initial stage that is determined to be good when shipped as a product. Become more. Therefore, when the value of the power supply current supplied to the integrated circuit 10 becomes larger than a certain value compared with the normal operation, an operation failure has occurred in the integrated circuit 10. Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 10 and determines whether an operation failure has occurred in the integrated circuit 10 from the detected value of the power supply current.
  • FIG. 40 is a block diagram showing a configuration of the operation determination circuit 200.
  • the operation determination circuit 200 includes a resistor 202 (detection means) and a switch 203 between the VA 201 that supplies power to the integrated circuit 10 and the integrated circuit 10.
  • the resistor 202 and the switch 203 are connected so as to be parallel to each other.
  • the operation determination circuit 200 includes an A / D converter 204 (detection means) connected to one end of the resistor 202 and the switch 203 on the integrated circuit 10 side, and a switch for inputting an output signal from the A / D converter 204.
  • a comparison circuit 208 (current value comparison means, drive circuit determination means) that compares the output value with the output value from the data latch circuit 207 is provided. Note that the output terminal of the comparison circuit 208 connects the comparison result in the comparison circuit 208 to a control circuit included in the integrated circuit 10. Note that switching of the switches 203 and 205 is controlled by a control circuit included in the integrated circuit 10.
  • the operation determination circuit 200 previously stores a value corresponding to the power supply current value during normal operation of the integrated circuit 10 in the EEPROM 206 as reference data.
  • the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit 10.
  • the value of the reference data stored in the EEPROM 206 is compared, and if the detected value is equal to or greater than a certain value, it is determined that an operation failure has occurred in the integrated circuit 10.
  • the operation determination circuit 200 outputs a signal indicating that an operation failure has occurred in the integrated circuit 10 to the control circuit included in the integrated circuit 10, so that the control circuit detects the self-detection of the integrated circuit 10. Start processing and self-healing process.
  • FIG. 41 is a flowchart showing an operation process in which the operation determination circuit 200 stores the reference data in the EEPROM 206.
  • the control circuit in generating the reference data, the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S301).
  • the resistance value of the resistor 202 is a resistance value such that the voltage drop of the resistor 202 during the normal operation of the integrated circuit 10 is about 0.1V. Note that the resistance value of the resistor 202 is preferably determined in consideration of current consumption of the integrated circuit.
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S302).
  • the A / D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205.
  • the EEPROM 206 stores the input digital value from the A / D converter as basic data (S303). Note that the switch 205 in S303 is switched by the control circuit so as to connect the A / D converter 204 and the EEPROM 206.
  • the control circuit short-circuits the switch 203 and returns the integrated circuit 10 to the normal operation state (S304).
  • the generation and storage processing of the reference data from S301 to S304 is performed at the product shipment stage of the display device including the integrated circuit 10, in other words, at the stage where the integrated circuit 10 is determined to be normal by various shipment inspections. Is called.
  • FIG. 42 is a flowchart showing a process of detecting an operation failure of the integrated circuit 10 in the operation determination circuit 200.
  • the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S305).
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S306).
  • the A / D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205.
  • the data latch circuit 207 stores the input digital value from the A / D converter as detection data (S307). Note that the switch 205 in S306 is switched by the control circuit so as to connect the A / D converter 204 and the data latch circuit 207.
  • the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data stored in the data latch circuit 207, and compares the value of the read reference data with the value of the detection data (S308). Further, the comparison circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is equal to or greater than a predetermined value (for example, 3 or more as a digital value) (S309).
  • a predetermined value for example, 3 or more as a digital value
  • the control circuit 208 when the control circuit 208 receives a signal indicating that a malfunction has occurred in the integrated circuit 10 from the comparison circuit 208, the control circuit starts self-detection of the integrated circuit 10 (S311). Further, in the self-detection of the integrated circuit 10, when the integrated circuit 10 detects a failure in its own output circuit block, the integrated circuit 10 switches between the output of the defective output circuit block and the output of the spare output circuit block, Perform self-healing. Note that if the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 10 in S311, it is considered that the power supply current value varies due to other factors.
  • the operation determination circuit 200 since the power supply current value fluctuates, the operation determination circuit 200 generates and stores the reference data shown in S301 to S304, and the power supply current value that has fluctuated is newly set.
  • the reference data is stored in the EEPROM 206 (S312). Further, after S312, the control circuit short-circuits the switch 203 to place the operation determination circuit 200 and the integrated circuit 10 in a normal operation state (S310).
  • the comparison circuit 208 detects in S309 that the difference between the reference data value and the detected data value is less than a predetermined value (for example, less than 3 as a digital value), the process proceeds to S310. Transition.
  • a predetermined value for example, less than 3 as a digital value
  • Example 2 (Periodic self-detection of the integrated circuit 10) Further, self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed periodically. Specifically, the self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed for each vertical blanking period of the display device described in the first embodiment. In this case, the vertical synchronization signal is counted and is displayed every certain number of times.
  • the counter can be configured by a non-volatile memory and the counter can count the number of vertical synchronization signals.
  • the integrated circuit 10 may be provided with a timer for measuring time, the operation time is counted by this timer, and the integrated circuit 10 is self-detected and self-repaired every preset accumulated operation time.
  • the self-detection (operation check test) and self-repair processing operation of the integrated circuit 10 may be performed during a part of a period during which the display device displays an image. For example, since each pixel of the display device stores the voltage of the display electrode, after charging of the voltage of the display electrode is finished, the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, There is no problem with the video display.
  • the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, and self-detection (operation check test) and self-repair processing operations are performed.
  • a method for setting the output terminals OUT1 to OUTn to high impedance by providing a switch in series for each signal transmission path connecting the output terminals OUT1 to OUTn and the display device, and opening the switch, The output terminals OUT1 to OUTn and the display device have high impedance, in other words, can be electrically disconnected.
  • the integrated circuit 10 in the first embodiment has been described.
  • the present invention is not limited to this, and the integrated circuits 10 ′, 20 and in the second and third embodiments, and The present invention can also be applied to the display unit 90 ′′ in the fourth embodiment.
  • the liquid crystal display device that displays an image on the liquid crystal display panel has been described.
  • the present invention is not limited to this, and a display device other than the liquid crystal display device, such as a plasma television or the like. It can also be applied to.
  • the display device driving integrated circuit and the display device of the present invention may be configured as follows.
  • a driving circuit for driving a display panel A drive circuit comprising self-repair means for self-repairing the drive circuit that has become defective.
  • the self-healing means is Determining means for determining whether or not the output circuit is defective;
  • the self-healing means is When the determination result of the determination means is defective, a switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal to the display panel is provided.
  • the drive circuit according to the second configuration characterized in that:
  • the determination means is Comparing means for comparing the output signal from the output circuit and the output signal from the preliminary output circuit, The drive circuit according to the third configuration, wherein it is determined whether or not the output circuit is defective based on a comparison result of the comparison means.
  • a display device comprising the drive circuit according to any one of the first to fourth configurations and the display panel.
  • a display panel A drive circuit including an output circuit for outputting an output signal for driving the display panel, and a display device comprising: The drive circuit is Determination means for determining whether or not the output circuit is defective, and a spare output circuit capable of outputting the output signal to the display panel; The display panel Switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel when the determination result from the determination means is defective. And a display device.
  • a display panel An output circuit for outputting an output signal for driving the display panel;
  • a preliminary output circuit capable of outputting the output signal to the display panel;
  • Determining means for determining whether or not the output circuit is defective; When the determination result of the determination means is defective, as an output signal for driving the display panel, switching means for switching the output signal from the defective output circuit to the output signal from the standby output circuit;
  • a display device comprising:
  • a television system comprising the display device according to any one of claims 5 to 7.
  • the output circuit block and the spare output circuit block further include an output buffer using an operational amplifier, and when the operational amplifier is used as the comparison unit and the determination result is bad, the output circuit block replaces the output circuit block.
  • the output circuit block and the spare output circuit block further include an output buffer using an operational amplifier and a circuit for storing a signal applied to an input of the output circuit, the operational amplifier is used as the comparing means, and the determination result is The drive circuit according to the ninth configuration, wherein, when defective, the spare output circuit block is connected instead of the output circuit block.
  • Control means for controlling input signals to be input to the output circuit and the standby output circuit includes While inputting input signals of different magnitudes to the output circuit and the standby output circuit, Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
  • the determination unit according to any one of the ninth configuration to the twelfth configuration, wherein the output circuit is determined to be defective when the comparison result is different from the expected value.
  • Flag storage means for storing a flag indicating the determination result of the determination means;
  • the connection switching means connects the spare output circuit to the output terminal instead of the output circuit when the value of the flag indicates that the output circuit is defective.
  • the drive circuit according to any one of the configurations from the configuration to the thirteenth configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit, After the connection switching means connects the output terminal and the output of the auxiliary output circuit, the auxiliary output circuit outputs an output signal to the output terminal.
  • the drive circuit according to any one of the configurations.
  • Detection means for detecting the value of the power supply current supplied to the drive circuit; Normal current value storage means for storing in advance the value of the power supply current during normal operation of the drive circuit; Current value comparison means for comparing the value of the power supply current from the detection means with the value of the power supply current from the normal current value storage means; Drive circuit determination means for determining whether or not the drive circuit is defective based on a comparison result of the current value comparison means; When the determination result of the drive circuit determination means is bad, The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to the configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to the configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to the configuration.
  • a blocking means for blocking a signal transmission path from the output terminal to the display panel After the blocking means blocks the signal transmission path from the output terminal to the display panel,
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the present invention provides a display device including a display drive integrated circuit that includes specific means for detecting a defect in the output circuit and self-repairing, and that can more easily cope with the malfunction of the output circuit. It is suitable for a liquid crystal display device that can perform self-detection and self-repair at an appropriate timing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

Un téléviseur à cristaux liquides (400) possède une unité afficheur (90), qui comprend un panneau d'affichage (80); un circuit d'attaque source (10a) qui attaque le panneau d'affichage (80) et qui comprend un circuit de comparaison/détermination (50) destiné à détecter une panne, et un circuit de commutation (60) destiné à effectuer une réparation de panne; et une mémoire (80) qui stocke un drapeau de détermination indiquant un résultat de détermination du circuit de comparaison/détermination (50). La mémoire (80) est extérieure au dispositif d'attaque source (10a).
PCT/JP2009/066654 2008-09-25 2009-09-25 Dispositif afficheur et système de télévision WO2010035785A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-246726 2008-09-25
JP2008246726A JP2010078869A (ja) 2008-09-25 2008-09-25 表示装置、およびテレビジョンシステム

Publications (1)

Publication Number Publication Date
WO2010035785A1 true WO2010035785A1 (fr) 2010-04-01

Family

ID=42059783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/066654 WO2010035785A1 (fr) 2008-09-25 2009-09-25 Dispositif afficheur et système de télévision

Country Status (3)

Country Link
JP (1) JP2010078869A (fr)
TW (1) TW201028992A (fr)
WO (1) WO2010035785A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854493B2 (en) 2019-11-27 2023-12-26 Boe Technology Group Co., Ltd. Display substrate and display device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4277055B2 (ja) 2007-05-29 2009-06-10 シャープ株式会社 駆動回路、表示装置、およびテレビジョンシステム
US8587573B2 (en) 2008-02-28 2013-11-19 Sharp Kabushiki Kaisha Drive circuit and display device
JP2012075046A (ja) * 2010-09-29 2012-04-12 Toshiba Corp 映像記録装置、映像記録方法、映像表示装置
JP6706954B2 (ja) 2016-04-01 2020-06-10 三菱電機株式会社 ドライバｉｃおよび液晶表示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225996A (ja) * 1988-03-07 1989-09-08 Hitachi Ltd 液晶表示装置
JPH06208346A (ja) * 1992-09-18 1994-07-26 Philips Electron Nv 能動マトリックスデバイス用電子式駆動回路
JPH06324651A (ja) * 1992-10-19 1994-11-25 Fujitsu Ltd 液晶表示装置の駆動回路
JPH0876723A (ja) * 1994-09-06 1996-03-22 Semiconductor Energy Lab Co Ltd アクティブマトリクス型表示装置の駆動回路およびその動作方法
JPH08185144A (ja) * 1994-12-28 1996-07-16 Sharp Corp 液晶表示装置
JP2009008891A (ja) * 2007-06-28 2009-01-15 Semiconductor Energy Lab Co Ltd 表示装置及び電子機器
JP2009104106A (ja) * 2007-05-29 2009-05-14 Sharp Corp 駆動回路、表示装置、およびテレビジョンシステム

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225996A (ja) * 1988-03-07 1989-09-08 Hitachi Ltd 液晶表示装置
JPH06208346A (ja) * 1992-09-18 1994-07-26 Philips Electron Nv 能動マトリックスデバイス用電子式駆動回路
JPH06324651A (ja) * 1992-10-19 1994-11-25 Fujitsu Ltd 液晶表示装置の駆動回路
JPH0876723A (ja) * 1994-09-06 1996-03-22 Semiconductor Energy Lab Co Ltd アクティブマトリクス型表示装置の駆動回路およびその動作方法
JPH08185144A (ja) * 1994-12-28 1996-07-16 Sharp Corp 液晶表示装置
JP2009104106A (ja) * 2007-05-29 2009-05-14 Sharp Corp 駆動回路、表示装置、およびテレビジョンシステム
JP2009008891A (ja) * 2007-06-28 2009-01-15 Semiconductor Energy Lab Co Ltd 表示装置及び電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854493B2 (en) 2019-11-27 2023-12-26 Boe Technology Group Co., Ltd. Display substrate and display device

Also Published As

Publication number Publication date
TW201028992A (en) 2010-08-01
JP2010078869A (ja) 2010-04-08

Similar Documents

Publication Publication Date Title
JP4277055B2 (ja) 駆動回路、表示装置、およびテレビジョンシステム
WO2010035797A1 (fr) Dispositif afficheur et système de télévision
US6191770B1 (en) Apparatus and method for testing driving circuit in liquid crystal display
JP6653593B2 (ja) 表示装置及び表示装置の検査方法
WO2010035785A1 (fr) Dispositif afficheur et système de télévision
WO2010035792A1 (fr) Dispositif afficheur et système de télévision
US8520076B2 (en) Liquid crystal display and method of testing the same
WO2010061839A1 (fr) Circuit de commande, dispositif d'affichage et procédé d'auto-détection et d'auto-réparation d'un circuit de commande
JP2006047315A (ja) Ｌｃｄ駆動用ｉｃ内のデジタル／アナログ変換器のテスト装置
WO2010058836A1 (fr) Dispositif d’affichage et système de télévision
WO2010035801A1 (fr) Dispositif afficheur et système de télévision
US20080180588A1 (en) Driver and driving method, and display device
US20090243981A1 (en) Driving module of display device and method for extending lifetime of the driving module
JP4494001B2 (ja) 表示装置の検査方法
JP5015037B2 (ja) 駆動回路および該駆動回路を備えた表示装置
JP5015038B2 (ja) 駆動回路および該駆動回路を備えた表示装置
JP5015041B2 (ja) 駆動回路および駆動回路を備えた表示装置
JPH0850796A (ja) シフトレジスタおよび表示装置
JP3230393B2 (ja) 液晶パネルの検査方法
JP2006235165A (ja) 電気光学装置用基板、電気光学装置及び電子機器
JP2006235164A (ja) 電気光学装置用基板、電気光学装置及び電子機器
JPH11326422A (ja) 表示装置用駆動回路
JP2006235160A (ja) 電気光学装置用基板、電気光学装置及び電子機器
JP2006234998A (ja) 電気光学装置用基板、電気光学装置及び電子機器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09816200

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09816200

Country of ref document: EP

Kind code of ref document: A1