WO2010003928A3 - Procédé de dopage de structures semi-conductrices et dispositif semi-conducteur associé - Google Patents

Procédé de dopage de structures semi-conductrices et dispositif semi-conducteur associé Download PDF

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Publication number
WO2010003928A3
WO2010003928A3 PCT/EP2009/058529 EP2009058529W WO2010003928A3 WO 2010003928 A3 WO2010003928 A3 WO 2010003928A3 EP 2009058529 W EP2009058529 W EP 2009058529W WO 2010003928 A3 WO2010003928 A3 WO 2010003928A3
Authority
WO
WIPO (PCT)
Prior art keywords
species
semiconductor layer
strained semiconductor
layer
doping
Prior art date
Application number
PCT/EP2009/058529
Other languages
English (en)
Other versions
WO2010003928A2 (fr
Inventor
Roger Loo
Frederik Leys
Matty Caymax
Original Assignee
Interuniversitair Microelektronica Centrum Vzw (Imec)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum Vzw (Imec) filed Critical Interuniversitair Microelektronica Centrum Vzw (Imec)
Priority to US13/002,749 priority Critical patent/US8507337B2/en
Priority to JP2011517120A priority patent/JP2011527124A/ja
Priority to EP09780201.1A priority patent/EP2311072B1/fr
Publication of WO2010003928A2 publication Critical patent/WO2010003928A2/fr
Publication of WO2010003928A3 publication Critical patent/WO2010003928A3/fr
Priority to US13/938,750 priority patent/US8962369B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

La présente invention se rapporte à un procédé d’introduction d’espèces dans une couche semi-conductrice contrainte comprenant les étapes consistant à : l’utilisation d’un substrat comprenant une première région comprenant une couche semi-conductrice contrainte exposée, charger le substrat dans une chambre de réaction, puis former une couche d’enrobage contenant des premières espèces par dépôt en phase vapeur (VPD) au moins sur la couche semi-conductrice contrainte exposée, et effectuer ensuite un traitement thermique, ce qui permet de diffuser au moins une partie des premières espèces provenant de la couche contenant des premières espèces dans la couche semi-conductrice contrainte et d’activer au moins une partie des premières espèces diffusées dans la couche semi-conductrice contrainte.
PCT/EP2009/058529 2008-07-06 2009-07-06 Procédé de dopage de structures semi-conductrices et dispositif semi-conducteur associé WO2010003928A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US13/002,749 US8507337B2 (en) 2008-07-06 2009-07-06 Method for doping semiconductor structures and the semiconductor device thereof
JP2011517120A JP2011527124A (ja) 2008-07-06 2009-07-06 半導体構造のドープ方法およびその半導体デバイス
EP09780201.1A EP2311072B1 (fr) 2008-07-06 2009-07-06 Procédé de dopage de structures semi-conductrices
US13/938,750 US8962369B2 (en) 2008-07-06 2013-07-10 Method for doping semiconductor structures and the semiconductor device thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7840308P 2008-07-06 2008-07-06
US61/078,403 2008-07-06

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/002,749 A-371-Of-International US8507337B2 (en) 2008-07-06 2009-07-06 Method for doping semiconductor structures and the semiconductor device thereof
US13/938,750 Division US8962369B2 (en) 2008-07-06 2013-07-10 Method for doping semiconductor structures and the semiconductor device thereof

Publications (2)

Publication Number Publication Date
WO2010003928A2 WO2010003928A2 (fr) 2010-01-14
WO2010003928A3 true WO2010003928A3 (fr) 2010-05-06

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Family Applications (1)

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PCT/EP2009/058529 WO2010003928A2 (fr) 2008-07-06 2009-07-06 Procédé de dopage de structures semi-conductrices et dispositif semi-conducteur associé

Country Status (4)

Country Link
US (2) US8507337B2 (fr)
EP (1) EP2311072B1 (fr)
JP (2) JP2011527124A (fr)
WO (1) WO2010003928A2 (fr)

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US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US9048261B2 (en) * 2011-08-04 2015-06-02 International Business Machines Corporation Fabrication of field-effect transistors with atomic layer doping
US9006069B2 (en) * 2011-12-19 2015-04-14 Intel Corporation Pulsed laser anneal process for transistors with partial melt of a raised source-drain
KR101894221B1 (ko) 2012-03-21 2018-10-04 삼성전자주식회사 전계 효과 트랜지스터 및 이를 포함하는 반도체 장치
EP2717316B1 (fr) * 2012-10-05 2019-08-14 IMEC vzw Procédé de production de structures à ailettes contraintes de germanium
US9059044B2 (en) 2012-11-15 2015-06-16 International Business Machines Corporation On-chip diode with fully depleted semiconductor devices
US9105559B2 (en) * 2013-09-16 2015-08-11 International Business Machines Corporation Conformal doping for FinFET devices
US9530776B2 (en) * 2014-01-17 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET semiconductor device with germanium diffusion over silicon fins
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US9390976B2 (en) 2014-05-01 2016-07-12 International Business Machines Corporation Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
US9443770B2 (en) 2014-05-20 2016-09-13 International Business Machines Corporation Patterning process for fin implantation
US20150372099A1 (en) * 2014-06-19 2015-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide formation using a spike annealing process
US9318318B1 (en) 2015-01-05 2016-04-19 International Business Machines Corporation 3D atomic layer gate or junction extender
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Also Published As

Publication number Publication date
JP2011527124A (ja) 2011-10-20
US20140008727A1 (en) 2014-01-09
WO2010003928A2 (fr) 2010-01-14
JP2016139806A (ja) 2016-08-04
US8962369B2 (en) 2015-02-24
US20110169049A1 (en) 2011-07-14
JP6405325B2 (ja) 2018-10-17
US8507337B2 (en) 2013-08-13
EP2311072B1 (fr) 2013-09-04
EP2311072A2 (fr) 2011-04-20

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