WO2009152770A1 - 一种第二次交织及解交织的方法和装置 - Google Patents

一种第二次交织及解交织的方法和装置 Download PDF

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Publication number
WO2009152770A1
WO2009152770A1 PCT/CN2009/072321 CN2009072321W WO2009152770A1 WO 2009152770 A1 WO2009152770 A1 WO 2009152770A1 CN 2009072321 W CN2009072321 W CN 2009072321W WO 2009152770 A1 WO2009152770 A1 WO 2009152770A1
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Prior art keywords
data
column
address
deinterleaving
interleaving
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PCT/CN2009/072321
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English (en)
French (fr)
Inventor
袁学龙
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中兴通讯股份有限公司
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Priority to US12/999,599 priority Critical patent/US8364916B2/en
Publication of WO2009152770A1 publication Critical patent/WO2009152770A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation

Definitions

  • the present invention relates to interleaving and de-interleaving techniques in a mobile communication system, and more particularly to a second interleaving and de-interleaving method and apparatus.
  • channel coding is only effective when detecting and correcting single bit errors and not too long bit error strings. In practical applications, bit errors often occur in a string. When a long bit error string is encountered, the channel coding is performed. I can't correct it correctly.
  • This method is an interleaving technique, in which the transmitted data is interleaved in the uplink, and successive bits are transmitted in a non-sequential out-of-order manner; in the downlink, the received interleaved data is deinterleaved. , restores non-sequential out-of-order bits to successive bits.
  • the interleaving process is divided into a first interleaving and a second interleaving of the uplink, and a first deinterleaving and a second deinterleaving of the corresponding downlink.
  • a data packet can be divided into several data frames, which are respectively transmitted from different transmission channels, and each data frame has a transmission time of 10 milliseconds.
  • Different time delay requirements are specified in the Third Generation Partnership Organization (3GPP) protocol. According to these delay requirements, the time interval for transmitting data may be 10 milliseconds, 20 milliseconds, 40 milliseconds, or 80 milliseconds, that is, 1 may be transmitted separately.
  • the first interleaving is performed by interleaving between data frames, that is, the data frames are inter-interleaved and then mapped to the physical channel, instead of being directly mapped to the physical channel in order; the second interleaving is data carried in a single physical channel.
  • Interleaving, using the method of writing data to the interleaving matrix, the specific process of the second interleaving includes the following steps: Step 11. Construct an interlacing matrix.
  • the number of columns of the interleaving matrix specified by the second interleaving is fixed to 30, and the number of rows is calculated according to the data to be transmitted in the channel, that is, the length of the data to be transmitted M is divided by 30, and if it can be divisible, the obtained quotient m That is, the number of rows of the interleaving matrix; if it is not divisible, the obtained quotient m plus 1 is the number of rows of the interleaving matrix. Then, based on the number of columns and the calculated number of rows, a two-dimensional array is initialized, and the interleave matrix is represented by the address determined by the two-dimensional array.
  • Step 12 The data to be transmitted is sequentially written into the interleaving matrix in the order of rows. If the length M of the data to be transmitted is not a multiple of 30, that is, the data to be transmitted cannot fill the interleaving matrix, and the invalid data needs to be filled in the interleaving. At the end of the last line of the matrix, the invalid data may be a null bit.
  • Step 13 The data in the column of the interleaving matrix is replaced according to the inter-column replacement rule specified by the 3GPP.
  • Table 1 shows an interleaved column permutation table based on the inter-column replacement rule.
  • the data position of the 0th column before interleaving is unchanged, and the data of the 20th column before interleaving is replaced by the first column of data after interleaving, and the 10th column before interleaving.
  • the data is replaced by the second column of data after interleaving, and the data of the fifth column before interleaving is replaced with the third column of data after interleaving, and the order of all the columns of the interleave matrix is replaced by this rule.
  • the row number and column number of the matrix in which the data is located are obtained.
  • the invalid data stored at the end of the interleaving matrix is also replaced according to the above-described inter-column replacement rule.
  • the interleaving matrix is 1 line 30. Column, and the last three columns, column 27, column 28, and The 29 columns store invalid data.
  • Table 1 the data of the 27th column before interleaving is replaced by the 28th column of data after interleaving, and the data of the 28th column before interleaving is replaced by the 12th column of data after interleaving, and the data of the 29th column before interleaving is replaced by interleaving. After the 24th column of data. After interleaving, the invalid data and the data to be transmitted are interleaved in the interleaving matrix.
  • Step 14 The interleaver matrix after the column replacement is read in the order of the column, and the data to be transmitted is read according to the row number column number, and all the data are read out to complete the interleaving process.
  • the invalid data and the data to be transmitted are arranged in the interleaving matrix, and if they are transmitted without distinction, they will occupy unnecessary bandwidth. Therefore, a better method is to calculate whether invalid data is stored at the end of the interleaving matrix. When reading each data, it is judged whether the data is invalid data. If it is not invalid data, read it directly; if it is invalid data, skip reading
  • the second de-interleaving process is opposite to the second interleaving process, and the process includes the following steps: Step 21. Construct a de-interleaving matrix.
  • the number of columns of the deinterleaving matrix specified by the second deinterleaving is fixed to 30, and the number of rows is calculated according to the received data in the channel, that is, the received data length N is divided by 30, and if divisible, the resulting quotient n That is, the number of rows of the deinterleaving matrix; if it is not divisible, the obtained quotient n plus 1 is the number of rows of the deinterleaving matrix.
  • a two-dimensional array is initialized, and the deinterleaving matrix is represented by the address determined by the two-dimensional array.
  • Step 22 The received data is sequentially written into the deinterleaving matrix in the order of columns.
  • the invalid data is filled in. Deinterleaving the space of the last row of some columns of the matrix, the invalid data may be a null bit.
  • Step 23 Replace the data in the column in the de-interleaving matrix according to the inter-column replacement rule specified by the 3GPP.
  • Table 2 is a deinterleaved column permutation table according to the inter-column permutation rule, which is opposite to the interleaved column permutation table.
  • the data position of the 0th column before deinterleaving is unchanged, and the data of the first column before deinterleaving is replaced by deinterleaving.
  • the data in the second column before deinterleaving is replaced into the 10th column data after deinterleaving, and the data in the third column before deinterleaving is replaced into the 5th column data after deinterleaving, and this rule will be The order of all the columns of the deinterleaving matrix is replaced. It can be seen that the deinterleaved data is restored to the arrangement before data interleaving. After the replacement, the row number and column number of the matrix in which the data is located are obtained.
  • the invalid data stored at the end of some columns of the deinterleaving matrix is also replaced according to the above-mentioned inter-column replacement rule, for example, when the received data length N is 27, deinterleaving
  • the matrix is 1 row and 30 columns, and the last 3 columns, that is, the 27th column, the 28th column, and the 29th column store invalid data.
  • the data of the 27th column before deinterleaving is replaced by the 22nd column of data after deinterleaving
  • the data of the 28th column before deinterleaving is replaced by the 27th column of data after deinterleaving, and the 29th column before deinterleaving.
  • the data is replaced by the 17th column of data after deinterleaving.
  • the invalid data and the received data are arranged in a deinterleaving matrix before the column permutation.
  • Step 24 The deinterleaved matrix after the column replacement is read in the order of rows according to the row number column number, and the received data is all read out to complete the deinterleaving process.
  • the main object of the present invention is to provide a second interleaving and deinterleaving method and apparatus, which can reduce the computational complexity and does not require special hardware.
  • a second interleaving method includes: generating, for each input data, an interleaving address preset in an interleaving matrix; the method further comprising:
  • step C judging whether the read operation of the column data of the interleave matrix is completed. If yes, calculating the interleave address of the next column of the interleave matrix according to the inter-column replacement rule, and performing step D; if not, the interleave address is obtained by adding the column value to the interleave value. ;
  • the step A further includes:
  • Al initializing the interleaving address, and writing the data to the interleaving matrix according to the current interleaving address
  • step A3. Determine whether to complete the writing operation of all the data. If yes, execute step B; otherwise, remove the next data, write the data to the interleaving matrix according to the current interleaving address, and return to step A2.
  • the step B further includes initializing the column values
  • the method further includes: adding 1 to the column value, and calculating an interleaving address of the next column of the interleaving matrix according to the column-column replacement rule between columns.
  • the inter-column replacement rule is: an inter-column replacement rule of a 30-column matrix specified by 3GPP.
  • a second interleaving device comprising:
  • the interleaving data writing module is configured to receive data, sequentially generate an interleaving address according to the data receiving order, and respectively send the interleaving address and data to the interleaving storage module;
  • An interleaving memory module configured to receive an interleaving address and data of the interleaved data writing module, store data according to an interleave address of the interleaved data writing module, and receive an interleaving address of the interleaved data reading module according to the interleaving from the interleaved data reading module
  • the address sends the data to the interleaved data reading module;
  • the interleaving end determining module is configured to determine whether the interleaving address from the interleaved data writing module is the last column address, and is not sent to the interleaved data reading module in the column when the end address is not listed.
  • the signal when the end address of the column is sent to the interleaved inter-column conversion module, sends a column end signal
  • An interleaved inter-column conversion module configured to calculate an interleave address of a next column according to an inter-column permutation rule and a column end signal from the interleave end decision module, and send the interleave address to the interleaved data reading module; the interleaved data reading module, And configured to calculate a next interleave address of the column according to a signal in a column from the interleaved column end judging module, and receive an interleave address of the interleaved inter-column conversion module; and read data from the interleave memory module one by one according to the interleave address sent to the interleave memory module. And send the data out.
  • a second deinterleaving method comprising:
  • step c determine whether to complete all data write operations, if completed, perform step d; otherwise, take a data, the data is written to the deinterleaving matrix according to the deinterleave address, return to step b;
  • the step d further includes:
  • Dl initializing the deinterleaving address, reading data from the deinterleaving matrix according to the deinterleaving address; d2, adding 1 to the current deinterleaving address;
  • step d3. Determine whether the reading operation of all the data is completed. If it is completed, the second deinterleaving ends; otherwise, the data is read out from the deinterleaving matrix according to the current deinterleaving address, and the process returns to step d2.
  • the step a further includes initializing the column values; If the writing operation of the column data of the deinterleaving matrix is completed in step b, the method further comprises: adding 1 to the column value, and calculating a deinterleaving address of the next column of the deinterleaving matrix according to the column value replacement corresponding column replacement rule.
  • the inter-column replacement rule is: an inter-column replacement rule of a 30-column matrix specified by 3GPP.
  • a second deinterlacing device comprising:
  • Deinterleaving data writing module configured to receive data, calculate a next deinterleaving address of the column according to a signal from a column of the deinterleaving column end judging module, and receive a deinterleaving address of the deinterleaving inter-column conversion module, and deinterleave
  • the address and data are sent to the deinterleaving storage module;
  • a deinterleaving memory module configured to receive a deinterleaved address and data of the deinterleaved data writing module, store data according to a deinterleaving address of the deinterleaving data writing module, and receive a deinterleaving address of the deinterleaving data reading module, according to The deinterleaving address of the deinterleaving data reading module sends the data to the deinterleaving data reading module;
  • the deinterleaving column end judging module is configured to determine whether the deinterleaving address from the deinterleaving data writing module is a column end address, and when not the column end address, send a signal in the column to the deinterleaving data writing module, which is a column end address Sending a column end signal to the deinterleaved inter-column conversion module;
  • a deinterleaving inter-column conversion module configured to calculate a deinterleaving address of a next column according to an inter-column permutation rule and a column end signal from the deinterleaving column end judging module, and send the deinterleaving address to the deinterleaving data writing module;
  • the interleaved data reading module sequentially generates a deinterleaving address according to the data sending order, and sends the generated deinterleaving address to the deinterleaving storage module, and reads data from the deinterleaving storage module one by one according to the deinterleaving address sent to the deinterleaving storage module. And send the data out.
  • the present invention determines the position of the data in the interleaving matrix or the de-interleaving matrix by using the interleaving address or the de-interleaving address, without calculating the row number and the column number of the matrix in which the data is located, that is, without calculating the number of rows of the interleaving matrix or the de-interleaving matrix.
  • Constructing an interleaving matrix or a de-interleaving matrix eliminates redundant division operations and saves the corresponding division unit, reducing the chip area. It conforms to the development trend of small size and low power consumption of mobile communication terminals, and has good practical value.
  • FIG. 1 is a schematic flow chart of a method for implementing a second interleaving process according to the present invention
  • FIG. 2 is a schematic structural diagram of a second interlacing device of the present invention.
  • FIG. 3 is a schematic flow chart of a method for implementing a second deinterleaving process according to the present invention
  • FIG. 4 is a schematic structural diagram of a second deinterlacing device of the present invention.
  • the present invention is different from the prior art method for determining the position in the interleaving matrix or the de-interleaving matrix in which the data is located by using the row number and the column number, and determining the position of the data in the interleaving matrix or the de-interleaving matrix by using the interleaving address or the de-interleaving address. The calculation is easier.
  • the interleave address or the deinterleave address is in the order of the matrix row: the interleave address of the 0th row and the 0th column of the interleave matrix is 0, and the interleave address of the 0th row and the 1st column is 1, the 0th row and the 29th column
  • the interleave address is 29, the interleave address of the 0th column of the 1st row is 30, and so on.
  • the length of the data to be transmitted is M
  • the required interleave address is also M.
  • the general interleave address is 0 to M minus 1, and the value of the interlaced address is always smaller than the data length to be transmitted.
  • the deinterleaving address order is the same as the interleaving address order and is always less than the received data length.
  • FIG. 1 is a schematic flowchart of a method for implementing a second interleaving process according to the present invention. As shown in FIG. 1, the method includes the following steps:
  • Step 101 Initialize the interleave address.
  • the interleave address can be initialized to 0.
  • Step 102 Write data to the current interleaved address location of the interlace matrix.
  • Step 103 Add 1 to the interleaved address.
  • Step 104 Determine whether the write operation of all data is completed. If yes, execute step 105; if not, execute step 102.
  • the interleave address is always smaller than the data length of the required transmission, that is, the interleave address is at most M minus 1, it is only necessary to determine whether the interleave address is greater than the difference of M minus 1, and if it is greater, it indicates that all data write operations have been completed; If it is not greater than, it means that all data is not written.
  • the M data to be transmitted can be written to the position corresponding to the interlace matrix according to the interleaved address sequentially generated.
  • Step 105 Initialize the interleave address and the column value, and initialize the interleave address and the column value to 0.
  • Step 106 Read data from a corresponding position of the interlace matrix according to the current interleave address.
  • Step 107 Determine whether to complete the read operation of the column data of the interleave matrix. If yes, execute step 108; if not, execute step 109.
  • the interleaving matrix is a 30-column matrix
  • the last 30 interleaving addresses must be at the end of the column of the interleaving matrix. Therefore, it is only necessary to judge whether the interleaving address is greater than the difference of M minus 31. If it is greater than, the reading of the data of the interleaving matrix is completed. Operation; if not greater, it means that the read operation of one column of data of the interleave matrix is not completed.
  • Step 108 Add 1 to the column value, and calculate an interleave address of the next column of the interleave matrix according to the inter-column replacement rule of the column value, and go to step 110.
  • the inter-column replacement rule may be an inter-column replacement rule of a 30-column matrix prescribed by 3GPP.
  • Step 109 Add the interleave address to the column spacing.
  • the column pitch is the column difference of the adjacent interleave addresses, and since the interleave matrix used in the present invention is a 30-column matrix, the column pitch is 30. Thus, by adding 30 to the interleaved address, the next interleaved address of the column is obtained.
  • the interleaving matrix is not limited to the 30-column matrix, and other interleaving matrices may be used. Regardless of which interleaving matrix is used, the processing is the same as this process, and details are not described herein again.
  • Step 110 Determine whether the reading operation of all data is completed. If not, execute step 106; if complete, the second interleaving process ends.
  • the interleave address is always smaller than the data length M of the required transmission, that is, the interleave address is at most M minus 1, it is only necessary to determine whether the interleave address is greater than the difference of M minus 1, and if it is greater than, the second interleaving process ends; If it is not greater than, then step 106 is performed.
  • step 107 When the data is read by the step 106 to the step 110, it is determined according to step 107 whether the read operation of the column data of the interleave matrix is completed. If not, the next address of the column obtained in step 109 is sequentially read downward; if it is completed, Then, according to step 108, the next column interleave address calculated according to the inter-column replacement rule is changed to the next column to sequentially read the data. The entire process loops back until all data is read.
  • FIG. 2 is a schematic structural diagram of a second interlacing device of the present invention. As shown in FIG. 2, the device includes:
  • the interleaved data writing module 201 is configured to receive data sent from outside the second interleaving device, sequentially generate interleave addresses according to the data receiving order, and respectively send the interleaved address and the data to the interleave storage module 202.
  • the interleaved data writing module 201 each time a data is received, the interleaved data writing module 201 generates an interleaving address for the data, and may first initialize the interleaving address to 0, and then after the data is read according to the current interleaving address, the interleaving address is incremented by one. The interleaved address of the next data.
  • the interleaving memory module 202 is configured to receive the interleaved address and data sent by the interleaved data writing module 201, store the data according to the interleave address of the interleave data writing module 201, and also receive the interlace sent by the interleaved data reading module 205.
  • the address, the data corresponding to the interleaved address sent from the interleaved data reading module 205 is sent to the interleaved data reading module 205.
  • the interleaved end determination module 203 is configured to determine, according to the interleave address sent by the interleave storage module 205, whether the interleave address is the end of the column address according to the interleave address sent by the interleave data writing module 201, and if not, read the interleaved data. Module 205 sends the signal in the column, and if so, sends the end of column signal to interleaved inter-column conversion module 204.
  • the interleaved inter-column conversion module 204 is configured to calculate an interleave address of the next column according to the end-of-column signal sent by the interleave column end judging module 203, and send the calculated interleave address to the interleave data reading module 205.
  • the interleaved inter-column conversion module 204 increments the column value by 1 and calculates the converted interleave address corresponding to the current column value according to the inter-column permutation rule, and sends the converted interleave address.
  • the interleaved data reading module 205 is provided.
  • the interleaved data reading module 205 is configured to calculate the next interleaving address of the column according to the signal in the column sent by the interleaving column end determining module 203; and is further configured to receive the interleaving address sent by the interleaving inter-column conversion module 204, and interleave the interleaving address The address is sent to the interleave storage module 202; and is further configured to read data from the interleave storage module 202 one by one according to the interleave address sent by the interleave storage module 202, and transmit the data from the second interleaving device.
  • the interleave address may be initialized to 0, and the interleaved address is simultaneously sent to the interleave storage module 202 and the interleaved end decision module 203.
  • the interleave storage module 202 sends the data corresponding to the current interleave address to the interleave data reading module 205.
  • the interleave end decision module 203 determines whether the current interleave address is the end of the column address. If not, the interleave address of the next data is read by the interleaved data.
  • Module 205 increments the current interleaved address by 30; if so, the interleaved address of the next data is computed by interleaved inter-column conversion module 204.
  • FIG. 3 is a schematic flowchart of a method for implementing a second deinterleaving process according to the present invention. As shown in FIG. 3, the method includes the following steps:
  • Step 301 Initialize the deinterleaving address and the column value.
  • the deinterleave address can be initialized to 0.
  • Step 302 Write the data to the deinterleaving matrix according to the deinterleaving address.
  • Step 303 Determine whether the write operation of the data of the deinterleaving matrix is completed. If yes, execute step 304. If not, go to step 305.
  • the de-interleaving matrix is a 30-column matrix
  • the last 30 bits of the de-interleaving address must be at the end of the column of the de-interleaving matrix.
  • the length of the received data is N, it is only necessary to determine whether the deinterleaving address is greater than the difference of N minus 31. If it is greater, it indicates that the write operation of the data of the deinterleaving matrix is completed. If not, the deinterleaving is not completed.
  • Step 304 The column value is incremented by one, and the deinterleaving address of the next column of the deinterleaving matrix is calculated according to the inter-column replacement rule corresponding to the column value, and step 306 is performed.
  • the inter-column replacement rule may be an inter-column replacement rule of a 30-column matrix prescribed by 3GPP.
  • Step 305 Add the deinterleaving address to the column spacing.
  • the column pitch is the column difference of the adjacent deinterleaving addresses, and since the deinterleaving matrix used in the present invention is a 30 column matrix, the column pitch is 30.
  • the deinterleaving address is obtained by adding 30 to its own value, that is, the next deinterleaving address of the column is obtained.
  • the de-interleaving matrix is not limited to the 30-column matrix, and other de-interleaving matrices may be used. Regardless of which de-interleaving matrix is used, the processing is the same as this process, and details are not described herein again.
  • Step 306 It is judged whether the writing operation of all the data is completed. If yes, step 307 is performed; if not, step 302 is performed.
  • the deinterleaving address is always smaller than the received data length N, that is, the deinterleaving address is at most N minus 1, it is only necessary to judge whether the deinterleaving address is greater than the difference of N minus 1, and if it is greater, it indicates that all data has been completed. Write operation; if it is not greater than, it means that all data is not written.
  • step 303 When the data is written in step 302 to step 306, it is determined according to step 303 whether the write operation of the data of the deinterleaving matrix is completed. If not, the next address of the column obtained in step 305 is sequentially written downward; Then, according to step 304, the next column deinterleaving address calculated according to the inter-column replacement rule is switched to the next column to sequentially write data. The entire process loops back until all data is written.
  • Step 307 Initialize the deinterleaving address.
  • the deinterleave address can be initialized to 0.
  • Step 308 Read data from the deinterleaving matrix according to the deinterleaving address.
  • Step 309 Add 1 to the deinterleave address.
  • Step 310 Determine whether the read operation of all data is completed. If not, execute step 308; if completed, the second deinterleave process ends.
  • the deinterleaving address is always smaller than the received data length N, that is, the deinterleaving address is at most N minus 1, it is only necessary to judge whether the deinterleaving address is greater than N minus one, and if it is greater than, All data read operations have been completed; if not greater, it means that all data read operations have not been completed.
  • the received N data are sequentially read out from the positions corresponding to the deinterleaving matrix according to the deinterleaved addresses generated in sequence.
  • FIG. 4 is a schematic structural diagram of a second deinterleaving device of the present invention. As shown in FIG. 4, the device includes:
  • Deinterleaving data writing module 401 configured to receive data from the outside of the second deinterleave device; and further configured to calculate a next deinterleaving address of the column according to the signal in the column sent by the deinterleaving column end determining module 402; It is also used to receive the deinterleaving address sent by the deinterleaving inter-column conversion module 403, and send the de-interleaving address and data to the de-interleaving storage module 404, respectively.
  • the deinterleaving address may be initialized to 0, and the deinterleaving address is simultaneously sent to the deinterleaving storage module 404 and the deinterleaving column end determining module 402.
  • the deinterleaving column end determining module 402 Determining whether the current deinterleave address is a column end address, if not, the deinterleave data writing module 401 adds 30 the current deinterleave address to obtain a deinterleave address of the next data; if so, the deinterleaving inter column conversion module 403 calculates Get the deinterleaved address of the next data.
  • the deinterleaving storage module 404 is configured to receive the deinterleaved address and data sent by the deinterleaving data writing module 401, and store data according to the deinterleaving address sent by the deinterleaving data writing module 401; and is further configured to receive the deinterleaved data.
  • the deinterleaving address sent by the reading module 405 is sent to the deinterleaving data reading module 405 by the data corresponding to the deinterleaving address sent by the deinterleaving data reading module 405.
  • the deinterleaving column end determining module 402 is configured to determine, according to the deinterleaving address received by the deinterleave data writing module 401, whether the deinterleaving address is a column end address, and if yes, send the deinterleave data writing module 401 The signal in the column, otherwise the end-of-column signal is sent to the deinterleaved inter-column conversion module 403.
  • the de-interleaving matrix is a 30-column matrix
  • the last 30 of the de-interleaving addresses must be at the end of the de-interleaving matrix. According to the received data length N, it is judged whether the deinterleaving address is greater than the difference of N minus 31, that is, whether it is the last 30 deinterleaving addresses, and whether the deinterleaving address is the end of column address.
  • the interleaved data is written to the module 401.
  • the deinterleaving inter-column conversion module 403 increments the column value by 1, and calculates the converted de-interleaved address corresponding to the current column value according to the inter-column permutation rule, and sends the de-interleaved address to The deinterleaved data is written to the module 401.
  • the deinterleaving data reading module 405 is configured to sequentially generate a deinterleave address according to the data transmission order, and send the deinterleave address to the deinterleave storage module 404, and decompose the solution according to the deinterleave address sent to the deinterleave storage module 404.
  • the interleaved memory module 404 reads the data and transmits the data from the second deinterleaving device.
  • the deinterleaving address may be initialized to 0 first, and after the data is read according to the current deinterleaving address, the deinterleaving address is incremented by 1 to obtain the deinterleaving address of the next data.
  • the present invention determines the position of the data in the interleaving matrix or the de-interleaving matrix by using the interleaving address or the de-interleaving address, without calculating the row number and the column number of the matrix in which the data is located, that is, without calculating the number of rows of the interleaving matrix or the de-interleaving matrix.
  • Constructing an interleaving matrix or a de-interleaving matrix eliminates redundant division operations and saves the corresponding division unit, reducing the chip area. It conforms to the development trend of small size and low power consumption of mobile communication terminals, and has good industrial applicability.

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Description

一种第二次交织及解交织的方法和装置
技术领域
本发明涉及移动通信系统中的交织及解交织技术， 尤其涉及一种第二次 交织及解交织的方法和装置。
背景技术
在移动通信中， 由于无线信道的衰落， 传送的数据流会产生误码， 因此 需要通过信道编码对数据流进行相应的处理， 提高数据传输的纠错能力和可 靠性。 但是信道编码仅在检测和校正单个比特差错和不太长的比特差错串时 才有效， 而在实际应用中， 比特差错经常成串发生， 当遇到较长的比特差错 串时， 信道编码就不能正常纠错了。
为了解决这一问题， 需要将一条消息中的相继比特分散开， 即将一条消 息中的相继比特以非相继方式发送， 这样， 在传输过程中即使发生成串差错， 恢复成一条相继比特串的消息时， 比特差错也就变成单个或长度很短的比特 串， 这时就可以通过信道编码纠正差错， 恢复原消息。 这种方法就是交织技 术， 即在上行链路中， 将发送的数据进行交织， 将相继比特以非相继的乱序 方式发送； 在下行链路中， 将接收到的经过交织的数据进行解交织， 将非相 继的乱序比特还原成相继比特。 交织过程分为上行链路的第一次交织和第二 次交织， 以及对应下行链路的第一次解交织和第二次解交织。
在第三代（3G )无线通信中， 一个数据包可以分成若干个数据帧， 这些 数据帧分别从不同的传输信道传输， 每个数据帧的传输时间为 10毫秒。 第三 代合作伙伴组织（3GPP )协议中规定了不同的时延要求，按照这些时延要求， 传输数据的时间间隔可以为 10毫秒、 20毫秒、 40毫秒或 80毫秒， 即： 可以 分别传输 1个数据帧、 2个数据帧、 4个数据帧或 8个数据帧。 第一次交织是 在数据帧间进行交织， 即将上述数据帧进行帧间交织后再映射到物理信道， 而不是按顺序直接映射到物理信道； 第二次交织是在单个物理信道中承载的 数据间进行交织， 釆用了将数据写入交织矩阵的方法， 第二次交织的具体过 程包括以下步骤： 步骤 11、 构造一个交织矩阵。
一般， 第二次交织规定的交织矩阵列数固定为 30, 行数根据信道中需要 传输的数据计算得出， 即： 需要传输的数据长度 M除以 30, 如果能整除， 则 所得的商 m即为交织矩阵的行数； 如果不能整除， 则所得的商 m加 1即为交 织矩阵的行数。 然后， 根据列数和计算所得的行数， 初始化一个二维数组， 由该二维数组所确定的地址来表示交织矩阵。
步骤 12、 将需要传输的数据按行的顺序依次写入交织矩阵中， 如果需要 传输的数据长度 M不是 30的倍数， 即需要传输的数据无法填满交织矩阵， 需要将无效数据依次填入交织矩阵最后一行的末尾的空处， 所述的无效数据 可以为空比特。
步骤 13、 根据 3GPP规定的列间置换规则将交织矩阵中列的数据进行置 换。
表 1为根据列间置换规则制定的交织列置换表， 例如， 交织前第 0列的 数据位置不变， 交织前第 20列的数据置换成为交织后的第 1列数据， 交织前 第 10列的数据置换成为交织后的第 2列数据，交织前第 5列的数据置换成为 交织后的第 3列数据， 以此规则将交织矩阵所有列的顺序进行置换。 经过置 换后， 得到数据所在矩阵的行号和列号。
Figure imgf000004_0001
表 1
当需要传输的数据长度 M不是 30的倍数时， 将存储在交织矩阵末尾处 的无效数据也按照上述列间置换规则进行置换， 例如需要传输的数据长度 M 为 27时， 交织矩阵为 1行 30列， 并且最后 3列， 即第 27列、 第 28列和第 29列存储的是无效数据。 如表 1所示， 交织前第 27列的数据置换成为交织 后的第 28列数据， 交织前第 28列的数据置换成为交织后的第 12列数据， 交 织前第 29列的数据置换成为交织后的第 24列数据。 在交织后， 无效数据和 需要传输的数据交叉排列在交织矩阵之中。
步骤 14、 将列置换后的交织矩阵按列的顺序， 根据行号列号读取需要传 输的数据， 数据全部读出完成交织过程。
需要注意的是， 无效数据和需要传输的数据交叉排列在交织矩阵中， 如 果不加区分传输出去， 会占用不必要的带宽。 由此， 更好的方法是， 需要计 算交织矩阵末尾是否存储了无效数据。 读取每一个数据时， 判断该数据是否 为无效数据。 如果不是无效数据， 直接读取； 如果是无效数据， 跳过读取下
—数据„
第二次解交织过程与第二次交织过程相反， 其过程包括如下步骤： 步骤 21、 构造一个解交织矩阵。
第二次解交织规定的解交织矩阵列数固定为 30, 行数根据信道中接收到 的数据计算得出， 即： 接收到的数据长度 N除以 30, 如果能整除， 则所得的 商 n即为解交织矩阵的行数； 如果不能整除， 则所得的商 n加 1即为解交织 矩阵的行数。 然后， 根据列数和计算所得的行数， 初始化一个二维数组， 由 该二维数组所确定的地址来表示解交织矩阵。 步骤 22、 将接收到的数据按列的顺序依次写入解交织矩阵中， 如果接收 到的数据长度 N不是 30的倍数， 即接收到的数据无法填满解交织矩阵，那么 将无效数据填入解交织矩阵某些列的最后一行的空处， 所述无效数据可以为 空比特。
步骤 23、 根据 3GPP规定的列间置换规则， 将解交织矩阵中列的数据进 行置换。
表 2为根据列间置换规则制定的解交织列置换表，与交织列置换表相反， 例如， 解交织前第 0列的数据位置不变， 解交织前第 1列的数据置换成为解 交织后的第 20列数据， 解交织前第 2列的数据置换成为解交织后的第 10列 数据， 解交织前第 3列的数据置换成为解交织后的第 5列数据， 以此规则将 解交织矩阵所有列的顺序进行置换。 可见， 经过解交织后的数据还原成数据 交织前的排列。 经过置换后， 得到数据所在矩阵的行号和列号。
当接收到的数据长度 N不是 30的倍数时， 存储在解交织矩阵某些列末 尾处的无效数据也按照上述列间置换规则进行了置换， 例如接收到的数据长 度 N为 27时， 解交织矩阵为 1行 30列， 并且最后 3列， 即第 27列、 第 28 列和第 29列存储的是无效数据。 如表 1所示， 解交织前第 27列的数据置换 成为解交织后的第 22列数据， 解交织前第 28列的数据置换成为解交织后的 第 27列数据， 解交织前第 29列的数据置换成为解交织后的第 17列数据。 在 列置换前， 无效数据和接收到的数据交叉排列在解交织矩阵之中。
Figure imgf000006_0001
表 2
步骤 24、 将列置换后的解交织矩阵按行的顺序根据行号列号读取接收到 的数据， 接收到的数据全部读出完成解交织过程。
需要注意的是， 在写数到解交织矩阵时， 有些列的最后一行应填充无效 数据。 因此需要计算无效数据的填充位置。 在读取每一个数据时， 判断该数 据是否为无效数据。 如果不是无效数据， 直接读取； 如果是无效数据， 跳过 读取下一数据。 由以上分析可以看出， 现有技术中交织或解交织方法存在以下问题：
1 )构造交织矩阵或解交织矩阵时， 需要利用除法计算写入矩阵的数据占 用的行数， 计算复杂， 且硬件上需要专门的除法运算单元。
2 )如果数据无法填满交织矩阵或解交织矩阵时填入无效数据， 相应地， 在数据交织或解交织时， 需要通过计算得到矩阵中哪些数据是无效数据， 增 加了运算的复杂度。
发明内容
有鉴于此， 本发明的主要目的在于提供一种第二次交织及解交织的方法 和装置， 能降低运算复杂度， 且不需要专门的硬件。
为达到上述目的， 本发明的技术方案是这样实现的：
一种第二次交织方法， 包括： 为每个输入数据生成一个预先设定在交织 矩阵中的交织地址； 该方法还包括：
A、 按交织地址顺序将数据写入交织矩阵；
B、 对交织地址初始化， 根据交织地址从交织矩阵中读取数据；
C、判断是否完成交织矩阵一列数据的读操作， 如果完成， 则根据列间置 换规则计算交织矩阵下一列的交织地址， 执行步骤 D; 如果未完成， 则交织 地址由自身值加上列间距得到；
D、 判断是否完成所有数据的读操作， 如果完成， 则第二次交织结束； 否则， 根据当前交织地址从交织矩阵中读取数据， 返回步骤 。
较佳的， 所述步骤 A进一步包括：
Al、 对交织地址初始化， 将数据 4艮据当前交织地址写入交织矩阵；
A2、 将当前交织地址加 1；
A3、 判断是否完成所有数据的写操作， 如果完成， 则执行步骤 B; 否则， 取下一个数据， 将数据根据当前交织地址写入交织矩阵， 返回步骤 A2。
较佳的， 所述步骤 B进一步包括对列值初始化；
步骤 C中如果完成交织矩阵一列数据的读操作， 进一步包括： 将列值加 1 , 根据列值对应列间置换规则计算交织矩阵下一列的交织地址。
较佳的， 所述列间置换规则为： 3GPP规定的 30列矩阵的列间置换规则。 一种第二次交织装置， 包括：
交织数据写入模块， 用于接收数据， 根据数据接收顺序依次生成交织地 址， 并分别将交织地址和数据发送给交织存储模块； 交织存储模块， 用于接收交织数据写入模块的交织地址和数据， 根据交 织数据写入模块的交织地址存储数据， 以及接收交织数据读取模块的交织地 址，根据来自交织数据读取模块的交织地址将数据发送给交织数据读取模块； 交织列末判断模块， 用于判断来自交织数据写入模块的交织地址是否为 列末地址， 不为列末地址时向交织数据读取模块发送列中信号， 为列末地址 时向交织列间转换模块发送列末信号；
交织列间转换模块， 用于根据列间置换规则和来自交织列末判断模块的 列末信号计算下一列的交织地址，并将该交织地址发送给交织数据读取模块； 交织数据读取模块， 用于根据来自交织列末判断模块的列中信号计算该 列下一个交织地址， 以及接收交织列间转换模块的交织地址； 并根据发送给 交织存储模块的交织地址逐个从交织存储模块读取数据， 并将该数据发送出 去。
一种第二次解交织方法， 包括：
a、对预先设定在解交织矩阵中的解交织地址初始化， 将数据根据解交织 地址写入解交织矩阵；
b、 判断是否完成解交织矩阵一列数据的写操作， 如果完成， 则根据列间 置换规则计算解交织矩阵下一列的解交织地址； 否则， 将解交织地址加上列 间距；
c、 判断是否完成所有数据的写操作， 如果完成， 则执行步骤 d; 否则， 取下一个数据， 将数据根据解交织地址写入解交织矩阵， 返回步骤 b;
d、 按解交织地址顺序从解交织矩阵中读取数据。
较佳的， 所述步骤 d进一步包括：
dl、 对解交织地址初始化， 将数据根据解交织地址从解交织矩阵读出； d2、 将当前解交织地址加 1 ;
d3、 判断是否完成所有数据的读操作， 如果完成， 则第二次解交织结束； 否则， 将数据根据当前解交织地址从解交织矩阵读出， 返回步骤 d2。
较佳的， 所述步骤 a进一步包括对列值初始化； 步骤 b中如果完成解交织矩阵一列数据的写操作， 进一步包括： 将列值 加 1 , 根据列值对应列间置换规则计算解交织矩阵下一列的解交织地址。 较佳的， 所述列间置换规则为： 3GPP规定的 30列矩阵的列间置换规则。 一种第二次解交织装置， 包括：
解交织数据写入模块， 用于接收数据， 根据来自解交织列末判断模块的 列中信号计算该列下一个解交织地址， 以及接收解交织列间转换模块的解交 织地址， 并将解交织地址和数据发送给解交织存储模块；
解交织存储模块， 用于接收解交织数据写入模块的解交织地址和数据， 根据解交织数据写入模块的解交织地址存储数据， 以及接收解交织数据读取 模块的解交织地址， 根据来自解交织数据读取模块的解交织地址将数据发送 给解交织数据读取模块；
解交织列末判断模块， 用于判断来自解交织数据写入模块的解交织地址 是否为列末地址， 不为列末地址时向解交织数据写入模块发送列中信号， 为 列末地址时向解交织列间转换模块发送列末信号；
解交织列间转换模块， 用于根据列间置换规则和来自解交织列末判断模 块的列末信号计算下一列的解交织地址， 并将该解交织地址发送给解交织数 据写入模块； 解交织数据读取模块， 根据数据发送顺序依次生成解交织地址， 并将生 成的解交织地址发送给解交织存储模块， 根据发送给解交织存储模块的解交 织地址逐个从解交织存储模块读取数据， 并将该数据发送出去。
本发明釆用交织地址或解交织地址确定数据在交织矩阵或解交织矩阵中 的位置， 无需计算数据所在矩阵的行号和列号， 即无需通过计算交织矩阵或 解交织矩阵的行数即可构造交织矩阵或解交织矩阵，免去了多余的除法运算， 也节省了相应的除法运算单元， 减少了芯片的面积。 符合移动通信终端体积 小、 功耗低的发展趋势， 拥有良好的实用价值。
本发明的方法中， 将数据从交织矩阵按列读出、 或将数据按列写入到解 交织矩阵时， 为每个数据生成一个交织地址或解交织地址， 按交织地址或解 交织地址直接将相应数据写入交织矩阵或解交织矩阵， 而无需按行号、 列号 将相应数据写入交织矩阵或解交织矩阵， 无需写入无效数据。 节省了现有技 术中计算交织矩阵或解交织矩阵最后一行每一列是否为无效数据的步骤， 降 低了运算复杂度， 提高了运算效率。 附图概述
图 1为本发明第二次交织处理实现方法的流程示意图；
图 2为本发明第二次交织装置的组成结构示意图；
图 3为本发明第二次解交织处理实现方法的流程示意图；
图 4为本发明第二次解交织装置的组成结构示意图。
本发明的较佳实施方式
本发明不同于现有技术中釆用行号、 列号确定数据所在交织矩阵或解交 织矩阵中位置的方法， 釆用交织地址或解交织地址确定数据在交织矩阵或解 交织矩阵中的位置， 运算更加简便。
具体地， 交织地址或解交织地址按所在矩阵行的顺序为： 交织矩阵第 0 行第 0列的交织地址为 0, 第 0行第 1列的交织地址为 1 , 第 0行第 29列的 交织地址为 29, 第 1行第 0列的交织地址为 30, 以此类推。 如果需要传输的 数据长度为 M, 则所需交织地址也为 M个， 一般交织地址为 0到 M减 1 , 交 织地址的值总小于所需传输的数据长度。 解交织地址顺序与交织地址顺序相 同， 且总小于接收到的数据长度。
下面结合附图和具体实施例对本发明的技术方案作进一步详细阐述。 图 1为本发明的第二次交织处理实现方法的流程示意图， 如图 1所示， 该方法包括如下步骤：
步骤 101 : 对交织地址初始化。
其中， 可将交织地址初始化为 0。
步骤 102: 将数据写入交织矩阵的当前交织地址位置。
步骤 103： 将交织地址加 1。 步骤 104:判断是否完成所有数据的写操作，如果完成，则执行步骤 105; 如果未完成， 则执行步骤 102。
这里， 由于交织地址总小于所需传输的数据长度， 即交织地址最大为 M 减 1 , 故只需判断交织地址是否大于 M减 1的差， 如果大于， 则表示已经完 成所有数据的写操作； 如果不大于， 则表示未完成所有数据的写操作。
通过步骤 102到步骤 104的循环写操作， 可将所需传输的 M个数据才艮据 依次生成的交织地址写入交织矩阵对应的位置。
步骤 105: 对交织地址和列值初始化， 可将交织地址和列值全部初始化 为 0。
步骤 106: 根据当前交织地址从交织矩阵的相应位置读取数据。
步骤 107: 判断是否完成交织矩阵一列数据的读操作， 如果完成， 则执 行步骤 108; 如果未完成， 则执行步骤 109。
这里， 由于交织矩阵为 30列矩阵， 最后 30个交织地址必处在交织矩阵 的列末， 故只需判断交织地址是否大于 M减 31的差， 如果大于， 则表示完 成交织矩阵一列数据的读操作； 如果不大于， 则表示未完成交织矩阵一列数 据的读操作。
步骤 108: 将列值加 1 , 根据列值对应列间置换规则计算交织矩阵下一列 的交织地址， 执行步骤 110。
这里，所述列间置换规则可以为 3GPP规定的 30列矩阵的列间置换规则。 步骤 109: 将交织地址加列间距。
这里， 列间距为相邻交织地址的列差， 由于本发明釆用的交织矩阵为 30 列矩阵， 所以列间距为 30。 由此， 将交织地址加 30即得到了该列的下一个 交织地址。
在实际应用中， 交织矩阵不限于 30列矩阵， 可以釆用其它的交织矩阵， 无论釆用哪种交织矩阵， 处理过程均与本流程相同， 这里不再赘述。
步骤 110: 判断是否完成所有数据的读操作， 如果未完成， 则执行步骤 106; 如果完成， 则第二次交织过程结束。 这里， 由于交织地址总小于所需传输的数据长度 M, 即交织地址最大为 M减 1 , 故只需判断交织地址是否大于 M减 1的差， 如果大于， 则第二次交 织过程结束； 如果不大于， 则执行步骤 106。
通过步骤 106到步骤 110读取数据时， 根据步骤 107判断是否完成交织 矩阵一列数据的读操作， 如果未完成， 则才艮据步骤 109得到的该列下一地址 依次向下读； 如果完成， 则根据步骤 108依据列间置换规则计算得到的下一 列交织地址， 换到下一列依次读取数据。 整个过程循环往复， 直到完成所有 数据的读操作为止。
图 2为本发明第二次交织装置的组成结构示意图， 如图 2所示， 该装置 包括：
交织数据写入模块 201 , 其用于接收从第二次交织装置外部发来的数据， 根据该数据接收顺序依次生成交织地址， 并分别将交织地址和该数据发送给 交织存储模块 202。
其中， 每接收到一个数据， 交织数据写入模块 201就为该数据生成一个 交织地址， 可先将交织地址初始化为 0, 才艮据当前交织地址读取数据后， 将 该交织地址加 1得到下一数据的交织地址。
交织存储模块 202, 其用于接收交织数据写入模块 201发来的交织地址 和数据， 根据交织数据写入模块 201的交织地址存储数据； 还用于接收交织 数据读取模块 205发来的交织地址， 将与交织数据读取模块 205发来的交织 地址对应的数据发送给交织数据读取模块 205。
交织列末判断模块 203 , 其用于根据交织数据写入模块 201发来的交织 地址由交织存储模块 205存储的交织地址判断该交织地址是否为列末地址， 如果不是， 则向交织数据读取模块 205发送列中信号， 如果是， 则向交织列 间转换模块 204发送列末信号。
由于交织矩阵为 30列矩阵， 所以交织地址的最后 30个一定处于交织矩 阵列末。根据需要传输的数据长度 M, 判断交织地址是否大于 M减 31的差， 即判断该交织地址是否为最后 30个交织地址，即可得出该交织地址是否为列 末地址。 交织列间转换模块 204 , 其用于根据由交织列末判断模块 203发来的列 末信号计算下一列的交织地址， 并将计算出的交织地址发送给交织数据读取 模块 205。
每接收到一次列末信号， 交织列间转换模块 204就将列值加 1 , 并才艮据 列间置换规则计算当前列值所对应的转换后的交织地址， 并将转换后的交织 地址发送给交织数据读取模块 205。
交织数据读取模块 205 , 其用于根据由交织列末判断模块 203发来的列 中信号计算该列下一个交织地址； 还用于接收交织列间转换模块 204发来的 交织地址， 将交织地址发送给交织存储模块 202; 还用于根据自身发送给交 织存储模块 202的交织地址， 逐个从交织存储模块 202中读取数据， 并将该 数据从第二次交织装置中发送出去。
交织数据读取模块 205读取数据时， 可先将交织地址初始化为 0, 将该 交织地址同时发送给交织存储模块 202和交织列末判断模块 203。 交织存储 模块 202将当前交织地址对应的数据发送给交织数据读取模块 205; 交织列 末判断模块 203判断当前交织地址是否为列末地址， 如果不是， 下一数据的 交织地址由交织数据读取模块 205将当前交织地址加 30得到； 如果是， 下一 数据的交织地址由交织列间转换模块 204计算得到。
图 3为本发明第二次解交织处理实现方法的流程示意图， 如图 3所示， 该方法包括如下步骤：
步骤 301 : 对解交织地址和列值初始化。
其中， 可将解交织地址初始化为 0。
步骤 302: 将数据 4艮据解交织地址写入解交织矩阵。
步骤 303 : 判断是否完成解交织矩阵一列数据的写操作， 如果完成， 则 执行步骤 304; 如果未完成， 则执行步骤 305。
这里， 由于解交织矩阵为 30列矩阵， 所以解交织地址最后 30位必处在 解交织矩阵的列末。 又由于接收到的数据长度为 N, 故只需判断解交织地址 是否大于 N减 31的差，如果大于，则表示完成解交织矩阵一列数据的写操作； 如果不大于， 则表示未完成解交织矩阵一列数据的写操作。 步骤 304: 将列值加 1 , 根据列值对应的列间置换规则计算解交织矩阵下 一列的解交织地址， 执行步骤 306。
这里，所述列间置换规则可以为 3GPP规定的 30列矩阵的列间置换规则。 步骤 305: 将解交织地址加列间距。
这里， 列间距为相邻解交织地址的列差， 由于本发明中釆用的解交织矩 阵为 30列矩阵， 所以列间距为 30。 由此， 解交织地址由自身值加 30得到， 即得到了该列的下一个解交织地址。
实际应用中，解交织矩阵不限于 30列矩阵，可以釆用其它的解交织矩阵， 无论釆用哪种解交织矩阵， 处理过程均与本流程相同， 这里不再赘述。
步骤 306:判断是否完成所有数据的写操作，如果完成，则执行步骤 307; 如果未完成， 则执行步骤 302。
这里， 由于解交织地址总小于接收到的数据长度 N, 即解交织地址最大 为 N减 1 , 故只需判断解交织地址是否大于 N减 1的差， 如果大于， 则表示 已经完成所有数据的写操作； 如果不大于， 则表示未完成所有数据的写操作。
通过步骤 302到步骤 306写入数据时， 根据步骤 303判断是否完成解交 织矩阵一列数据的写操作， 如果未完成， 则才艮据步骤 305得到的该列下一地 址依次向下写； 如果完成， 则根据步骤 304依据列间置换规则计算得到的下 一列解交织地址， 换到下一列依次写入数据。 整个过程循环往复， 直到完成 所有数据的写操作为止。
步骤 307: 对解交织地址初始化。
其中， 可将解交织地址初始化为 0。
步骤 308: 根据解交织地址从解交织矩阵中读取数据。
步骤 309: 将解交织地址加 1。
步骤 310: 判断是否完成所有数据的读操作， 如果未完成， 则执行步骤 308; 如果完成， 则第二次解交织过程结束。
这里， 由于解交织地址总小于接收到的数据长度 N, 即解交织地址最大 为 N减 1 , 故只需判断解交织地址是否大于 N减 1的差， 如果大于， 则表示 已经完成所有数据的读操作； 如果不大于， 则表示未完成所有数据的读操作。 通过步骤 308到步骤 310的循环读操作， 才艮据依次生成的解交织地址将 接收到的 N个数据依次从解交织矩阵对应的位置中读出。
图 4为本发明第二次解交织装置的组成结构示意图， 如图 4所示， 该装 置包括：
解交织数据写入模块 401 , 其用于从第二次解交织装置的外部接收数据； 还用于根据由解交织列末判断模块 402发来的列中信号计算该列下一个解交 织地址； 还用于接收解交织列间转换模块 403发来的解交织地址， 分别将解 交织地址和数据发送给解交织存储模块 404。
解交织数据写入模块 401 写入数据时， 可先将解交织地址初始化为 0, 将该解交织地址同时发送给解交织存储模块 404和解交织列末判断模块 402; 解交织列末判断模块 402判断当前解交织地址是否为列末地址， 如果不是， 则解交织数据写入模块 401将当前解交织地址加 30得到下一数据的解交织地 址； 如果是， 则解交织列间转换模块 403计算得到下一数据的解交织地址。
解交织存储模块 404, 其用于接收解交织数据写入模块 401发来的解交 织地址和数据， 根据解交织数据写入模块 401发来的解交织地址存储数据； 还用于接收解交织数据读取模块 405发来的解交织地址， 将与解交织数据读 取模块 405发来的解交织地址对应的数据发送给解交织数据读取模块 405。
解交织列末判断模块 402, 其用于根据由解交织数据写入模块 401接收 到的解交织地址判断该解交织地址是否为列末地址， 如果是， 则向解交织数 据写入模块 401发送列中信号， 否则向解交织列间转换模块 403发送列末信 号。
由于解交织矩阵为 30列矩阵， 所以解交织地址的最后 30个一定处于解 交织矩阵列末。 根据接收到的数据长度 N, 判断解交织地址是否大于 N减 31 的差， 即是否为最后 30个解交织地址， 即可得出该解交织地址是否为列末地 址。
解交织列间转换模块 403 , 其用于根据由解交织列末判断模块 402发来 的列末信号计算下一列的解交织地址， 并将该下一列的解交织地址发送给解 交织数据写入模块 401。
每接收到一次列末信号， 解交织列间转换模块 403就将列值加 1 , 并根 据列间置换规则计算当前列值所对应的转换后的解交织地址， 并将该解交织 地址发送给解交织数据写入模块 401。
解交织数据读取模块 405 , 其用于根据数据发送顺序依次生成解交织地 址， 并将该解交织地址发送给解交织存储模块 404, 根据发送给解交织存储 模块 404的解交织地址逐个从解交织存储模块 404读取数据， 并将该数据从 第二次解交织装置中发送出去。
解交织数据读取模块 405读取数据时， 可先将解交织地址初始化为 0, 根据当前解交织地址读取数据后， 将该解交织地址加 1得到下一数据的解交 织地址。
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围。
工业实用性
本发明釆用交织地址或解交织地址确定数据在交织矩阵或解交织矩阵中 的位置， 无需计算数据所在矩阵的行号和列号， 即无需通过计算交织矩阵或 解交织矩阵的行数即可构造交织矩阵或解交织矩阵，免去了多余的除法运算， 也节省了相应的除法运算单元， 减少了芯片的面积。 符合移动通信终端体积 小、 功耗低的发展趋势， 具有良好的工业实用性。

Claims

权 利 要 求 书
1、 一种第二次交织方法， 该方法为每个输入数据生成一个预先设定在交 织矩阵中的交织地址； 该方法还包括：
A、 按交织地址顺序将数据写入交织矩阵；
B、 对交织地址初始化， 根据交织地址从交织矩阵中读取数据；
C、判断是否完成交织矩阵一列数据的读操作， 如果完成， 则根据列间置 换规则计算交织矩阵下一列的交织地址， 执行步骤 D; 如果未完成， 则交织 地址由自身值加上列间距得到；
D、 判断是否完成所有数据的读操作， 如果完成， 则第二次交织结束； 否则， 根据当前交织地址从交织矩阵中读取数据， 返回步骤 。
2、根据权利要求 1所述的第二次交织方法， 其中， 所述步骤 A进一步包 括：
Al、 对交织地址初始化， 将数据 4艮据当前交织地址写入交织矩阵；
A2、 将当前交织地址加 1；
A3、 判断是否完成所有数据的写操作， 如果完成， 则执行步骤 B; 否则， 取下一个数据， 将数据根据当前交织地址写入交织矩阵， 返回步骤 A2。
3、根据权利要求 1所述的第二次交织方法， 其中， 所述步骤 B中对交织 地址初始化时， 还对列值初始化；
步骤 C中如果完成交织矩阵一列数据的读操作， 则将列值加 1 , 根据列 值对应列间置换规则计算交织矩阵下一列的交织地址。
4、 根据权利要求 1或 3所述的第二次交织方法， 其中， 所述列间置换规 则为： 3GPP规定的 30列矩阵的列间置换规则。
5、 一种第二次交织装置， 该装置包括： 交织数据写入模块、 交织存储模 块、 交织列末判断模块、 交织列间转换模块和交织数据读取模块， 其中， 所述交织数据写入模块用于从所述第二次交织装置外部接收数据， 根据 数据接收顺序依次生成交织地址， 并分别将交织地址和数据发送给所述交织 存储模块； 所述交织存储模块用于接收所述交织数据写入模块发来的交织地址和数 据， 根据所述交织数据写入模块发来的交织地址存储数据； 还用于接收所述 交织数据读取模块发来的交织地址， 将与所述交织数据读取模块发来的交织 地址对应的数据发送给所述交织数据读取模块；
所述交织列末判断模块用于判断所述交织数据写入模块生成的交织地址 是否为列末地址， 不为列末地址时向所述交织数据读取模块发送列中信号， 为列末地址时向所述交织列间转换模块发送列末信号； 所述交织列间转换模块用于根据列间置换规则和来自所述交织列末判断 模块的列末信号计算下一列的交织地址， 并将该交织地址发送给所述交织数 据读取模块； 且
所述交织数据读取模块用于根据来自所述交织列末判断模块的列中信号 计算该列下一个交织地址； 还用于接收所述交织列间转换模块发来的交织地 址； 还用于根据自身发送给所述交织存储模块的交织地址逐个从所述交织存 储模块读取数据， 并将该数据从所述第二次交织装置中发送出去。
6、 一种第二次解交织方法， 该方法包括：
a、对预先设定在解交织矩阵中的解交织地址初始化， 将数据根据解交织 地址写入解交织矩阵；
b、 判断是否完成解交织矩阵一列数据的写操作， 如果完成， 则根据列间 置换规则计算解交织矩阵下一列的解交织地址； 否则， 将解交织地址加上列 间距；
c、 判断是否完成所有数据的写操作， 如果完成， 则执行步骤 d; 否则， 取下一个数据， 将数据根据解交织地址写入解交织矩阵， 返回步骤 b;
d、 按解交织地址顺序从解交织矩阵中读取数据。
7、 根据权利要求 6所述的第二次解交织方法， 其中， 所述步骤 d进一步 包括：
dl、 对解交织地址初始化， 将数据根据解交织地址从解交织矩阵读出； d2、 将当前解交织地址加 1 ;
d3、 判断是否完成所有数据的读操作， 如果完成， 则第二次解交织结束； 否则， 将数据根据当前解交织地址从解交织矩阵读出， 返回步骤 d2。
8、 根据权利要求 6所述的第二次解交织方法， 其中， 所述步骤 a中对解 交织地址初始化时， 还对列值初始化；
步骤 b中如果完成解交织矩阵一列数据的写操作， 进一步包括： 将列值 加 1 , 根据列值对应列间置换规则计算解交织矩阵下一列的解交织地址。
9、 根据权利要求 6或 8所述的第二次解交织方法， 其中， 所述列间置换 规则为： 3GPP规定的 30列矩阵的列间置换规则。
10、 一种第二次解交织装置， 该装置包括： 解交织数据写入模块、 解交 织存储模块、 解交织列末判断模块、 解交织列间转换模块和解交织数据读取 模块， 其中，
所述解交织数据写入模块用于从所述第二次解交织装置外部接收数据； 还用于根据来自所述解交织列末判断模块的列中信号计算该列下一个解交织 地址； 还用于接收所述解交织列间转换模块发来的解交织地址， 并将解交织 地址和数据发送给所述解交织存储模块；
所述解交织存储模块用于接收所述解交织数据写入模块发来的解交织地 址和数据， 根据所述解交织数据写入模块发来的解交织地址存储数据； 还用 于接收所述解交织数据读取模块发来的解交织地址， 将与所述解交织数据读 取模块发来的解交织地址对应的数据发送给所述解交织数据读取模块；
所述解交织列末判断模块用于判断所述解交织数据写入模块接收到的解 交织地址是否为列末地址， 不为列末地址时向所述解交织数据写入模块发送 列中信号， 为列末地址时向所述解交织列间转换模块发送列末信号；
所述解交织列间转换模块用于根据列间置换规则和来自所述解交织列末 判断模块的列末信号计算下一列的解交织地址， 并将该解交织地址发送给所 述解交织数据写入模块；
所述解交织数据读取模块用于根据数据发送顺序依次生成解交织地址， 并将生成的解交织地址发送给所述解交织存储模块， 根据自身发送给所述解 交织存储模块的解交织地址逐个从所述解交织存储模块读取数据， 并将该数 据从所述第二次解交织装置发送出去。
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