WO2009142165A1 - Dispositif à semi-conducteur et procédé de fabrication associé - Google Patents

Dispositif à semi-conducteur et procédé de fabrication associé Download PDF

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Publication number
WO2009142165A1
WO2009142165A1 PCT/JP2009/059113 JP2009059113W WO2009142165A1 WO 2009142165 A1 WO2009142165 A1 WO 2009142165A1 JP 2009059113 W JP2009059113 W JP 2009059113W WO 2009142165 A1 WO2009142165 A1 WO 2009142165A1
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Prior art keywords
variable resistor
layer
semiconductor device
diffusion layer
metal
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PCT/JP2009/059113
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English (en)
Japanese (ja)
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潤 砂村
仁彦 伊藤
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日本電気株式会社
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Priority to JP2010513007A priority Critical patent/JPWO2009142165A1/ja
Publication of WO2009142165A1 publication Critical patent/WO2009142165A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device having a resistance change element and a manufacturing method thereof.
  • nonvolatile memories As rewritable semiconductor memory devices, the demand for nonvolatile memories as rewritable semiconductor memory devices has increased.
  • flash memories which are typical examples of nonvolatile memories, those using floating gates are the mainstream, but it is said that it is difficult to reduce the thickness of the tunnel gate oxide film, and miniaturization is approaching the limit. It is said that.
  • a memory using a resistance variable element has been proposed as a nonvolatile memory exceeding the limit of miniaturization of a flash memory.
  • This memory is expected not only as a non-volatile memory but also as a general-purpose memory that operates at high speed.
  • Memory using resistance change elements includes magnetic RAM (MRAM), phase change RAM (PRAM), resistive RAM (ReRAM), and programmable metallization cell (PMC). Each of these has a unique rewrite condition, resistance change rate, and number of rewrites, but those having a high resistance change rate defined by the resistance ratio between the low resistance state and the high resistance state are ReRAM and PMC. A higher read margin can be expected.
  • MRAM magnetic RAM
  • PRAM phase change RAM
  • ReRAM resistive RAM
  • PMC programmable metallization cell
  • ReRAM and PMC are usually provided on a semiconductor integrated circuit together with a transistor.
  • Patent Document 1 Japanese Patent Laid-Open No. 2004-363604
  • FIG. 24 a MOS transistor 200 including a gate insulating film 230, a gate electrode, a source 210, and a drain 220 on a silicon substrate 191
  • a nonvolatile memory 190 is described in which a variable resistance element 300 including two electrodes 310 and 330 and a variable resistor 320 is formed.
  • the lower electrode 310 of the resistance change element 300 is connected to the drain 220 of the MOS transistor 200
  • the upper electrode 330 of the resistance change element 300 is connected to the wiring 400 on the upper layer side.
  • a voltage is applied to the variable resistance 320 through the MOS transistor 200.
  • the variable resistor 320 a transition metal oxide is used.
  • Patent Document 2 Japanese Patent Laid-Open No. 2006-279042 discloses a lower electrode plug that extends vertically, a variable resistance film that is horizontally disposed so as to cover the upper surface of the lower electrode plug, and the variable resistance film.
  • a variable resistance element including an upper electrode disposed on a resistance film is described.
  • a memory including a plurality of memory cells including the variable resistance element and the transistor is described. In this memory, the gate electrode of each transistor forms a word line, and the lower electrode of each variable resistance element has a corresponding transistor. It is described that a drain is connected and a bit line is connected to an upper electrode of each resistance change element.
  • the inventors of the present invention have clarified the following problems as a result of repeated studies on improving the performance of a semiconductor memory device, particularly ReRAM using a transition metal oxide as a variable resistor.
  • the lower electrode 310 of the resistance change element 300 is connected to the drain 220 of the MOS transistor 200, and the variable resistor 320 is connected to the lower electrode 310. Is connected. Therefore, on the current path from the drain 220 of the MOS transistor 200 to the variable resistor 320, which is generated when a voltage is applied to the variable resistor 320, the junction interface between the drain 220 and the lower electrode 310, and the lower electrode 310 There is a junction interface of the variable resistor 320. An increase in contact resistance due to such a two-junction interface is inevitable.
  • the current flowing to the variable resistor 32 must pass through the distance corresponding to the thickness of the lower electrode 310.
  • the diameter of vias that electrically connect different wiring layers has become on the order of several tens of nanometers. The voltage drop due to parasitic resistance cannot be ignored.
  • variable resistor 320 Furthermore, a high frequency voltage in the order of GHz may be applied to the variable resistor 320, and in such a case, transmission loss due to the high frequency becomes significant.
  • an object of the present invention is to overcome the problems of such a semiconductor device, to reduce the parasitic resistance between the variable resistor of the variable resistance element and the diffusion layer of the field effect transistor, and to perform writing and reading performance with respect to the variable resistive element. It is an object of the present invention to provide a semiconductor device in which deterioration of the semiconductor is suppressed and a manufacturing method thereof.
  • a semiconductor device including a field effect transistor having a diffusion layer and a variable resistance element having a variable resistance layer, The variable resistor layer provided on the diffusion layer; Vias provided on the variable resistor layer; A semiconductor device having a wiring layer connected to the via is provided.
  • a semiconductor device having a field effect transistor having a diffusion layer, a variable resistor layer provided on the diffusion layer, and a via provided on the variable resistor layer.
  • a manufacturing method comprising: Forming a metal layer made of the same metal element as the metal element contained in the variable resistor layer on the diffusion layer; The metal layer is reformed into the variable resistor layer by heating at a temperature of 150 ° C. or more and 600 ° C. or less in an atmosphere containing a gas component containing the same nonmetal element as the nonmetal element contained in the variable resistor layer.
  • a method for manufacturing a semiconductor device is provided.
  • the present invention it is possible to provide a semiconductor device in which parasitic resistance between a variable resistor of a resistance change element and a diffusion layer of a field effect transistor is reduced, and deterioration of writing and reading performance with respect to the variable resistance element is suppressed. Can do.
  • FIG. 2B is a plan view of the configuration shown in FIG. 2A. It is a figure which shows the part of the resistance change element of a structure shown to FIG. 2A. It is a figure which shows the part of the resistance change element of a structure shown to FIG. 2A.
  • FIG. 1A is a diagram showing an example of a configuration of a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device according to the first embodiment of the present invention includes a field effect transistor 110 including a diffusion layer region 118, a variable resistor 131 provided in contact with the diffusion layer region 118, and , Vias 140 and wirings 150.
  • the via 140 is formed in the interlayer insulating film 138, and one end (lower end) of the via is connected to the surface (upper surface) opposite to the diffusion layer region 118 side of the variable resistor 131, and the other end ( A wiring 150 is connected to the upper end.
  • a resistance change element is formed in which the lower end surface of the via 140 (upper electrode) is disposed to face the diffusion layer region 118 (lower electrode) via the variable resistor 131.
  • variable resistor 131 and the via 140 may be connected between the variable resistor 131 and the via 140 via a thin metal layer 1310 such as a barrier metal.
  • the parasitic resistance between the variable resistor 131 of the variable resistance element and the diffusion layer region 118 of the field effect transistor 110 is reduced, and deterioration of writing and reading performance with respect to the variable resistance element is suppressed. be able to.
  • a layer, a via, and a wiring including a variable resistor may be formed in this order on the substrate, a via (lower electrode), a variable resistor, and a via are formed on the substrate as in the technique described in FIG.
  • the manufacturing process can be simplified as compared with the case where the (upper electrode) and the wiring are formed in this order.
  • variable resistor 131 is generally a material having a dielectric constant larger than that of the interlayer insulating film. However, since the variable resistor 131 can be separated from the wiring 150, the wiring 150 and the adjacent wiring are more effective than the technique shown in FIG. The influence of the variable resistor on the parasitic capacitance between the two can be reduced.
  • the film thickness of the variable resistor 131 is preferably about 1 nanometer to 200 nanometers.
  • a gate insulating film 112 on a semiconductor substrate 111, a gate electrode 113 provided on the gate insulating film 112, and a semiconductor substrate on both sides of the gate electrode 113 are formed.
  • An MIS transistor including the provided diffusion layer regions 117 and 118 can be used.
  • the semiconductor substrate a substrate having a semiconductor layer on at least the surface can be used.
  • a side wall 116 made of an insulator can be provided on the side surface of the gate electrode 113.
  • variable resistor 131 may be configured to extend from the contact portion between the variable resistor 131 and the diffusion layer region 118 onto the side wall 116.
  • the diffusion layer region 118 (lower electrode), the variable resistor 131, and the via 140 (upper electrode) constitute a resistance change element 130.
  • one diffusion layer region (here, diffusion layer region 118) is shared (so as to be sandwiched) among diffusion layer regions 117 and 118 provided on both sides of gate electrode 113.
  • a structure 127 is provided on the opposite side of the gate electrode 113, and a side wall 116 made of an insulator is provided on a side surface of the structure 127 so as to face the side wall 116 of the gate electrode 113, and the variable resistor 131 is variable.
  • a configuration may be adopted in which the resistor 131 and the diffusion layer region 118 extend from the contact portion onto the side wall 116 of the structure 127.
  • the structure 127 may have a height that allows the variable resistor 131 to sufficiently extend, and may be a conductor or an insulator. Considering the process, a structure made of the same material as the gate electrode 113 and having the same size is preferable. A gate electrode or a dummy gate electrode in a cell unrelated to the cell including the gate electrode 113 is preferable.
  • FIG. 2B shows a plan view (viewed from the upper surface side) of the structure shown in FIG. 2A.
  • the gate electrode 113 and the structure 127 are preferably extended to the outside of the diffusion layer region 118 along the gate width direction (vertical direction in the drawing).
  • the variable resistor 131 can be formed in the dotted line part of FIG. 2B. That is, the outer peripheral end portion of the variable resistor 131 is disposed outside the periphery of the side surface of the via 140.
  • the end in the gate width direction can be disposed outside the side surface of the via 140 with a margin.
  • the semiconductor substrate 111 a silicon substrate, a silicon-on-insulator (SOI) substrate, or the like can be used.
  • SOI silicon-on-insulator
  • the gate insulating film 112 when a silicon substrate is used, a silicon oxide film formed by thermally oxidizing the substrate surface, a silicon oxynitride film or a high dielectric constant insulating film to which a small amount of nitrogen is added, or a film of these films is used. A laminated film containing at least one kind may be used.
  • the thickness of the gate insulating film 112 is preferably 0.8 nanometers or more and 3 nanometers or less in terms of oxide film thickness.
  • the gate electrode 113 is preferably polysilicon formed of monosilane gas, metal or metal silicide formed by sputtering, or a combination thereof.
  • the thickness of the gate electrode can be set to 50 nanometers or more. Further, the gate length (left-right direction in the plane of FIG. 1A: horizontal direction) can typically be set to 100 nanometers or less.
  • the sidewall 116 is preferably a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a laminated film containing at least two of these, and the film thickness is preferably 5 nm or more and 100 nm or less.
  • the end of the variable resistor 131 in the gate length direction can be extended to the upper part of the gate electrode 113 and the upper part of the structure 127.
  • an insulating film 114 is provided on the gate electrode 113 in order to maintain insulation between the variable resistor 131 and the gate electrode 113.
  • the insulating film 114 is preferably a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like.
  • the film thickness may be any thickness that can ensure sufficient insulation, and can be set to 20 nanometers, for example.
  • variable resistance element 130 having the configuration shown in FIG. 2A.
  • the effect of this embodiment is demonstrated using FIG. 4 based on FIG.
  • the region where the switching operation occurs is considered to be a region where the electric field is more likely to be applied to the variable resistor 131. That is, it is a region where the variable resistor 131 between the two electrodes is the thinnest, for example, a region where the corner of the electrode exists.
  • the switching operation in the variable resistance element shown in FIG. 4 occurs in a region near the diffusion layer region 118 of the variable resistor 131. That is, it is sandwiched between the interface where the variable resistor 131 and the diffusion layer region 118 (lower electrode) are in contact and the interface where the variable resistor 131 and the bottom portion (132) of the via 140 are in contact, which are indicated by thick solid lines in FIG. A switching operation will occur in this area.
  • the variable resistor can have a shape other than the shape of the variable resistor 131 shown in FIG. 3, and may have the following shape, for example.
  • the variable resistor 131 may have a shape that does not overlap with the insulating film 114 on the gate electrode 113.
  • the variable resistor 131 may have a tapered end portion.
  • the end of the variable resistor 131 may be connected to the outer peripheral surface of the via 140 in a straight line.
  • the variable resistor 131 may have tapered ends, and the size between the ends may be about the diameter of the via.
  • a metal silicide layer 120 may be provided at a contact portion of the diffusion layer region 118 with the variable resistor 131.
  • the resistance between the diffusion layer region 118 and the via 140 can be reduced. For this reason, high-speed operation can be achieved.
  • a silicide layer 119 of the same metal element as the metal element included in the variable resistor 131 can be provided at the contact portion of the diffusion layer region 117 with the via 140.
  • extension regions 115 electrically connected to the diffusion layer regions 117 and 118 can be provided in the semiconductor region below the side wall 116. With this structure, the short channel effect between the diffusion layer regions 117 and 118 can be suppressed, so that the semiconductor device can be miniaturized.
  • the semiconductor device of this embodiment may have a configuration in which both the metal silicide layer 120 and the extension region 115 are provided.
  • the variable resistor 131 can be formed of a material selected from a compound of one or more elements selected from the group consisting of oxygen, nitrogen, selenium, and tellurium and a metal.
  • this metal transition metals such as Cr, Ti, V, Ni, Cu, Zr, Nb, Mo, Hf, Ta, and W can be used.
  • a metal selected from the group consisting of Ti, Ni, Mo, Hf, Ta, and W is preferable, and Ni or Ti is more preferable. That is, the variable resistor 131 is selected from the group consisting of a metal selected from Cr, Ti, V, Ni, Cu, Zr, Nb, Mo, Hf, Ta, and W, and oxygen, nitrogen, selenium, and tellurium.
  • the variable resistor 131 can be formed of an oxide of a metal selected from Cr, Ti, V, Ni, Cu, Zr, Nb, Mo, Hf, Ta, and W, and includes Ti, Ni, Mo, and Hf.
  • variable resistor 131 can be used which changes between a first state and a second state having a lower electrical resistance than the first state in accordance with the application of a voltage. .
  • the operation of this variable resistor will be described below using the example of Patent Document 1 shown in FIG.
  • the semiconductor memory device 190 shown in FIG. 24 has the following configuration.
  • MOS type including impurity diffusion layers 210 and 220 to be source and drain electrodes, a gate insulating film 230 made of a silicon oxide film, and a gate electrode 240 made of polysilicon on the gate insulating film 230 on a semiconductor substrate (silicon substrate) 191
  • a transistor 200, two electrodes 310 and 330, and a variable resistor 320 are formed.
  • One electrode 310 of the resistance change element 300 is connected to the drain 220 of the MOS transistor 200, and the other electrode 330 of the resistance change element 300 is connected to the wiring 400 on the upper layer side.
  • a switching operation of the resistance change element 300 using a unipolar voltage in the semiconductor memory device 190 shown in FIG. 24 will be described with reference to FIG.
  • the voltage applied between the two electrodes 310 and 330 of the resistance change element 300 is denoted as Vsw.
  • the semiconductor memory device 190 in order to apply a desired voltage Vsw to the resistance change element 300, a voltage higher than Vsw is applied between the source 210 and the upper layer wiring 400, and the transistor 200 is turned on to the gate electrode 240. A voltage equal to or higher than the threshold voltage is applied.
  • the relationship between the voltage Vsw applied to the resistance change element 300 and the current flowing through the resistance change element 300 is the relationship shown in FIG.
  • the variable resistance element 300 is in the low resistance state (that is, the set state)
  • the voltage-current characteristic A in FIG. 25 is shown with respect to the applied voltage Vsw. In the region where Vsw is low, a large amount of current flows because of the low resistance state.
  • both the high resistance state and the low resistance state are stable in the region of Vsw ⁇ V1, but the high resistance state is stable in the region of V1 ⁇ Vsw ⁇ V2, and the low resistance state is in the region of Vsw> V2. Is stable.
  • the reset operation (operation for setting the reset state) is performed under the condition of V1 ⁇ Vsw ⁇ V2, and the set operation (operation for setting the set state) is Vsw> V2. It is said that it is good to do in the condition of.
  • the set operation is performed by applying a set voltage from 1 nanosecond to 100 nanoseconds under the condition of Vsw> V2, and the reset operation is performed with a reset voltage of 1 micrometer under the condition of V1 ⁇ Vsw ⁇ V2. It is described that it can be performed by applying from 100 to 100 microseconds.
  • variable resistor whose electrical resistance changes to three or more different values depending on the application of voltage.
  • FIG. 12 shows an example of the configuration of the semiconductor device according to the second embodiment of the present invention.
  • the semiconductor device according to the present embodiment includes, as another example of the field effect transistor 110, a vertical transistor in which a source and a drain are arranged in a direction perpendicular to the substrate plane.
  • This vertical transistor includes a semiconductor column protruding from the surface of the substrate 111, a lower diffusion layer region provided on the substrate 111, an upper diffusion layer region provided above the column, and side surfaces of the column. It includes a gate electrode 113 provided above, and a gate insulating film (not shown) interposed between the column portion and the gate electrode 113.
  • the lower diffusion layer region has an extending portion extending in the substrate plane direction, and the variable resistor 131 of the variable resistance element is provided in contact with the extending portion. It is preferable that a silicide layer of the same metal element as the metal element included in the variable resistor is interposed between the variable resistor 131 and the extended portion of the lower diffusion layer region.
  • FIG. 13 is an explanatory diagram of the manufacturing method of the present embodiment.
  • a hole reaching the diffusion layer region 118 of the field effect transistor 110 is formed in the interlayer insulating film 138, and a metal film 135 made of a transition metal is formed at least at the bottom of the hole.
  • heating is performed at a temperature of 150 ° C. to 600 ° C. in an atmosphere containing oxygen.
  • the transition metal the same metal element as the metal element constituting the variable resistor can be used, and is selected from the group consisting of Ti, Ni, Mo, Hf, Ta, and W from the viewpoint of satisfactorily forming the silicide layer. It is preferable to use a metal such as Ni or Ti.
  • the silicide layer 120 can be formed on the diffusion layer region 118 at the bottom of the hole, and the variable resistor can be formed on the silicide layer.
  • the transition metal film 135 is formed on the side wall 116 from the region in contact with the diffusion layer region 118 of the field effect transistor 110. You may form so that it may extend.
  • the oxidation rate can be controlled by controlling the oxygen concentration in the atmosphere from a very small concentration to a concentration mainly composed of oxygen.
  • the atmosphere containing oxygen as a main component means an atmosphere containing oxygen in an amount of approximately 50% by volume (standard state) or more.
  • Said heat processing can be performed in the atmosphere containing the gas component containing the same nonmetallic element as the nonmetallic element contained in a variable resistor. Specifically, it can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of this element and a metal such as Ni.
  • the gas component containing an oxygen element is an oxidizing gas (eg, O 2 or N 2 O)
  • the gas component containing a nitrogen element is a nitriding gas (eg, N 2 )
  • the gas component containing a sulfur element is a sulfide gas (
  • H 2 S) a gas component containing a selenium element, a gas capable of forming a metal selenide (eg, H 2 Se), and a gas component containing a tellurium element, such as a gas capable of forming a metal telluride (eg, H 2 S). 2 Te)
  • oxidizing gas eg, O 2 or N 2 O
  • the gas component containing a nitrogen element is a nitriding gas (eg, N 2 )
  • the gas component containing a sulfur element is a sulfide gas (
  • H 2 S a gas component containing a selenium element, a gas capable of forming a metal selenide (eg,
  • the MIS transistor 110 is formed by a normal method.
  • the silicon substrate 111 is thermally oxidized to form a gate insulating film 112 made of a silicon oxide film.
  • a gate insulating film As the gate insulating film, a high dielectric constant insulating film having a higher dielectric constant or a laminated film of a silicon oxide film and a high dielectric constant insulating film may be used instead of the silicon oxide film.
  • a polysilicon film 113 is formed on the gate insulating film 112 by monosilane gas. Subsequently, a silicon nitride film 114 is formed on the polysilicon film by sputtering.
  • a photoresist is formed on the silicon nitride film 114 in order to process the silicon oxide film 112, the polysilicon 113, and the silicon nitride film 114 sequentially formed on the silicon substrate 111.
  • a photoresist having a predetermined gate pattern is formed by exposing the photoresist by optical exposure using a normal optical mask and developing the photoresist.
  • the gate insulating film 112, the polysilicon film 113, and the silicon nitride film 114 on the silicon substrate 111 are processed by etching using the gate-patterned photoresist as a mask.
  • the gate insulating film 112 formed on the silicon substrate 111, the gate electrode 113 formed on the silicon substrate 111 via the gate insulating film 112, and the insulating film 114 formed on the gate electrode 113 are formed.
  • a laminated structure having a gate pattern shape is obtained.
  • the first impurity diffusion layer 117 and the second impurity diffusion layer 118 are formed in the silicon substrate 111 by performing ion implantation on the silicon substrate 111.
  • a silicon oxide film is formed to cover the gate pattern laminated structure, and the entire surface is etched back to form sidewalls 116 on the side surfaces of the laminated structure.
  • FIG. 14A shows a partial cross section at this stage.
  • a stacked structure including the gate insulating film 112, the gate electrode 113, and the insulating film 114 is drawn integrally.
  • another stacked structure is formed so as to face the stacked structure with the impurity diffusion layer 118 interposed therebetween, and a side wall 116 is formed on the side surface of the stacked structure.
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 14B), and this Ni film 135 is formed in an oxygen atmosphere (O 2 content: 100 vol%). It is modified to the variable resistor 131 by heating in the inside (FIG. 14C).
  • the heat treatment can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of the element and a metal such as Ni.
  • the heating temperature can be set in the range of 150 ° C to 600 ° C.
  • a metal such as Ni and one or more elements selected from oxygen, nitrogen, sulfur, selenium, and tellurium.
  • a compound composed of a metal and oxygen as a typical example may be directly deposited by sputtering, laser ablation, chemical vapor deposition, or the like. According to this method, the structure shown in FIG. 14C can be formed directly from the structure shown in FIG.
  • variable resistor 131 is formed on the variable resistor 131.
  • a photoresist 136 having a predetermined pattern is formed by exposing the photoresist 136 by optical exposure using a normal optical mask and performing development processing (FIG. 14D).
  • the variable resistor 131 is etched using the photoresist 136 as a mask. Etching can be dry etching or wet etching.
  • the variable resistor 131 is disposed only in a predetermined region including the impurity diffusion layer 118 (FIGS. 14E and 2B).
  • an interlayer insulating film 138 made of a silicon nitride film or a silicon oxide film is formed on the MIS transistor 110 and the variable resistor 131, and planarized by a chemical mechanical polishing (CMP) method or the like (FIG. 14). (F)).
  • the thickness of the interlayer insulating film can be generally set to 50 nanometers to 400 nanometers.
  • a photoresist is formed over the interlayer insulating film 138, a resist pattern is formed by a lithography technique, and etching is performed using this pattern as a mask to form a via hole 139 (FIG. 14G).
  • a titanium nitride film is formed as a barrier metal film, and then filled with tungsten, thereby forming a via 140 (FIG. 14H). Removal of unnecessary titanium nitride and tungsten outside the via hole 139 can be performed using a chemical mechanical polishing (CMP) method. Thereafter, a first wiring layer 150 is formed on the interlayer insulating film 138 according to a normal method, whereby the semiconductor device 110 shown in FIG. 2A is obtained.
  • CMP chemical mechanical polishing
  • the Ni film 135 is modified into the variable resistor 131 and then processed into a predetermined shape. However, in the first modification, the Ni film 135 is processed into a predetermined shape and then applied to the variable resistor 131. Perform reforming.
  • MIS transistor 110 is formed on silicon substrate 111 by the same method as in Example 1 (FIG. 15A).
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 15B).
  • a photoresist 136 is formed on the Ni film 135 in order to process the Ni film 135.
  • a photoresist 136 having a predetermined pattern is formed by exposing the photoresist 136 by optical exposure using a normal optical mask and performing development (FIG. 15C).
  • the Ni film 135 is etched using the photoresist 136 as a mask.
  • the Ni film 135 is disposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 15D).
  • the Ni film 135 is modified into the variable resistor 131 by heating in an oxygen atmosphere (O 2 content: 100 vol%) (FIG. 15E).
  • This heat treatment can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of this element and a metal such as Ni.
  • Example 2 Thereafter, in the same manner as in Example 1, the interlayer insulating film 138 and the via 140 are formed (FIGS. 15F to 5H), and the semiconductor device 110 shown in FIG. 2A is obtained.
  • a predetermined region of the Ni film 135 is modified into the variable resistor 131 and then processed into a predetermined shape.
  • MIS transistor 110 is formed on silicon substrate 111 by the same method as in Example 1 (FIG. 16A).
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 16B).
  • a silicon oxide film having a thickness of 100 nm is formed as a reaction preventing film 137 (antioxidation film) for modifying only a predetermined region of the Ni film 135 into the variable resistor 131.
  • the reaction preventing film is preferably made of a material that does not change when the variable resistor 131 is formed.
  • an insulating film such as a silicon nitride film can be used. A film thickness of 10 nanometers or more and 300 nanometers or less is sufficient, but any film thickness may be used as long as the Ni film 135 can be removed without being modified or removed.
  • a photoresist is formed on the reaction preventing film 137.
  • a photoresist having a predetermined pattern is formed by exposing the photoresist by optical exposure using a normal optical mask and developing the photoresist.
  • the reaction preventing film 137 is etched using this photoresist as a mask. As a result, the Ni film 135 is exposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 16C).
  • the Ni film 135 is heated in an oxygen atmosphere (O 2 content: 100% by volume), so that only the exposed portion of the Ni film 135 is modified into the variable resistor 131 (FIG. 16D).
  • This heat treatment can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of this element and a metal such as Ni.
  • variable resistor 131 is disposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 16E).
  • Example 2 Thereafter, in the same manner as in Example 1, the interlayer insulating film 138 and the via 140 are formed (FIGS. 16F to 6H), and the semiconductor device 110 shown in FIG. 2A is obtained.
  • the third modification is an example of manufacturing a semiconductor device having the structure shown in FIG.
  • MIS transistor 110 is formed on silicon substrate 111 by the same method as in Example 1 (FIG. 17A).
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 17B), and this Ni film 135 is formed in an oxygen atmosphere (O 2 content: 100 volume%). It is modified to the variable resistor 131 by heating in the inside (FIG. 17C).
  • This heat treatment can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of this element and a metal such as Ni.
  • a photoresist 136 is formed on the Ni film 135 in order to process the Ni film 135.
  • the patterned photoresist 136 is provided up to the gate electrode (FIG. 14D), but in this modification, the photoresist is provided up to the side wall as follows and not provided on the gate electrode (FIG. 14). 17 (D)).
  • a photoresist 136 having a predetermined pattern is formed by exposing the photoresist 136 by optical exposure using a normal optical mask and performing development processing (FIG. 17D).
  • the Ni film 135 is etched using the photoresist 136 as a mask.
  • the variable resistor 131 is disposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 17E).
  • the interlayer insulating film 138 and the via 140 are formed (FIGS. 17F to 17H), and the semiconductor device having the structure shown in FIG. 8 is obtained. Also in this structure, the effect described with reference to FIG. 4 is obtained, the problems in the techniques described in Patent Document 1 and Patent Document 2 are solved, and the high-speed operation and stable operation of the semiconductor memory device having the resistance change element are achieved. Repeat resistance can be realized.
  • the fourth modification is another example of manufacturing a semiconductor device having the structure shown in FIG.
  • MIS transistor 110 is formed on silicon substrate 111 by the same method as in Example 1 (FIG. 18A).
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 18B).
  • a silicon oxide film is formed to a thickness of 100 nanometers.
  • the film thickness is not particularly limited as long as the Ni film 135 can be removed without being modified or removed.
  • the processed reaction preventing film 137 is formed so as not to be applied on the side wall 116 (FIG. 16C), but in this modified example, on the side wall 116 as follows. (FIG. 18C).
  • a photoresist is formed on the reaction preventing film 137.
  • a photoresist having a predetermined pattern is formed by exposing the photoresist by optical exposure using a normal optical mask and developing the photoresist.
  • the mask used for forming the via hole described with reference to FIG. 14G can be directly applied to the optical mask. As a result, the number of masks necessary for manufacturing the variable resistance element 130 can be reduced, and the manufacturing cost of the semiconductor memory device can be suppressed.
  • reaction preventing film 137 is etched using this photoresist pattern as a mask.
  • the Ni film 135 is exposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 18C).
  • the Ni film 135 is heated in an oxygen atmosphere (O 2 content: 100% by volume), so that only the exposed portion of the Ni film 135 is modified into the variable resistor 131 (FIG. 18D).
  • This heat treatment can be performed in an atmosphere containing an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium, and a gas component that forms a compound of this element and a metal such as Ni.
  • variable resistor 131 is disposed only in a predetermined region including the impurity diffusion layer 118 (FIG. 18E).
  • Example 2 Thereafter, in the same manner as in Example 1, the interlayer insulating film 138 and the via 140 are formed (FIGS. 18F to 18H), and the semiconductor device having the structure shown in FIG. 8 is obtained.
  • the semiconductor device of the first embodiment and the first to fourth modified examples of the first embodiment manufactured by the above method can be rewritten at a high speed of a semiconductor device having a resistance change element by reducing parasitic resistance and parasitic capacitance components.
  • a read operation can be realized.
  • the number of possible repeated operations can be increased by about two digits.
  • Example 2 is a manufacturing example of a semiconductor device having the structure shown in FIG. 9, that is, the structure in which the metal silicide 120 is provided in the contact portion of the diffusion layer 118 with the variable resistor 131.
  • a description will be given with reference to FIGS. 19 and 20.
  • MIS transistor 110 is formed on silicon substrate 111 by the same method as in Example 1 (FIG. 19A).
  • a Ni film 135 for forming the variable resistor 131 is formed on the MIS transistor 110 (FIG. 19B).
  • this Ni film 135 By heating this Ni film 135 at a temperature of 150 ° C. or higher and 600 ° C. or lower in an atmosphere containing oxygen as a main component, silicidation of the surface of the diffusion layer 118 and modification of the Ni film 135 can be performed simultaneously ( FIG. 19 (C)). Thereafter, similarly to the steps described with reference to FIGS. 14D to 14H in Embodiment 1, the steps of FIGS. 19D to 19H are performed, and the semiconductor device shown in FIG. can get.
  • the modification of the metal film 135 provided on the diffusion layer 118 to the variable resistor 131 and the silicidation of the surface of the diffusion layer 118 can be performed by three methods as shown in FIG.
  • the surface of the diffusion layer 118 is first silicided to form the silicide 120, and then the remaining metal film 135 is modified to form the variable resistor 131. It is.
  • the metal film 135 is first modified to form the variable resistor 131, and then the surface of the diffusion layer 118 is silicided with the remaining metal film 135. Is what you do.
  • the silicidation and the modification of the metal film can be selectively performed by controlling the heating atmosphere during silicidation and the atmosphere during the modification of the metal film 135. More specifically, for silicidation of the diffusion layer 118, it is effective to heat in an inert gas such as nitrogen (N 2 ) gas.
  • the heating temperature depends on the type of metal film 135 used, but is generally 150 ° C. or higher.
  • the metal film 135 is reformed by heating in a gas atmosphere containing a gas component containing the same element as the element constituting the variable resistor 131.
  • the variable resistor 131 include a compound composed of a metal and one or more selected from oxygen, nitrogen, sulfur, selenium, and tellurium.
  • variable resistor 131 includes the gas component that forms the metal film 135 including an element selected from oxygen, nitrogen, sulfur, selenium, and tellurium and forms a compound of this element and the metal of the metal film 135. It can carry out by heating in the atmosphere to do.
  • the heating temperature depends on the type of metal film 135 used, but can be set to 150 ° C. or higher.
  • the third method is a method of simultaneously siliciding the surface of the diffusion layer 118 and modifying the metal film 135 after the metal film 135 is formed.
  • the manufacturing cost can be reduced by performing the heating process once.
  • a Ni film 135 having a thickness of 42 nanometers is formed on a silicon film having a thickness of 50 nanometers formed on the silicon oxide film, and is 450 ° C. in an oxygen atmosphere (O 2 content: 100% by volume).
  • O 2 content 100% by volume
  • NiO to be a variable resistance film 131 is formed on the surface side, NiSi to be a silicide electrode is formed below the NiO, and there are almost no regions where Si and O exist simultaneously. Absent. From this result, it can be said that NiSiO is not formed in the surface region, and a laminated structure of NiO and NiSi is formed. The effectiveness of this method could be confirmed when any of Ti, Mo, Hf, Ta, and W was used instead of the Ni film.
  • 22 (A) to 22 (H) are diagrams showing a manufacturing method according to a modification of the second embodiment.
  • the modification of the Ni film 135 and the silicidation of the surface of the diffusion layer 118 are simultaneously performed in the second modification of the first embodiment (FIG. 22D).
  • 22A to 22H correspond to FIGS. 16A to 16H, respectively, except that the silicide layer 120 is formed in FIG. 22D.
  • FIGS. 22 (A) to 22 (H) correspond to FIGS. 22 (A) to 22 (H), respectively.
  • the reaction preventing film 137 is formed so as to cover the Ni film 135 on the diffusion layer 117, and the Ni film 135 is not exposed during the reforming process.
  • the silicide layer 119 is formed by the modification process, but the Ni film 135 is not modified.
  • the unmodified Ni film 135 is completely removed in a later etching process (FIG. 23E).
  • the semiconductor device of the second embodiment manufactured by the above method can realize high-speed rewriting and reading operations of a semiconductor device having a resistance change element by reducing parasitic resistance and parasitic capacitance components.
  • the number of possible repeated operations can be increased by about two digits.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteur qui comprend un transistor à effet de champ qui comprend une couche de diffusion et un élément de changement de résistance qui comprend une couche de résistance variable. Le dispositif à semi-conducteur comprend la couche de résistance variable prévue sur la couche de diffusion, un trou d’interconnexion prévu sur la couche de résistance variable, et une couche de câblage connectée au trou d’interconnexion.
PCT/JP2009/059113 2008-05-20 2009-05-18 Dispositif à semi-conducteur et procédé de fabrication associé WO2009142165A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010251529A (ja) * 2009-04-16 2010-11-04 Sony Corp 半導体記憶装置およびその製造方法
CN102693985A (zh) * 2011-03-25 2012-09-26 北京兆易创新科技有限公司 一种可编程存储器及其制造方法

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JP2004319587A (ja) * 2003-04-11 2004-11-11 Sharp Corp メモリセル、メモリ装置及びメモリセル製造方法
JP2004363604A (ja) * 2003-06-03 2004-12-24 Samsung Electronics Co Ltd 一つのスイッチング素子と一つの抵抗体とを含む不揮発性メモリ装置およびその製造方法
JP2006286726A (ja) * 2005-03-31 2006-10-19 Toshiba Corp スピン注入ｆｅｔ
WO2007004843A1 (fr) * 2005-07-04 2007-01-11 Industry-University Cooperation Foundation Hanyang University Procede de formation de film d'oxyde binaire multicouche pour memoire ram a resistance
WO2007023569A1 (fr) * 2005-08-26 2007-03-01 Fujitsu Limited Dispositif d’enregistrement semi-conducteur non volatile et son procédé d’écriture
JP2007109875A (ja) * 2005-10-13 2007-04-26 Matsushita Electric Ind Co Ltd 記憶素子，メモリ装置，半導体集積回路
JP2007243183A (ja) * 2006-03-10 2007-09-20 Samsung Electronics Co Ltd 抵抗性メモリ素子
WO2007138646A1 (fr) * 2006-05-25 2007-12-06 Hitachi, Ltd. Élément de mémoire non volatile, son procédé de fabrication et dispositif à semi-conducteurs l'utilisant
JP2008065953A (ja) * 2006-09-11 2008-03-21 Fujitsu Ltd 不揮発性半導体記憶装置及びその読み出し方法
JP2008085204A (ja) * 2006-09-28 2008-04-10 Toshiba Corp 半導体記憶装置及びその製造方法
JP2009016845A (ja) * 2007-07-04 2009-01-22 Dongbu Hitek Co Ltd 半導体素子及びその製造方法

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Publication number Priority date Publication date Assignee Title
JPH0621467A (ja) * 1992-07-03 1994-01-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004319587A (ja) * 2003-04-11 2004-11-11 Sharp Corp メモリセル、メモリ装置及びメモリセル製造方法
JP2004363604A (ja) * 2003-06-03 2004-12-24 Samsung Electronics Co Ltd 一つのスイッチング素子と一つの抵抗体とを含む不揮発性メモリ装置およびその製造方法
JP2006286726A (ja) * 2005-03-31 2006-10-19 Toshiba Corp スピン注入ｆｅｔ
WO2007004843A1 (fr) * 2005-07-04 2007-01-11 Industry-University Cooperation Foundation Hanyang University Procede de formation de film d'oxyde binaire multicouche pour memoire ram a resistance
WO2007023569A1 (fr) * 2005-08-26 2007-03-01 Fujitsu Limited Dispositif d’enregistrement semi-conducteur non volatile et son procédé d’écriture
JP2007109875A (ja) * 2005-10-13 2007-04-26 Matsushita Electric Ind Co Ltd 記憶素子，メモリ装置，半導体集積回路
JP2007243183A (ja) * 2006-03-10 2007-09-20 Samsung Electronics Co Ltd 抵抗性メモリ素子
WO2007138646A1 (fr) * 2006-05-25 2007-12-06 Hitachi, Ltd. Élément de mémoire non volatile, son procédé de fabrication et dispositif à semi-conducteurs l'utilisant
JP2008065953A (ja) * 2006-09-11 2008-03-21 Fujitsu Ltd 不揮発性半導体記憶装置及びその読み出し方法
JP2008085204A (ja) * 2006-09-28 2008-04-10 Toshiba Corp 半導体記憶装置及びその製造方法
JP2009016845A (ja) * 2007-07-04 2009-01-22 Dongbu Hitek Co Ltd 半導体素子及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010251529A (ja) * 2009-04-16 2010-11-04 Sony Corp 半導体記憶装置およびその製造方法
CN102693985A (zh) * 2011-03-25 2012-09-26 北京兆易创新科技有限公司 一种可编程存储器及其制造方法

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