WO2009131215A1 - Circuit d'attaque - Google Patents

Circuit d'attaque Download PDF

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Publication number
WO2009131215A1
WO2009131215A1 PCT/JP2009/058171 JP2009058171W WO2009131215A1 WO 2009131215 A1 WO2009131215 A1 WO 2009131215A1 JP 2009058171 W JP2009058171 W JP 2009058171W WO 2009131215 A1 WO2009131215 A1 WO 2009131215A1
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Prior art keywords
transistor
signal
input
driver circuit
switching transistor
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PCT/JP2009/058171
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English (en)
Japanese (ja)
Inventor
康之 鈴木
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日本電気株式会社
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Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2010509242A priority Critical patent/JP5338810B2/ja
Publication of WO2009131215A1 publication Critical patent/WO2009131215A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Definitions

  • the present invention relates to a driver circuit used in an optical transmission circuit.
  • the present invention drives an external modulator such as a dielectric modulator using a dielectric waveguide such as LiNbO 3 or an electroabsorption semiconductor modulator using light absorption of a semiconductor with a voltage of about several volts. It relates to the driver circuit.
  • MZ optical modulator Mach-Zehnder optical modulator
  • EA optical modulator electroabsorption modulator
  • the EA optical modulator can be driven at a lower voltage than the MZ optical modulator (driving voltage 4 V pp or more) and is suitable for downsizing, the driving voltage needs to be 2 V pp or more. Therefore, a driver circuit for driving these modulators requires high amplitude output as well as high speed operation.
  • FIG. 13 is a circuit diagram showing a driver circuit employing the differential amplifier configuration described in Patent Document 1. In FIG. This driver circuit is composed of two stages of input buffer circuits 2 and 3 and one stage of output circuit 1.
  • GND is the ground terminal
  • VEE is the power supply voltage
  • IN0 is the input terminal
  • R1 and R2 are load resistors
  • Q1 to Q4 are transistors
  • CS is a constant current source
  • VCAS is the voltage terminal
  • I is the current flowing through the current source CS
  • OUT OUTB is a differential output terminal.
  • the output circuit 1 is a cascode amplifier in which transistors Q3 and Q4, whose bases are grounded on the collector side of the switching transistors Q1 and Q2, are vertically stacked in order to reduce the mirror capacitance of the switching transistors Q1 and Q2 and improve the bandwidth. It is.
  • FIG. 14 shows an output circuit 1a of a modulator driver circuit composed of a normal differential amplifier having no cascode connection.
  • 15A to 15B show signal waveforms at the respective terminals of the output circuit 1a.
  • Q1 and Q2 are switching transistors.
  • the resistors R1 and R2 are load resistors for generating an output amplitude, and the output amplitude is determined by these load resistors, the external load (the internal resistance of the modulator), and the current I of the constant current source CS.
  • the switching transistors Q1 and Q2 require a VCE breakdown voltage of 6V or more.
  • the base potentials of the cascode-connected transistors Q3 and Q4 are grounded to about -4.4V (about the output amplitude). For this reason, when the output terminal OUTB (see FIG. 17A) becomes HIGH level, the VCE of the switching transistor Q1 (see FIG. 17C) is about 1.1V, whereas the cascode-connected transistor Q3 has a potential of 5V as VCE. Applied (see FIG. 17B). Therefore, the cascode-connected transistors Q3 and Q4 require a VCE breakdown voltage of 5V or more.
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a driver circuit that uses a device having a low withstand voltage and can obtain a high output amplitude.
  • the present invention includes a first switching transistor to which an input signal is applied, and a first transistor cascode-connected to the first switching transistor, and the first transistor Is a driver circuit that inputs a signal whose level is inverted in synchronization with the input signal to the first switching transistor. Further, the present invention is a method of adding an input signal to a switching transistor, and applying a signal whose level is inverted and synchronized with the input signal to the switching transistor to the input of the transistor cascode-connected to the switching transistor. .
  • the voltage corresponding to the output amplitude is divided into the emitter-collector voltage of the switching transistor and the emitter-collector voltage of the transistor cascode-connected to the switching transistor.
  • a device with a low breakdown voltage can be used and a high output amplitude can be obtained.
  • FIG. 1 is a circuit diagram showing a configuration of a driver circuit 11 according to the first embodiment of the present invention.
  • the driver circuit 11 shown in this figure is configured using a differential circuit.
  • GND is a ground terminal
  • VEE is a power supply voltage
  • IN and INB are input terminals
  • OUT and OUTB are differential output terminals for outputting a signal having an amplitude for driving a modulator (not shown).
  • Q1 and Q2 (first switching transistor and second switching transistor in the present invention) are switching transistor pairs
  • Q3 and Q4 first transistor and second transistor in the present invention) are respectively connected to transistors Q1 and Q2.
  • a cascode-connected transistor is a cascode-connected transistor.
  • CS is a constant current source, which is connected between the emitters of the transistors Q1 and Q2 and the power supply voltage VEE, and I is a current flowing through the constant current source CS.
  • Resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND are load resistors for generating a signal having an output amplitude. The output amplitude is determined by the load resistance, the external load (the internal resistance of the modulator), and the current I flowing through the constant current source CS.
  • INCAS and INCASB are input terminals connected to the bases of the cascode-connected transistors Q3 and Q4.
  • Data signals for driving the modulator are input to input terminals IN and INB connected to the bases of the switching transistors Q1 and Q2.
  • Signals whose levels are inverted in synchronization with these data signals are input to input terminals INCAS and INCASB connected to the bases of cascode-connected transistors Q3 and Q4.
  • 2A to 2E show signal waveforms at each terminal.
  • Signals having a HIGH level of -5.1 V, a LOW level of -5.5 V, and phases inverted from each other are applied to the input terminals IN and INB connected to the switching transistors Q1 and Q2 (see FIG. 2B).
  • the input terminals INCAS and INCASB connected to the cascode-connected transistors Q3 and Q4 have a HIGH level of -2.4V and a LOW level of -4.2 which are inverted in synchronization with the signals applied to the input terminals IN and INB, respectively.
  • Give a V signal see Figure 2C).
  • a signal having an amplitude of 4.6 V see FIG.
  • the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 3.0 V at the maximum (see FIG. 2D).
  • the emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2.9 V at maximum (see FIG. 2E). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q1 to Q4 to be used.
  • the relationship between the voltages of the terminals IN, INB, INCAS, and INCASB is obtained.
  • a high level signal is input to the terminal IN and a low level signal is input to the terminal INB.
  • the voltage applied to the constant current source CS is VCS, and the output amplitude is VR.
  • the emitter-base voltage when the transistor is turned on is VB
  • the emitter-collector voltage is VE
  • the emitter-base voltage when the transistor is turned off is VBO
  • the emitter-collector voltage is VEO
  • transistors Q1, Q3 Q2 , Q4
  • the voltage applied to terminal IN is VA-VB
  • the voltage applied to the terminal INCAS is VA-VE-VB
  • the voltage applied to terminal INB is VA-VBO
  • the voltage applied to the terminal INCASB is VA-VEO-VBO. If the HIGH and LOW level voltages of the terminal IN, the terminal INB and the terminal INCAS, and the terminal INCASB are set so that the above holds, the voltage VA is between the emitter and collector of the switching transistor Q1 (Q2) when the output is high. And evenly between the emitter and collector of the cascode-connected transistor Q3 (Q4).
  • cascode-connected transistors Q3 and Q4 are provided.
  • signals whose levels are inverted in synchronization with the signals input to the switching transistors Q1 and Q2 are input to the transistors Q3 and Q4.
  • the voltage applied to the transistor Q3 (Q4) cascode-connected to the switching transistor Q1 (Q2) is set so as to be equally divided into the emitter-collector voltage and the emitter-collector voltage of the cascode-connected transistor. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 3 shows a circuit diagram of the driver circuit 12 according to the second embodiment of the present invention.
  • 4A to 4D show waveforms of terminals for explaining the operation.
  • the driver circuit 12 shown in FIG. 3 includes an input buffer circuit 2 (first amplification means in the present invention), two buffer circuits 3 and 4 (second amplification means and third amplification means in the present invention), and a difference.
  • the output circuit 13 is configured using a dynamic circuit.
  • the single-phase data signal input to the input terminal IN0 is converted into a differential data signal of both phases and input to the two buffer circuits 3 and 4.
  • the output circuit 13 is composed of a differential circuit, and includes a pair of switching transistors Q1 and Q2, transistors Q3 and Q4 cascode-connected to these switching transistors Q1 and Q2, ground terminal GND, power supply voltage VEE, and a modulator, respectively.
  • differential output terminals OUT and OUTB that output signals with the driving amplitude
  • load resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND, and the emitters of the transistors Q1 and Q2 and the power supply voltage VEE It is comprised from the constant current source CS connected to.
  • the differential outputs of the buffer circuit 3 (the first signal and the second signal in the present invention) are connected to the bases of the switching transistor pair Q1, Q2.
  • the bases of the cascode-connected transistor pairs Q3 and Q4 have differential outputs of the buffer circuit 4 whose levels are inverted from the differential outputs of the buffer circuit 3 (the third signal and the fourth signal in the present invention). ) Is connected.
  • the power supply voltage VEE of the output circuit 13 is set to -7V.
  • the switching transistor pair Q1, Q2 of the output circuit 13 has a HIGH level of -5.1V.
  • a signal whose LOW level is ⁇ 5.5 V is input through the buffer circuit 3.
  • a signal having a HIGH level of ⁇ 2.4 V and a LOW level of ⁇ 4.2 V is amplified and inputted through the buffer circuit 4 to the cascode-connected transistor pair Q3 and Q4 of the output circuit 13.
  • the input signal to the switching transistor Q1 (Q2) and the input signal to the cascode-connected transistor Q3 (Q4) are synchronized, although the logic is inverted.
  • 4A to 4D show waveforms at each terminal.
  • a cascode-connected transistor is provided in the output circuit.
  • the buffer circuit in the preceding stage of the output circuit generates a signal whose level is inverted in synchronization with the signal input to the switching transistor and inputs the signal to the cascode-connected transistor.
  • the input level of the switching transistor is LOW (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum)
  • the emitter of the transistor cascode-connected with the emitter-collector voltage VCE of the switching transistor set the input signal level to the base of the cascode-connected transistors so that the collector-to-collector voltage VCE is equal.
  • a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 5 shows a driver circuit 14 according to a third embodiment of the present invention.
  • FIGS. 6A to 6D and FIGS. 7A to 7C show waveforms of terminals for explaining the operation.
  • the driver circuit 14 shown in FIG. 5 is composed of a differential circuit, and includes a pair of switching transistors Q1, Q2, two transistor pairs Q3, Q4 and Q5, Q6 cascode-connected to these transistor pairs Q1, Q2, ground It consists of a terminal GND, a power supply voltage VEE, differential output terminals OUT and OUTB that output a signal having an amplitude for driving the modulator, load resistors R1 and R2, and a constant current source CS.
  • INCAS and INCASB are input terminals connected to the bases of cascode-connected transistors Q5 and Q6, INCAS1 and INCAS1B are input terminals connected to the bases of cascode-connected transistors Q3 and Q4, and IN and INB Is a terminal to which an input signal input to each base of the switching transistors Q1 and Q2 is applied.
  • the signal whose level is inverted in synchronization with these input signals is applied to the input terminals INCA and INCASB connected to the cascode-connected transistor pair Q5 and Q6 (see FIG. 6C).
  • signals having the same phase and different levels are applied to the input terminals INCAS1 and INCAS1B connected to the cascode-connected transistor pairs Q3 and Q4 in synchronization with the signals applied to the input terminals INCAS and INCASB (see FIG. 6D). .
  • the input terminals INCA1 and INCAS1B connected to the cascode-connected transistor pair Q3 and Q4 have a HIGH level ⁇ 3.4V, a LOW level ⁇ whose level is inverted in synchronization with the signal applied to the input terminals IN and INB.
  • a signal of 4.6V is applied (see FIG. 6D).
  • 6A to 6D and FIGS. 7A to 7C show signal waveforms at the respective terminals.
  • a signal having an amplitude of 3.5 V appears at the output terminal OUT (OUTB) (see FIG. 6A).
  • the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 2 V or less (see FIG. 7A).
  • the emitter-collector voltage VCE of the cascode-connected transistors Q5 and Q6 is 2V or less (see FIG. 7B), and the emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2V or less. (See Figure 7C). Accordingly, a transistor having a VCE breakdown voltage of 2 V can be used as a transistor to be used.
  • the cascode-connected transistor pair As described above, two cascode-connected transistor pairs are provided. Further, a signal whose level is inverted in synchronization with a signal input to the switching transistor pair is input to the cascode-connected transistor pair. Furthermore, when the output is at a high level (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the voltage applied to the switching transistor and the two transistors cascode-connected to the switching transistor is The input signal level to the cascode-connected transistor pair is set so as to be equally divided into the emitter-collector voltage VCE and the emitter-collector voltage VCE of the two cascode-connected transistors. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • the number of transistors that are cascode-connected to the switching transistors is two, but other numbers of transistors may be cascode-connected to the switching transistors.
  • FIG. 8 shows a driver circuit according to a fourth embodiment of the present invention.
  • the driver circuit shown in FIG. 8 includes emitter follower circuits 5a and 5b (first amplifying means and second amplifying means in the present invention) and an output circuit 15.
  • the output circuit 15 is configured using a differential circuit, and includes a switching transistor pair Q1, Q2 (first switching transistor and second switching transistor in the present invention), a cascode-connected transistor pair Q3, Q4, Q5.
  • the emitter follower circuit 5a includes an input terminal IN, input transistors Q9 and Q11, level shift diodes (transistors that are diode-connected) D1, D3, D5, D7, and D9, and current source resistors R3 and R5. .
  • the emitter follower circuit 5b includes an input terminal INB, input transistors Q10 and Q12, level shift diodes D2, D4, D6, D8, and D10, and current source resistors R4 and R6.
  • the outputs of the emitter follower circuits 5a and 5b are connected to the bases of the switching transistor pair Q1 and Q2 of the output circuit 15. Further, the signals of the emitters of the level-shifted diodes D8, D6, D4 of the emitter follower circuit 5b (a plurality of fourth signals in the present invention) are applied to the cascode-connected transistors Q3, Q5, Q7 of the output circuit 15. . Further, the signals of the emitters of the level-shifted diodes D7, D5, and D3 of the emitter follower circuit 5a (a plurality of second signals in the present invention) are applied to the cascode-connected transistors Q4, Q6, and Q8 of the output circuit 15. .
  • the signal input to the switching transistor Q1 and the signal whose level is inverted are added to the transistors Q3, Q5, and Q7.
  • a signal whose level is inverted from that of the signal input to the switching transistor Q2 is applied to the transistors Q4, Q6, and Q8.
  • the input signals of the transistor pairs Q3, Q4, Q5, Q6, Q7, and Q8 that are cascode-connected to the input signals of the switching transistor pair Q1 and Q2 of the output circuit 15 are synchronized by adjusting the wiring length.
  • the switching transistor pair Q1, Q2 of the output circuit 15 functions to switch the current of the constant current source CS.
  • the input signals of the cascode-connected transistors Q3, Q5, Q7 (Q4, Q6, Q8) are synchronized with the input signal of the switching transistor Q1 (Q2), but the logic level is inverted.
  • the input signals of transistors Q3, Q5, Q7 (Q4, Q6, Q8) are input signals using diodes D4, D6, D8, D10 (D3, D5, D7, D9) of emitter follower circuit 5b (5a). The level is determined.
  • the differential output terminal OUTB becomes HIGH level and the transistors Q1, Q3, Q5 and Q7 are applied with an equal voltage divided by using diodes D4, D6, D8, and D10 as VCE. Therefore, a lower voltage (a voltage of about 1/4 of the output amplitude) is applied between the emitter and collector of the transistors Q1, Q3, Q5, and Q7 with respect to the required output amplitude.
  • a plurality of cascode-connected transistor pairs are provided in the output circuit. Also, a signal whose level is changed by the level shift diode of the emitter follower circuit in the previous stage of the output circuit is generated, and the signal whose level is inverted in synchronization with the signal input to the switching transistor pair is cascode connected to the switching transistor pair Input to the transistor pair.
  • an emitter follower circuit having a plurality of level shift diodes is used to change the input level of a plurality of cascode-connected transistors, but other methods may be used.
  • the number of transistors that are cascode-connected to the switching transistors is three.
  • other numbers of transistors may be cascode-connected to the switching transistors.
  • the number of level shift diodes is appropriately changed according to the number of transistors cascode-connected to the switching transistors.
  • FIG. 9 is a circuit diagram showing a configuration of the driver circuit 16 according to the fifth embodiment of the present invention.
  • the driver circuit 16 shown in this figure is constituted by a distributed circuit.
  • the driver circuit 16 includes an input terminal IN, an input terminal INCAS, an input-side distributed constant transmission line 19 (input-side transmission line in the present invention), an input termination resistor Rin (input-side termination circuit in the present invention), an input Side bias circuit 18a, common-emitter transistor Q9 (amplifier circuit in the present invention), transistor Q10 cascode-connected to transistor Q9, input-side distributed constant transmission line 21 of transistor Q10, termination circuit for input-side distributed constant transmission line 21 (termination) Resistor) Rincas, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20 (output side transmission line in the present invention), output termination resistor Rout (output side termination circuit in the present invention), output side bias circuit 18c, output terminal Consists of OUT.
  • Vbin1 and Vbin2 are bias voltages, and V
  • a signal input from the input terminal IN propagates through the input-side distributed constant transmission line 19 in the direction of the input termination resistor Rin (forward direction). Most of the signals propagating in this way are sequentially distributed to the transistor Q9 and amplified.
  • the signal input to each transistor Q9 is amplified according to the current flowing through each transistor, and propagates through the output-side distributed constant transmission line 20 in the direction of the output terminal OUT. Further, since the electrical lengths in the respective propagation paths from the input terminal IN to the output terminal OUT are selected to be equal, the signals amplified by the transistors Q9 are sequentially synthesized by the output-side distributed constant transmission line 20. The amplified signal is output from the output terminal OUT.
  • a transistor whose logic is inverted in synchronization with a signal input from the input terminal IN is input from the input terminal INCAS to the transistor Q10 which is cascode-connected to the transistor Q9.
  • the input-side distributed constant transmission line 21 of the cascode-connected transistor Q10 is set so that the signal input to each emitter grounded transistor Q9 and the signal input to the transistor Q10 are distributed in synchronization.
  • 10A to 10E show signal waveforms at each terminal.
  • the power supply voltage VEE is 5V.
  • a signal having a HIGH level of 1.0 V and a LOW level of 0.5 V is applied to the input terminal IN on the grounded emitter transistor Q9 side (see FIG. 10C).
  • a HIGH level 2.8V signal and a LOW level 1.6V signal whose phases are inverted in synchronization with a signal applied to the input terminal IN are applied to the cascode-connected input terminal INCAS on the transistor Q10 side (see FIG. 10B).
  • a signal (see FIG. 10A) having an amplitude of 4.0 V appears at the output terminal OUT.
  • the emitter-collector voltage VCE of the common-emitter transistor Q9 is 2.6 V at the maximum (see FIG. 10E). Further, the emitter-collector voltage VCE of the cascode-connected transistor Q10 is also a maximum of 2.6 V or less (see FIG. 10D). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q9 and Q10 to be used.
  • the cascode-connected transistor Q10 is provided in the driver circuit configured by the distributed circuit. Further, a signal whose phase is inverted in synchronization with the signal input to the grounded emitter transistor Q9 is input to the transistor Q10. Furthermore, when the output is at a high level, the voltage applied to the transistor Q10 cascode-connected to the common-emitter transistor Q9 is equal to the emitter-collector voltage of the common-emitter transistor Q9 and the emitter-collector voltage of the cascode-connected transistor Q10.
  • the input signal level of the cascode-connected transistors is set so as to be divided. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 11 shows a circuit diagram of a driver circuit 22 according to the sixth embodiment of the present invention.
  • 12A to 12C show waveforms at each terminal for explaining the operation.
  • the driver circuit shown in FIG. 11 includes a differential circuit 23 (first amplifying means in the present invention) and an output circuit 17 configured by a distributed circuit.
  • a differential data signal is input to the input terminals IN and INB, and a differential data signal having a gain and an amplitude for driving the output circuit 17 (the first signal and the first signal in the present invention). 2 signal) is output.
  • an input buffer circuit for converting a single-phase data signal into a differential data signal may be provided in the preceding stage of the differential circuit 23.
  • R1 and R2 are load resistors
  • Q1 and Q2 are transistors
  • CS is a constant current source.
  • the output circuit 17 is a distributed circuit. Specifically, the output circuit 17 includes an input side distributed constant transmission line 19, an input termination resistor Rin, an input side bias circuit 18a, a common emitter transistor Q9, a transistor Q10 cascode-connected to the common emitter transistor Q9, and an input of the transistor Q10. Side distributed constant transmission line 21, termination circuit (termination resistor) Rincas of input side distributed constant transmission line 21 of transistor Q10, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20, output termination resistor Rout, output side bias circuit 18c and an output terminal OUT.
  • termination circuit termination resistor
  • One of the outputs of the differential circuit 23 is connected to the input of the grounded emitter transistor (switching transistor) Q9 via the bias circuit 18a and the input-side distributed constant transmission line 19.
  • the other of the outputs of the differential circuit 23 is connected to the input of the cascode-connected transistor pair Q10 via the bias circuit 18b and the input-side distributed constant transmission line 21.
  • a signal whose phase is inverted is input to the transistor pair Q10 cascode-connected to the grounded emitter transistor (switching transistor) Q9 of the output circuit 17.
  • the operation will be described in the case of outputting an output amplitude of 4.0V.
  • the load resistors R1 and R2 of the differential circuit 23 and the constant current source CS are adjusted so that a signal with a HIGH level of 0 V and a LOW level of -1.0 V is output from the output terminal of the differential circuit 23.
  • the power supply voltage VEE of the output circuit 17 is set to 5V and the bias voltage Vbin1 of the bias circuit 18a on the input side of the grounded emitter transistor Q9 is set to 0.5V, the grounded transistor Q9 receives a signal of HIGH level 1.0V and LOW level 0V. Entered.
  • the bias voltage Vbin2 in the bias circuit 18b on the input side of the transistor Q10 cascode-connected to the grounded-emitter transistor Q9 is set to 2.2V
  • a signal of HIGH level 2.7V and LOW level 1.7V is applied to the cascode-connected transistor Q10.
  • the input signal of the grounded-emitter transistor Q9 and the input signal of the cascode-connected transistor Q10 are signals whose phases are inverted and synchronized.
  • 12A to 12C show waveforms at each terminal. An output waveform having a 4V amplitude is obtained at the output terminal OUT of the output circuit 17 (see FIG. 12A).
  • the voltage VCE (see FIG. 12C) applied between the emitter and collector of the grounded-emitter transistor Q9 and the voltage VCE (see FIG. 12B) applied between the emitter and collector of the cascode-connected transistor Q10 are 3V or less. .
  • a cascode-connected transistor is provided in an output circuit constituted by a distributed circuit. Further, the signal output from the differential circuit in the previous stage of the output circuit is set so that a signal whose phase is inverted from that of the signal input to the grounded emitter transistor is input to the cascode-connected transistor. In addition, when the input level of the common-emitter transistor is LOW, the input of the cascode-connected transistor is such that the emitter-collector voltage VCE of the switching transistor and the emitter-collector voltage VCE of the cascode-connected transistor are equal. Set the signal level. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • the transistor is formed of a bipolar transistor, but may be formed of a FET such as a MOS.
  • a driver circuit that drives a modulator used in a transmitter for optical communication has been described.
  • the present invention can also be applied to a power amplifier.
  • the driver circuit according to each of the above embodiments has the following common concept. That is, a cascode-connected transistor is provided for a transistor to which an input signal is input. In addition, a signal that is synchronized with the input signal of the transistor and whose phase is inverted is input to the input of the cascode-connected transistor. Further, when the emitter-collector voltage of the transistor is maximum (when the output is at a high level), the voltage applied to both ends of the circuit composed of the transistor connected to the transistor in cascode is connected to the emitter-collector voltage of the transistor in cascode connection. Is divided into the emitter-collector voltage of the transistor. Such a common concept is applied to a driver circuit constituted by a differential circuit and a driver circuit constituted by a distributed circuit.
  • the present invention is used in a driver circuit for driving an external modulator such as a dielectric modulator using a dielectric waveguide or an electroabsorption semiconductor modulator using light absorption of a semiconductor.
  • Input-side distributed constant transmission line 20 ... Output-side distributed constant transmission line 21 ... Cascade-connected transistor input-side distributed constant line Q1, Q2, Q9 ... Switching transistors Q3, Q4, Q5, Q6, Q7, Q8, Q10 ... transistor R1, R2 ... Load resistance Rin, Rout, Rincas ... Terminating resistor CS... Constant current source VEE ... Power supply voltage Vbin1, Vbin2 ... Bias voltage IN, INB, INCAS, INCASB, INCAS1, INCAS1B ... Input terminal OUT, OUTB ... Output terminals GND ... Ground

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  • General Engineering & Computer Science (AREA)
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Abstract

La présente invention concerne un circuit d'attaque qui utilise un composant à faible tension de claquage et qui peut acquérir une forte amplitude de sortie. Le circuit d'attaque inclut un premier transistor de commutation sur lequel est appliqué le signal d'entrée, ainsi qu'un premier transistor relié en série avec le transistor de commutation. Un signal, qui est synchronisé avec le signal d'entrée sur le premier transistor de commutation et dont le niveau est inversé, est appliqué à l’entrée du premier transistor.
PCT/JP2009/058171 2008-04-25 2009-04-24 Circuit d'attaque WO2009131215A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010509242A JP5338810B2 (ja) 2008-04-25 2009-04-24 ドライバー回路、及び信号入力方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008115845 2008-04-25
JP2008-115845 2008-04-25
JP2009-099967 2009-04-16
JP2009099967 2009-04-16

Publications (1)

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WO2009131215A1 true WO2009131215A1 (fr) 2009-10-29

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PCT/JP2009/058171 WO2009131215A1 (fr) 2008-04-25 2009-04-24 Circuit d'attaque

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014050087A (ja) * 2012-09-04 2014-03-17 Renesas Electronics Corp 差動出力回路および半導体装置
JP2014072553A (ja) * 2012-09-27 2014-04-21 Asahi Kasei Electronics Co Ltd 演算増幅器及びそれを備えたパイプライン型ａ／ｄコンバータ
JP2016054542A (ja) * 2015-11-27 2016-04-14 ルネサスエレクトロニクス株式会社 差動出力回路および半導体装置
US11290073B1 (en) * 2020-11-20 2022-03-29 Synaptics Incorporated Self-biased differential transmitter

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JPS59228430A (ja) * 1983-06-10 1984-12-21 Hitachi Ltd 半導体回路
JPH03270408A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 半導体集積回路
JPH05291844A (ja) * 1992-04-10 1993-11-05 Olympus Optical Co Ltd レベルシフト回路
JP2004297165A (ja) * 2003-03-25 2004-10-21 Toshiba Corp アナログ／ディジタル変換回路および通信装置
JP2007180797A (ja) * 2005-12-27 2007-07-12 Matsushita Electric Ind Co Ltd レベルシフト回路

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JPS59228430A (ja) * 1983-06-10 1984-12-21 Hitachi Ltd 半導体回路
JPH03270408A (ja) * 1990-03-20 1991-12-02 Fujitsu Ltd 半導体集積回路
JPH05291844A (ja) * 1992-04-10 1993-11-05 Olympus Optical Co Ltd レベルシフト回路
JP2004297165A (ja) * 2003-03-25 2004-10-21 Toshiba Corp アナログ／ディジタル変換回路および通信装置
JP2007180797A (ja) * 2005-12-27 2007-07-12 Matsushita Electric Ind Co Ltd レベルシフト回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014050087A (ja) * 2012-09-04 2014-03-17 Renesas Electronics Corp 差動出力回路および半導体装置
JP2014072553A (ja) * 2012-09-27 2014-04-21 Asahi Kasei Electronics Co Ltd 演算増幅器及びそれを備えたパイプライン型ａ／ｄコンバータ
JP2016054542A (ja) * 2015-11-27 2016-04-14 ルネサスエレクトロニクス株式会社 差動出力回路および半導体装置
US11290073B1 (en) * 2020-11-20 2022-03-29 Synaptics Incorporated Self-biased differential transmitter

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