WO2009131215A1 - Driver circuit - Google Patents

Driver circuit Download PDF

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Publication number
WO2009131215A1
WO2009131215A1 PCT/JP2009/058171 JP2009058171W WO2009131215A1 WO 2009131215 A1 WO2009131215 A1 WO 2009131215A1 JP 2009058171 W JP2009058171 W JP 2009058171W WO 2009131215 A1 WO2009131215 A1 WO 2009131215A1
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Prior art keywords
transistor
signal
input
driver circuit
switching transistor
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PCT/JP2009/058171
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French (fr)
Japanese (ja)
Inventor
康之 鈴木
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日本電気株式会社
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Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP2010509242A priority Critical patent/JP5338810B2/en
Publication of WO2009131215A1 publication Critical patent/WO2009131215A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Definitions

  • the present invention relates to a driver circuit used in an optical transmission circuit.
  • the present invention drives an external modulator such as a dielectric modulator using a dielectric waveguide such as LiNbO 3 or an electroabsorption semiconductor modulator using light absorption of a semiconductor with a voltage of about several volts. It relates to the driver circuit.
  • MZ optical modulator Mach-Zehnder optical modulator
  • EA optical modulator electroabsorption modulator
  • the EA optical modulator can be driven at a lower voltage than the MZ optical modulator (driving voltage 4 V pp or more) and is suitable for downsizing, the driving voltage needs to be 2 V pp or more. Therefore, a driver circuit for driving these modulators requires high amplitude output as well as high speed operation.
  • FIG. 13 is a circuit diagram showing a driver circuit employing the differential amplifier configuration described in Patent Document 1. In FIG. This driver circuit is composed of two stages of input buffer circuits 2 and 3 and one stage of output circuit 1.
  • GND is the ground terminal
  • VEE is the power supply voltage
  • IN0 is the input terminal
  • R1 and R2 are load resistors
  • Q1 to Q4 are transistors
  • CS is a constant current source
  • VCAS is the voltage terminal
  • I is the current flowing through the current source CS
  • OUT OUTB is a differential output terminal.
  • the output circuit 1 is a cascode amplifier in which transistors Q3 and Q4, whose bases are grounded on the collector side of the switching transistors Q1 and Q2, are vertically stacked in order to reduce the mirror capacitance of the switching transistors Q1 and Q2 and improve the bandwidth. It is.
  • FIG. 14 shows an output circuit 1a of a modulator driver circuit composed of a normal differential amplifier having no cascode connection.
  • 15A to 15B show signal waveforms at the respective terminals of the output circuit 1a.
  • Q1 and Q2 are switching transistors.
  • the resistors R1 and R2 are load resistors for generating an output amplitude, and the output amplitude is determined by these load resistors, the external load (the internal resistance of the modulator), and the current I of the constant current source CS.
  • the switching transistors Q1 and Q2 require a VCE breakdown voltage of 6V or more.
  • the base potentials of the cascode-connected transistors Q3 and Q4 are grounded to about -4.4V (about the output amplitude). For this reason, when the output terminal OUTB (see FIG. 17A) becomes HIGH level, the VCE of the switching transistor Q1 (see FIG. 17C) is about 1.1V, whereas the cascode-connected transistor Q3 has a potential of 5V as VCE. Applied (see FIG. 17B). Therefore, the cascode-connected transistors Q3 and Q4 require a VCE breakdown voltage of 5V or more.
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a driver circuit that uses a device having a low withstand voltage and can obtain a high output amplitude.
  • the present invention includes a first switching transistor to which an input signal is applied, and a first transistor cascode-connected to the first switching transistor, and the first transistor Is a driver circuit that inputs a signal whose level is inverted in synchronization with the input signal to the first switching transistor. Further, the present invention is a method of adding an input signal to a switching transistor, and applying a signal whose level is inverted and synchronized with the input signal to the switching transistor to the input of the transistor cascode-connected to the switching transistor. .
  • the voltage corresponding to the output amplitude is divided into the emitter-collector voltage of the switching transistor and the emitter-collector voltage of the transistor cascode-connected to the switching transistor.
  • a device with a low breakdown voltage can be used and a high output amplitude can be obtained.
  • FIG. 1 is a circuit diagram showing a configuration of a driver circuit 11 according to the first embodiment of the present invention.
  • the driver circuit 11 shown in this figure is configured using a differential circuit.
  • GND is a ground terminal
  • VEE is a power supply voltage
  • IN and INB are input terminals
  • OUT and OUTB are differential output terminals for outputting a signal having an amplitude for driving a modulator (not shown).
  • Q1 and Q2 (first switching transistor and second switching transistor in the present invention) are switching transistor pairs
  • Q3 and Q4 first transistor and second transistor in the present invention) are respectively connected to transistors Q1 and Q2.
  • a cascode-connected transistor is a cascode-connected transistor.
  • CS is a constant current source, which is connected between the emitters of the transistors Q1 and Q2 and the power supply voltage VEE, and I is a current flowing through the constant current source CS.
  • Resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND are load resistors for generating a signal having an output amplitude. The output amplitude is determined by the load resistance, the external load (the internal resistance of the modulator), and the current I flowing through the constant current source CS.
  • INCAS and INCASB are input terminals connected to the bases of the cascode-connected transistors Q3 and Q4.
  • Data signals for driving the modulator are input to input terminals IN and INB connected to the bases of the switching transistors Q1 and Q2.
  • Signals whose levels are inverted in synchronization with these data signals are input to input terminals INCAS and INCASB connected to the bases of cascode-connected transistors Q3 and Q4.
  • 2A to 2E show signal waveforms at each terminal.
  • Signals having a HIGH level of -5.1 V, a LOW level of -5.5 V, and phases inverted from each other are applied to the input terminals IN and INB connected to the switching transistors Q1 and Q2 (see FIG. 2B).
  • the input terminals INCAS and INCASB connected to the cascode-connected transistors Q3 and Q4 have a HIGH level of -2.4V and a LOW level of -4.2 which are inverted in synchronization with the signals applied to the input terminals IN and INB, respectively.
  • Give a V signal see Figure 2C).
  • a signal having an amplitude of 4.6 V see FIG.
  • the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 3.0 V at the maximum (see FIG. 2D).
  • the emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2.9 V at maximum (see FIG. 2E). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q1 to Q4 to be used.
  • the relationship between the voltages of the terminals IN, INB, INCAS, and INCASB is obtained.
  • a high level signal is input to the terminal IN and a low level signal is input to the terminal INB.
  • the voltage applied to the constant current source CS is VCS, and the output amplitude is VR.
  • the emitter-base voltage when the transistor is turned on is VB
  • the emitter-collector voltage is VE
  • the emitter-base voltage when the transistor is turned off is VBO
  • the emitter-collector voltage is VEO
  • transistors Q1, Q3 Q2 , Q4
  • the voltage applied to terminal IN is VA-VB
  • the voltage applied to the terminal INCAS is VA-VE-VB
  • the voltage applied to terminal INB is VA-VBO
  • the voltage applied to the terminal INCASB is VA-VEO-VBO. If the HIGH and LOW level voltages of the terminal IN, the terminal INB and the terminal INCAS, and the terminal INCASB are set so that the above holds, the voltage VA is between the emitter and collector of the switching transistor Q1 (Q2) when the output is high. And evenly between the emitter and collector of the cascode-connected transistor Q3 (Q4).
  • cascode-connected transistors Q3 and Q4 are provided.
  • signals whose levels are inverted in synchronization with the signals input to the switching transistors Q1 and Q2 are input to the transistors Q3 and Q4.
  • the voltage applied to the transistor Q3 (Q4) cascode-connected to the switching transistor Q1 (Q2) is set so as to be equally divided into the emitter-collector voltage and the emitter-collector voltage of the cascode-connected transistor. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 3 shows a circuit diagram of the driver circuit 12 according to the second embodiment of the present invention.
  • 4A to 4D show waveforms of terminals for explaining the operation.
  • the driver circuit 12 shown in FIG. 3 includes an input buffer circuit 2 (first amplification means in the present invention), two buffer circuits 3 and 4 (second amplification means and third amplification means in the present invention), and a difference.
  • the output circuit 13 is configured using a dynamic circuit.
  • the single-phase data signal input to the input terminal IN0 is converted into a differential data signal of both phases and input to the two buffer circuits 3 and 4.
  • the output circuit 13 is composed of a differential circuit, and includes a pair of switching transistors Q1 and Q2, transistors Q3 and Q4 cascode-connected to these switching transistors Q1 and Q2, ground terminal GND, power supply voltage VEE, and a modulator, respectively.
  • differential output terminals OUT and OUTB that output signals with the driving amplitude
  • load resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND, and the emitters of the transistors Q1 and Q2 and the power supply voltage VEE It is comprised from the constant current source CS connected to.
  • the differential outputs of the buffer circuit 3 (the first signal and the second signal in the present invention) are connected to the bases of the switching transistor pair Q1, Q2.
  • the bases of the cascode-connected transistor pairs Q3 and Q4 have differential outputs of the buffer circuit 4 whose levels are inverted from the differential outputs of the buffer circuit 3 (the third signal and the fourth signal in the present invention). ) Is connected.
  • the power supply voltage VEE of the output circuit 13 is set to -7V.
  • the switching transistor pair Q1, Q2 of the output circuit 13 has a HIGH level of -5.1V.
  • a signal whose LOW level is ⁇ 5.5 V is input through the buffer circuit 3.
  • a signal having a HIGH level of ⁇ 2.4 V and a LOW level of ⁇ 4.2 V is amplified and inputted through the buffer circuit 4 to the cascode-connected transistor pair Q3 and Q4 of the output circuit 13.
  • the input signal to the switching transistor Q1 (Q2) and the input signal to the cascode-connected transistor Q3 (Q4) are synchronized, although the logic is inverted.
  • 4A to 4D show waveforms at each terminal.
  • a cascode-connected transistor is provided in the output circuit.
  • the buffer circuit in the preceding stage of the output circuit generates a signal whose level is inverted in synchronization with the signal input to the switching transistor and inputs the signal to the cascode-connected transistor.
  • the input level of the switching transistor is LOW (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum)
  • the emitter of the transistor cascode-connected with the emitter-collector voltage VCE of the switching transistor set the input signal level to the base of the cascode-connected transistors so that the collector-to-collector voltage VCE is equal.
  • a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 5 shows a driver circuit 14 according to a third embodiment of the present invention.
  • FIGS. 6A to 6D and FIGS. 7A to 7C show waveforms of terminals for explaining the operation.
  • the driver circuit 14 shown in FIG. 5 is composed of a differential circuit, and includes a pair of switching transistors Q1, Q2, two transistor pairs Q3, Q4 and Q5, Q6 cascode-connected to these transistor pairs Q1, Q2, ground It consists of a terminal GND, a power supply voltage VEE, differential output terminals OUT and OUTB that output a signal having an amplitude for driving the modulator, load resistors R1 and R2, and a constant current source CS.
  • INCAS and INCASB are input terminals connected to the bases of cascode-connected transistors Q5 and Q6, INCAS1 and INCAS1B are input terminals connected to the bases of cascode-connected transistors Q3 and Q4, and IN and INB Is a terminal to which an input signal input to each base of the switching transistors Q1 and Q2 is applied.
  • the signal whose level is inverted in synchronization with these input signals is applied to the input terminals INCA and INCASB connected to the cascode-connected transistor pair Q5 and Q6 (see FIG. 6C).
  • signals having the same phase and different levels are applied to the input terminals INCAS1 and INCAS1B connected to the cascode-connected transistor pairs Q3 and Q4 in synchronization with the signals applied to the input terminals INCAS and INCASB (see FIG. 6D). .
  • the input terminals INCA1 and INCAS1B connected to the cascode-connected transistor pair Q3 and Q4 have a HIGH level ⁇ 3.4V, a LOW level ⁇ whose level is inverted in synchronization with the signal applied to the input terminals IN and INB.
  • a signal of 4.6V is applied (see FIG. 6D).
  • 6A to 6D and FIGS. 7A to 7C show signal waveforms at the respective terminals.
  • a signal having an amplitude of 3.5 V appears at the output terminal OUT (OUTB) (see FIG. 6A).
  • the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 2 V or less (see FIG. 7A).
  • the emitter-collector voltage VCE of the cascode-connected transistors Q5 and Q6 is 2V or less (see FIG. 7B), and the emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2V or less. (See Figure 7C). Accordingly, a transistor having a VCE breakdown voltage of 2 V can be used as a transistor to be used.
  • the cascode-connected transistor pair As described above, two cascode-connected transistor pairs are provided. Further, a signal whose level is inverted in synchronization with a signal input to the switching transistor pair is input to the cascode-connected transistor pair. Furthermore, when the output is at a high level (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the voltage applied to the switching transistor and the two transistors cascode-connected to the switching transistor is The input signal level to the cascode-connected transistor pair is set so as to be equally divided into the emitter-collector voltage VCE and the emitter-collector voltage VCE of the two cascode-connected transistors. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • the number of transistors that are cascode-connected to the switching transistors is two, but other numbers of transistors may be cascode-connected to the switching transistors.
  • FIG. 8 shows a driver circuit according to a fourth embodiment of the present invention.
  • the driver circuit shown in FIG. 8 includes emitter follower circuits 5a and 5b (first amplifying means and second amplifying means in the present invention) and an output circuit 15.
  • the output circuit 15 is configured using a differential circuit, and includes a switching transistor pair Q1, Q2 (first switching transistor and second switching transistor in the present invention), a cascode-connected transistor pair Q3, Q4, Q5.
  • the emitter follower circuit 5a includes an input terminal IN, input transistors Q9 and Q11, level shift diodes (transistors that are diode-connected) D1, D3, D5, D7, and D9, and current source resistors R3 and R5. .
  • the emitter follower circuit 5b includes an input terminal INB, input transistors Q10 and Q12, level shift diodes D2, D4, D6, D8, and D10, and current source resistors R4 and R6.
  • the outputs of the emitter follower circuits 5a and 5b are connected to the bases of the switching transistor pair Q1 and Q2 of the output circuit 15. Further, the signals of the emitters of the level-shifted diodes D8, D6, D4 of the emitter follower circuit 5b (a plurality of fourth signals in the present invention) are applied to the cascode-connected transistors Q3, Q5, Q7 of the output circuit 15. . Further, the signals of the emitters of the level-shifted diodes D7, D5, and D3 of the emitter follower circuit 5a (a plurality of second signals in the present invention) are applied to the cascode-connected transistors Q4, Q6, and Q8 of the output circuit 15. .
  • the signal input to the switching transistor Q1 and the signal whose level is inverted are added to the transistors Q3, Q5, and Q7.
  • a signal whose level is inverted from that of the signal input to the switching transistor Q2 is applied to the transistors Q4, Q6, and Q8.
  • the input signals of the transistor pairs Q3, Q4, Q5, Q6, Q7, and Q8 that are cascode-connected to the input signals of the switching transistor pair Q1 and Q2 of the output circuit 15 are synchronized by adjusting the wiring length.
  • the switching transistor pair Q1, Q2 of the output circuit 15 functions to switch the current of the constant current source CS.
  • the input signals of the cascode-connected transistors Q3, Q5, Q7 (Q4, Q6, Q8) are synchronized with the input signal of the switching transistor Q1 (Q2), but the logic level is inverted.
  • the input signals of transistors Q3, Q5, Q7 (Q4, Q6, Q8) are input signals using diodes D4, D6, D8, D10 (D3, D5, D7, D9) of emitter follower circuit 5b (5a). The level is determined.
  • the differential output terminal OUTB becomes HIGH level and the transistors Q1, Q3, Q5 and Q7 are applied with an equal voltage divided by using diodes D4, D6, D8, and D10 as VCE. Therefore, a lower voltage (a voltage of about 1/4 of the output amplitude) is applied between the emitter and collector of the transistors Q1, Q3, Q5, and Q7 with respect to the required output amplitude.
  • a plurality of cascode-connected transistor pairs are provided in the output circuit. Also, a signal whose level is changed by the level shift diode of the emitter follower circuit in the previous stage of the output circuit is generated, and the signal whose level is inverted in synchronization with the signal input to the switching transistor pair is cascode connected to the switching transistor pair Input to the transistor pair.
  • an emitter follower circuit having a plurality of level shift diodes is used to change the input level of a plurality of cascode-connected transistors, but other methods may be used.
  • the number of transistors that are cascode-connected to the switching transistors is three.
  • other numbers of transistors may be cascode-connected to the switching transistors.
  • the number of level shift diodes is appropriately changed according to the number of transistors cascode-connected to the switching transistors.
  • FIG. 9 is a circuit diagram showing a configuration of the driver circuit 16 according to the fifth embodiment of the present invention.
  • the driver circuit 16 shown in this figure is constituted by a distributed circuit.
  • the driver circuit 16 includes an input terminal IN, an input terminal INCAS, an input-side distributed constant transmission line 19 (input-side transmission line in the present invention), an input termination resistor Rin (input-side termination circuit in the present invention), an input Side bias circuit 18a, common-emitter transistor Q9 (amplifier circuit in the present invention), transistor Q10 cascode-connected to transistor Q9, input-side distributed constant transmission line 21 of transistor Q10, termination circuit for input-side distributed constant transmission line 21 (termination) Resistor) Rincas, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20 (output side transmission line in the present invention), output termination resistor Rout (output side termination circuit in the present invention), output side bias circuit 18c, output terminal Consists of OUT.
  • Vbin1 and Vbin2 are bias voltages, and V
  • a signal input from the input terminal IN propagates through the input-side distributed constant transmission line 19 in the direction of the input termination resistor Rin (forward direction). Most of the signals propagating in this way are sequentially distributed to the transistor Q9 and amplified.
  • the signal input to each transistor Q9 is amplified according to the current flowing through each transistor, and propagates through the output-side distributed constant transmission line 20 in the direction of the output terminal OUT. Further, since the electrical lengths in the respective propagation paths from the input terminal IN to the output terminal OUT are selected to be equal, the signals amplified by the transistors Q9 are sequentially synthesized by the output-side distributed constant transmission line 20. The amplified signal is output from the output terminal OUT.
  • a transistor whose logic is inverted in synchronization with a signal input from the input terminal IN is input from the input terminal INCAS to the transistor Q10 which is cascode-connected to the transistor Q9.
  • the input-side distributed constant transmission line 21 of the cascode-connected transistor Q10 is set so that the signal input to each emitter grounded transistor Q9 and the signal input to the transistor Q10 are distributed in synchronization.
  • 10A to 10E show signal waveforms at each terminal.
  • the power supply voltage VEE is 5V.
  • a signal having a HIGH level of 1.0 V and a LOW level of 0.5 V is applied to the input terminal IN on the grounded emitter transistor Q9 side (see FIG. 10C).
  • a HIGH level 2.8V signal and a LOW level 1.6V signal whose phases are inverted in synchronization with a signal applied to the input terminal IN are applied to the cascode-connected input terminal INCAS on the transistor Q10 side (see FIG. 10B).
  • a signal (see FIG. 10A) having an amplitude of 4.0 V appears at the output terminal OUT.
  • the emitter-collector voltage VCE of the common-emitter transistor Q9 is 2.6 V at the maximum (see FIG. 10E). Further, the emitter-collector voltage VCE of the cascode-connected transistor Q10 is also a maximum of 2.6 V or less (see FIG. 10D). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q9 and Q10 to be used.
  • the cascode-connected transistor Q10 is provided in the driver circuit configured by the distributed circuit. Further, a signal whose phase is inverted in synchronization with the signal input to the grounded emitter transistor Q9 is input to the transistor Q10. Furthermore, when the output is at a high level, the voltage applied to the transistor Q10 cascode-connected to the common-emitter transistor Q9 is equal to the emitter-collector voltage of the common-emitter transistor Q9 and the emitter-collector voltage of the cascode-connected transistor Q10.
  • the input signal level of the cascode-connected transistors is set so as to be divided. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • FIG. 11 shows a circuit diagram of a driver circuit 22 according to the sixth embodiment of the present invention.
  • 12A to 12C show waveforms at each terminal for explaining the operation.
  • the driver circuit shown in FIG. 11 includes a differential circuit 23 (first amplifying means in the present invention) and an output circuit 17 configured by a distributed circuit.
  • a differential data signal is input to the input terminals IN and INB, and a differential data signal having a gain and an amplitude for driving the output circuit 17 (the first signal and the first signal in the present invention). 2 signal) is output.
  • an input buffer circuit for converting a single-phase data signal into a differential data signal may be provided in the preceding stage of the differential circuit 23.
  • R1 and R2 are load resistors
  • Q1 and Q2 are transistors
  • CS is a constant current source.
  • the output circuit 17 is a distributed circuit. Specifically, the output circuit 17 includes an input side distributed constant transmission line 19, an input termination resistor Rin, an input side bias circuit 18a, a common emitter transistor Q9, a transistor Q10 cascode-connected to the common emitter transistor Q9, and an input of the transistor Q10. Side distributed constant transmission line 21, termination circuit (termination resistor) Rincas of input side distributed constant transmission line 21 of transistor Q10, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20, output termination resistor Rout, output side bias circuit 18c and an output terminal OUT.
  • termination circuit termination resistor
  • One of the outputs of the differential circuit 23 is connected to the input of the grounded emitter transistor (switching transistor) Q9 via the bias circuit 18a and the input-side distributed constant transmission line 19.
  • the other of the outputs of the differential circuit 23 is connected to the input of the cascode-connected transistor pair Q10 via the bias circuit 18b and the input-side distributed constant transmission line 21.
  • a signal whose phase is inverted is input to the transistor pair Q10 cascode-connected to the grounded emitter transistor (switching transistor) Q9 of the output circuit 17.
  • the operation will be described in the case of outputting an output amplitude of 4.0V.
  • the load resistors R1 and R2 of the differential circuit 23 and the constant current source CS are adjusted so that a signal with a HIGH level of 0 V and a LOW level of -1.0 V is output from the output terminal of the differential circuit 23.
  • the power supply voltage VEE of the output circuit 17 is set to 5V and the bias voltage Vbin1 of the bias circuit 18a on the input side of the grounded emitter transistor Q9 is set to 0.5V, the grounded transistor Q9 receives a signal of HIGH level 1.0V and LOW level 0V. Entered.
  • the bias voltage Vbin2 in the bias circuit 18b on the input side of the transistor Q10 cascode-connected to the grounded-emitter transistor Q9 is set to 2.2V
  • a signal of HIGH level 2.7V and LOW level 1.7V is applied to the cascode-connected transistor Q10.
  • the input signal of the grounded-emitter transistor Q9 and the input signal of the cascode-connected transistor Q10 are signals whose phases are inverted and synchronized.
  • 12A to 12C show waveforms at each terminal. An output waveform having a 4V amplitude is obtained at the output terminal OUT of the output circuit 17 (see FIG. 12A).
  • the voltage VCE (see FIG. 12C) applied between the emitter and collector of the grounded-emitter transistor Q9 and the voltage VCE (see FIG. 12B) applied between the emitter and collector of the cascode-connected transistor Q10 are 3V or less. .
  • a cascode-connected transistor is provided in an output circuit constituted by a distributed circuit. Further, the signal output from the differential circuit in the previous stage of the output circuit is set so that a signal whose phase is inverted from that of the signal input to the grounded emitter transistor is input to the cascode-connected transistor. In addition, when the input level of the common-emitter transistor is LOW, the input of the cascode-connected transistor is such that the emitter-collector voltage VCE of the switching transistor and the emitter-collector voltage VCE of the cascode-connected transistor are equal. Set the signal level. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
  • the transistor is formed of a bipolar transistor, but may be formed of a FET such as a MOS.
  • a driver circuit that drives a modulator used in a transmitter for optical communication has been described.
  • the present invention can also be applied to a power amplifier.
  • the driver circuit according to each of the above embodiments has the following common concept. That is, a cascode-connected transistor is provided for a transistor to which an input signal is input. In addition, a signal that is synchronized with the input signal of the transistor and whose phase is inverted is input to the input of the cascode-connected transistor. Further, when the emitter-collector voltage of the transistor is maximum (when the output is at a high level), the voltage applied to both ends of the circuit composed of the transistor connected to the transistor in cascode is connected to the emitter-collector voltage of the transistor in cascode connection. Is divided into the emitter-collector voltage of the transistor. Such a common concept is applied to a driver circuit constituted by a differential circuit and a driver circuit constituted by a distributed circuit.
  • the present invention is used in a driver circuit for driving an external modulator such as a dielectric modulator using a dielectric waveguide or an electroabsorption semiconductor modulator using light absorption of a semiconductor.
  • Input-side distributed constant transmission line 20 ... Output-side distributed constant transmission line 21 ... Cascade-connected transistor input-side distributed constant line Q1, Q2, Q9 ... Switching transistors Q3, Q4, Q5, Q6, Q7, Q8, Q10 ... transistor R1, R2 ... Load resistance Rin, Rout, Rincas ... Terminating resistor CS... Constant current source VEE ... Power supply voltage Vbin1, Vbin2 ... Bias voltage IN, INB, INCAS, INCASB, INCAS1, INCAS1B ... Input terminal OUT, OUTB ... Output terminals GND ... Ground

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Abstract

Provided is a driver circuit, which uses a low breakdown voltage device and can acquire a high output amplitude. The driver circuit includes a first switching transistor, to which an input signal is applied, and a first transistor cascade-connected with the switching transistor. A signal, which is synchronized with the input signal to the first switching transistor and inverted in level, is inputted to the input of the first transistor.

Description

ドライバー回路Driver circuit
　本発明は、光送信回路において使用されるドライバー回路に係わるものである。特に、本発明は、LiNbO3等の誘電体導波路を用いた誘電体変調器や、半導体の光吸収を利用した電界吸収型半導体変調器などの外部変調器を数V程度の電圧で駆動するドライバー回路に関するものである。 The present invention relates to a driver circuit used in an optical transmission circuit. In particular, the present invention drives an external modulator such as a dielectric modulator using a dielectric waveguide such as LiNbO 3 or an electroabsorption semiconductor modulator using light absorption of a semiconductor with a voltage of about several volts. It relates to the driver circuit.
　光通信システムにおいては、伝送路の大容量化に伴い変調速度の増大が急務である。レーザダイオードの直接変調では、比較的大きな波長チャーピングが伝送距離及び変調速度を制限するため、10Gb/s以上の高速通信や数ｋｍの通信には、高速チャーピングを生じさせにくい外部変調器が使用されている。外部光変調器として、LiNbO3や半導体を用いたマッハツェンダ光変調器（MZ光変調器）や電界吸収型変調器（EA光変調器）が使用されている。EA光変調器はMZ光変調器（駆動電圧４Ｖpp以上）よりも低電圧駆動が可能で小型化に適した光変調器であるものの、駆動電圧は２Vpp以上が必要である。従って、これらの変調器を駆動するドライバー回路には、高速動作と共に高い振幅出力が必要となる。 In an optical communication system, an increase in modulation speed is urgently required with an increase in transmission line capacity. In direct modulation of laser diodes, the relatively large wavelength chirping limits the transmission distance and modulation speed. For high-speed communication of 10 Gb / s or higher, or for communication of several kilometers, there is an external modulator that is unlikely to cause high-speed chirping. in use. As an external optical modulator, a Mach-Zehnder optical modulator (MZ optical modulator) or an electroabsorption modulator (EA optical modulator) using LiNbO 3 or a semiconductor is used. Although the EA optical modulator can be driven at a lower voltage than the MZ optical modulator (driving voltage 4 V pp or more) and is suitable for downsizing, the driving voltage needs to be 2 V pp or more. Therefore, a driver circuit for driving these modulators requires high amplitude output as well as high speed operation.
　光変調器を駆動するドライバー回路としては、一般には図１３に示すようなECL(Emitter-coupled logic)やSCFL（Source-coupled FET (Field Effect Transistor) logic）の差動アンプ構成が知られている。
　また、差動アンプ構成の回路として特許文献１～特許文献３に記載される回路が知られている。図１３は、特許文献１に記載された差動アンプ構成を採用したドライバー回路を示す回路図である。このドライバー回路は、2段の入力バッファ回路2、3と1段の出力回路1から構成されている。GNDは接地端子、VEEは電源電圧、IN0は入力端子、R1、R2は負荷抵抗、Q1～Q4はトランジスタ、CSは定電流源、VCASは電圧端子、Iは電流源CSを流れる電流、OUTとOUTBは差動出力端子である。この特許文献１に記載されたドライバー回路の動作を簡単に説明する。単相信号である入力信号が入力端子IN0に加えられ、入力バッファ回路2で単相信号が差動の両相信号に変換される。入力バッファ回路2の出力信号は、差動アンプであるバッファ回路3において増幅され、エミッタフォロワ回路等を介して最終出力段の出力回路1へ受け渡される。出力回路1は、スイッチングするトランジスタQ1、Q2のミラー容量を低減し帯域を向上させるために、スイッチングするトランジスタQ1、Q2のコレクタ側にベースを接地したトランジスタQ3、Q4を縦積みにしたカスコード型アンプである。 As a driver circuit for driving an optical modulator, a differential amplifier configuration such as ECL (Emitter-coupled logic) or SCFL (Source-coupled FET (Field Effect Transistor) logic) as shown in FIG. 13 is generally known. .
Further, circuits described in Patent Documents 1 to 3 are known as circuits having a differential amplifier configuration. FIG. 13 is a circuit diagram showing a driver circuit employing the differential amplifier configuration described in Patent Document 1. In FIG. This driver circuit is composed of two stages of input buffer circuits 2 and 3 and one stage of output circuit 1. GND is the ground terminal, VEE is the power supply voltage, IN0 is the input terminal, R1 and R2 are load resistors, Q1 to Q4 are transistors, CS is a constant current source, VCAS is the voltage terminal, I is the current flowing through the current source CS, and OUT OUTB is a differential output terminal. The operation of the driver circuit described in Patent Document 1 will be briefly described. An input signal that is a single-phase signal is applied to the input terminal IN0, and the input buffer circuit 2 converts the single-phase signal into a differential two-phase signal. The output signal of the input buffer circuit 2 is amplified in the buffer circuit 3 that is a differential amplifier, and is passed to the output circuit 1 in the final output stage via an emitter follower circuit or the like. The output circuit 1 is a cascode amplifier in which transistors Q3 and Q4, whose bases are grounded on the collector side of the switching transistors Q1 and Q2, are vertically stacked in order to reduce the mirror capacitance of the switching transistors Q1 and Q2 and improve the bandwidth. It is.
特開２００６－３３９７７１号公報JP 2006-339771 A 特表２００５－５２９５０５号公報JP 2005-529505 A 特開２００６－１５７６４９号公報JP 2006-157649 A
　ところで、集積回路に使用される半導体デバイスでは微細化が進み、MOS (Metal Oxide Semiconductor) の電流利得遮断周波数は100GHz以上にも達している。また、SiGe HBT (Hetero-junction Bipolar Transistor) やInP系デバイスでは、300GHz以上のfTが実現されており、集積回路の高速化が図られている。しかしながらその反面、デバイスの耐圧は低下しており、デバイスの高速化と高耐圧はトレードオフの関係にある。
　光変調器を駆動するドライバー回路では、構成する半導体デバイスの特性には高速化と共に、高振幅化の観点から高耐圧が要求される。10Gb/s以上のドライバー回路は、現在、耐圧が4V以上あるGaAs系のHEMT (High Electron Mobility Transistor) やHBT、InP系のダブルHBTに限定されて使用されている。 By the way, miniaturization has progressed in semiconductor devices used in integrated circuits, and the current gain cutoff frequency of MOS (Metal Oxide Semiconductor) has reached 100 GHz or more. In addition, SiGe HBTs (Hetero-junction Bipolar Transistors) and InP-based devices have achieved fT of 300 GHz or higher, and the speed of integrated circuits has been increased. On the other hand, the breakdown voltage of the device is decreasing, and there is a trade-off between increasing the speed of the device and increasing the breakdown voltage.
In a driver circuit for driving an optical modulator, a high breakdown voltage is required from the viewpoint of increasing the speed and increasing the amplitude of the characteristics of a semiconductor device to be configured. Driver circuits of 10 Gb / s or higher are currently limited to GaAs HEMT (High Electron Mobility Transistor), HBT, and InP double HBT with a breakdown voltage of 4 V or higher.
　ここで、ドライバー回路のデバイスにかかる電圧と耐圧の関係を説明する。
図１４にカスコード接続を有しない通常の差動アンプで構成された変調器ドライバー回路の出力回路１ａを示す。図１５Ａ～図１５Ｂは、出力回路１ａの各端子の信号波形を示している。図１４において、Ｑ１とＱ２はスイッチングするトランジスタである。抵抗R1、R2は出力振幅を生成するための負荷抵抗で、これらの負荷抵抗と外部負荷（変調器の内部抵抗）及び定電流源CSの電流Iとで出力振幅がきまる。図１４のドライバー回路の出力回路１ａにおいて、必要な出力振幅を4.9V以上とすると、出力端子OUTB側（図１５Ａ参照）がHIGHレベルになるとスイッチングトランジスタＱ1のエミッタ－コレクタ間の電圧(VCE)として6Ｖの電位が印加される（図１５Ｂ参照）。従って、スイッチングトランジスタＱ１、Ｑ２には6V以上のVCE耐圧が必要となる。 Here, the relationship between the voltage applied to the device of the driver circuit and the withstand voltage will be described.
FIG. 14 shows an output circuit 1a of a modulator driver circuit composed of a normal differential amplifier having no cascode connection. 15A to 15B show signal waveforms at the respective terminals of the output circuit 1a. In FIG. 14, Q1 and Q2 are switching transistors. The resistors R1 and R2 are load resistors for generating an output amplitude, and the output amplitude is determined by these load resistors, the external load (the internal resistance of the modulator), and the current I of the constant current source CS. In the output circuit 1a of the driver circuit of FIG. 14, if the required output amplitude is 4.9 V or more, the voltage between the emitter and collector (VCE) of the switching transistor Q1 becomes high when the output terminal OUTB side (see FIG. 15A) becomes HIGH level. A potential of 6V is applied (see FIG. 15B). Therefore, the switching transistors Q1 and Q2 require a VCE breakdown voltage of 6V or more.
　図１６のカスコード型の回路１においても、4.7Vの出力振幅を得るためには、カスコード接続されたトランジスタＱ３、Ｑ４のベース電位は-4.4V程度（出力振幅程度）に接地する。そのために出力端子OUTB（図１７Ａ参照）側がHIGHレベルになると、スイッチングトランジスタQ1のVCE（図１７Ｃ参照）は1.1V程度であるのに対し、カスコード接続されたトランジスタQ3にはVCEとして5Ｖの電位が印加される（図１７Ｂ参照）。従ってカスコード接続されたトランジスタQ3、Q4には5V以上のVCE耐圧が必要となる。 Also in the cascode circuit 1 of FIG. 16, in order to obtain an output amplitude of 4.7V, the base potentials of the cascode-connected transistors Q3 and Q4 are grounded to about -4.4V (about the output amplitude). For this reason, when the output terminal OUTB (see FIG. 17A) becomes HIGH level, the VCE of the switching transistor Q1 (see FIG. 17C) is about 1.1V, whereas the cascode-connected transistor Q3 has a potential of 5V as VCE. Applied (see FIG. 17B). Therefore, the cascode-connected transistors Q3 and Q4 require a VCE breakdown voltage of 5V or more.
　本発明は、このような事情に鑑みてなされたもので、その目的は、耐圧の低いデバイスを使用し、しかも高出力振幅を得ることができるドライバー回路を提供することにある。 The present invention has been made in view of such circumstances, and an object of the present invention is to provide a driver circuit that uses a device having a low withstand voltage and can obtain a high output amplitude.
　上述した課題を解決するために、本発明は、入力信号が加えられる第１のスイッチングトランジスタと、前記第１のスイッチングトランジスタにカスコード接続された第１のトランジスタとを具備し、前記第１のトランジスタの入力に前記第１のスイッチングトランジスタへの前記入力信号に同期し、かつ、レベルが反転した信号を入力するドライバー回路である。
　また、本発明は、入力信号をスイッチングトランジスタへ加え、前記スイッチングトランジスタへの前記入力信号に同期し、かつ、レベルが反転した信号を前記スイッチングトランジスタにカスコード接続されたトランジスタの入力へ加える方法である。 In order to solve the above-described problem, the present invention includes a first switching transistor to which an input signal is applied, and a first transistor cascode-connected to the first switching transistor, and the first transistor Is a driver circuit that inputs a signal whose level is inverted in synchronization with the input signal to the first switching transistor.
Further, the present invention is a method of adding an input signal to a switching transistor, and applying a signal whose level is inverted and synchronized with the input signal to the switching transistor to the input of the transistor cascode-connected to the switching transistor. .
　以上説明したように、この発明によれば、出力振幅に相当する電圧が、スイッチングトランジスタのエミッタ-コレクタ間電圧とこのスイッチングトランジスタにカスコード接続されたトランジスタのエミッタ-コレクタ間電圧とに分割される。これにより、耐圧の低いデバイスを使用し、しかも高出力振幅を得ることができる。 As described above, according to the present invention, the voltage corresponding to the output amplitude is divided into the emitter-collector voltage of the switching transistor and the emitter-collector voltage of the transistor cascode-connected to the switching transistor. As a result, a device with a low breakdown voltage can be used and a high output amplitude can be obtained.
本発明の第１実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of 1st Embodiment of this invention. 同第１実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 1st embodiment. 同第１実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 1st embodiment. 同第１実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 1st embodiment. 同第１実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 1st embodiment. 同第１実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 1st embodiment. 本発明の第２実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of 2nd Embodiment of this invention. 同第２実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 2nd embodiment. 同第２実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 2nd embodiment. 同第２実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 2nd embodiment. 同第２実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 2nd embodiment. 本発明の第３の実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of the 3rd Embodiment of this invention. 同第３実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３の実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３の実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 同第３の実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 3rd embodiment. 本発明の第４実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of 4th Embodiment of this invention. 本発明の第５実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of 5th Embodiment of this invention. 同第５実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 5th embodiment. 同第５実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 5th embodiment. 同第５実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 5th embodiment. 同第５実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 5th embodiment. 同第５実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 5th embodiment. 本発明の第６実施形態の構成を示す回路図である。It is a circuit diagram which shows the structure of 6th Embodiment of this invention. 同第６実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 6th embodiment. 同第６実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 6th embodiment. 同第６実施形態の動作を説明するための波形図である。It is a wave form chart for explaining operation of the 6th embodiment. 関連するドライバー回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of a related driver circuit. 関連する差動回路の構成例を示す回路図である。It is a circuit diagram which shows the structural example of a related differential circuit. 同差動回路の動作を説明するための波形図である。It is a wave form diagram for demonstrating operation | movement of the differential circuit. 同差動回路の動作を説明するための波形図である。It is a wave form diagram for demonstrating operation | movement of the differential circuit. 関連するドライバー回路の他の構成例を示す回路図である。It is a circuit diagram which shows the other structural example of a related driver circuit. 同ドライバー回路の動作を説明するための波形図である。It is a wave form diagram for demonstrating operation | movement of the driver circuit. 同ドライバー回路の動作を説明するための波形図である。It is a wave form diagram for demonstrating operation | movement of the driver circuit. 同ドライバー回路の動作を説明するための波形図である。It is a wave form diagram for demonstrating operation | movement of the driver circuit.
　以下、図面を参照し、本発明の実施形態について説明する。
（第1実施形態）
　図１は本発明の第1実施形態に従ったドライバー回路１１の構成を示す回路図である。この図に示すドライバー回路１１は差動回路を用いて構成されている。GNDは接地端子、VEEは電源電圧、IN、INBは入力端子、OUTとOUTBは変調器（図示せず）を駆動する振幅を持つ信号を出力する差動出力端子である。Q1とQ2（本発明における第１のスイッチングトランジスタおよび第２のスイッチングトランジスタ）はスイッチングするトランジスタ対で、Q3とQ4（本発明における第１のトランジスタおよび第２のトランジスタ）はそれぞれトランジスタQ1，Q2にカスコード接続されたトランジスタである。CSは定電流源であり、トランジスタQ1、Q2のエミッタと電源電圧VEEとの間に接続されており、Iは定電流源CSを流れる電流である。トランジスタQ3、Q4の各コレクタと接地端子GNDとの間に接続された抵抗R1、R2は出力振幅を持つ信号を生成するための負荷抵抗である。これらの負荷抵抗と外部負荷（変調器の内部抵抗）及び定電流源CSに流れる電流Iとで出力振幅がきまる。INCASとINCASBはカスコード接続されたトランジスタQ3とQ4の各ベースに接続された入力端子である。スイッチングトランジスタQ1とQ2のベースに接続される入力端子INとINBには、変調器を駆動するデータ信号が入力される。これらのデータ信号と同期してレベルが反転された信号が、カスコード接続されたトランジスタQ3とQ4の各ベースに接続された入力端子INCASとINCASBに入力される。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a driver circuit 11 according to the first embodiment of the present invention. The driver circuit 11 shown in this figure is configured using a differential circuit. GND is a ground terminal, VEE is a power supply voltage, IN and INB are input terminals, and OUT and OUTB are differential output terminals for outputting a signal having an amplitude for driving a modulator (not shown). Q1 and Q2 (first switching transistor and second switching transistor in the present invention) are switching transistor pairs, and Q3 and Q4 (first transistor and second transistor in the present invention) are respectively connected to transistors Q1 and Q2. A cascode-connected transistor. CS is a constant current source, which is connected between the emitters of the transistors Q1 and Q2 and the power supply voltage VEE, and I is a current flowing through the constant current source CS. Resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND are load resistors for generating a signal having an output amplitude. The output amplitude is determined by the load resistance, the external load (the internal resistance of the modulator), and the current I flowing through the constant current source CS. INCAS and INCASB are input terminals connected to the bases of the cascode-connected transistors Q3 and Q4. Data signals for driving the modulator are input to input terminals IN and INB connected to the bases of the switching transistors Q1 and Q2. Signals whose levels are inverted in synchronization with these data signals are input to input terminals INCAS and INCASB connected to the bases of cascode-connected transistors Q3 and Q4.
　ここで、動作について説明する。図2A～図2Eは各端子における信号波形を示す。電源電圧VEEを-7Vとする。スイッチングトランジスタQ1とQ2に接続された入力端子INとINBに、HIGHレベル-5.1V、LOWレベル-5.5V、かつ、互いに位相が反転した信号を与える（図2B参照）。また、カスコード接続されたトランジスタQ3とQ4に接続された入力端子INCASとINCASBには、それぞれ入力端子INとINBに与えられる信号に同期してレベルが反転したHIGHレベル-2.4V、LOWレベル-4.2Vの信号を与える（図2C参照）。出力端子OUTB（OUT）には4.6Vの振幅を持つ信号（図2A参照）が現れている。一方、スイッチングトランジスタQ1とQ2のエミッタ-コレクタ間電圧VCEは、最大3.0Vになっている（図2D参照）。また、カスコード接続されたトランジスタQ3とQ4のエミッタ-コレクタ電圧VCEも最大2.9Vになっている（図2E参照）。従って、使用するトランジスタQ1～Q4として、3VのVCE耐圧を有するものを適用することができる。 Here, the operation will be described. 2A to 2E show signal waveforms at each terminal. Set the power supply voltage VEE to -7V. Signals having a HIGH level of -5.1 V, a LOW level of -5.5 V, and phases inverted from each other are applied to the input terminals IN and INB connected to the switching transistors Q1 and Q2 (see FIG. 2B). In addition, the input terminals INCAS and INCASB connected to the cascode-connected transistors Q3 and Q4 have a HIGH level of -2.4V and a LOW level of -4.2 which are inverted in synchronization with the signals applied to the input terminals IN and INB, respectively. Give a V signal (see Figure 2C). A signal having an amplitude of 4.6 V (see FIG. 2A) appears at the output terminal OUTB (OUT). On the other hand, the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 3.0 V at the maximum (see FIG. 2D). The emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2.9 V at maximum (see FIG. 2E). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q1 to Q4 to be used.
　ここで、端子IN、INB、INCAS、INCASBの電圧の関係を求める。端子INにHIGHレベルの信号が入力され、端子INBにLOWレベルの信号が入力される場合を考える。定電流源CSにかかる電圧をVCSとし、出力振幅をVRとする。トランジスタQ1とQ2のエミッタの電圧VAは、
　　　VA=VEE+VCSとなる。トランジスタがONとなるエミッタ-ベース間電圧をVB、エミッタ-コレクタ間電圧をVEとし、トランジスタがOFFになるエミッタ-ベース間電圧をVBO、エミッタ-コレクタ間電圧をVEOとし、トランジスタQ1,Q3（Q2、Q4）がONの時の抵抗R1(R2)の両端電圧をVRとすると、
　　　2×VE=-VA-VR、2×VEO=-VAなる関係式が成り立つ。 Here, the relationship between the voltages of the terminals IN, INB, INCAS, and INCASB is obtained. Consider a case where a high level signal is input to the terminal IN and a low level signal is input to the terminal INB. The voltage applied to the constant current source CS is VCS, and the output amplitude is VR. The voltage VA at the emitters of transistors Q1 and Q2 is
VA = VEE + VCS. The emitter-base voltage when the transistor is turned on is VB, the emitter-collector voltage is VE, the emitter-base voltage when the transistor is turned off is VBO, the emitter-collector voltage is VEO, and transistors Q1, Q3 (Q2 , Q4) When the voltage across resistor R1 (R2) when ON is VR,
The relational expressions 2 × VE = -VA-VR and 2 × VEO = -VA hold.
　また、
　　　端子INにかかる電圧は、VA-VB
　　　端子INCASにかかる電圧は、VA-VE-VB
　　　端子INBにかかる電圧は、VA-VBO
　　　端子INCASBにかかる電圧は、VA-VEO-VBOとなる。以上が成り立つように端子IN、端子INBと端子INCAS、端子INCASBのHIGHレベルとLOWレベルの電圧を設定すれば、出力がHIGHレベルの時に、電圧VAがスイッチングトランジスタQ1(Q2)のエミッタ－コレクタ間とカスコード接続されたトランジスタQ3(Q4)のエミッタ－コレクタ間に均等にかかる。 Also,
The voltage applied to terminal IN is VA-VB
The voltage applied to the terminal INCAS is VA-VE-VB
The voltage applied to terminal INB is VA-VBO
The voltage applied to the terminal INCASB is VA-VEO-VBO. If the HIGH and LOW level voltages of the terminal IN, the terminal INB and the terminal INCAS, and the terminal INCASB are set so that the above holds, the voltage VA is between the emitter and collector of the switching transistor Q1 (Q2) when the output is high. And evenly between the emitter and collector of the cascode-connected transistor Q3 (Q4).
　以上、説明したように、カスコード接続されたトランジスタQ3、Q4を設ける。また、スイッチングトランジスタQ1、Q2に入力される信号と同期してレベルが反転した信号をトランジスタQ3およびQ4に入力する。さらに、出力がHIGHレベルの時（すなわち、スイッチングトランジスタQ1(Q2)のエミッターコレクタ間電圧が最大時）に、スイッチングトランジスタQ1(Q2)とカスコード接続したトランジスタQ3(Q4)にかかる電圧がスイッチングトランジスタのエミッタ－コレクタ間電圧とカスコード接続されたトランジスタのエミッタ－コレクタ間電圧に均等に分割されるように、カスコード接続されたトランジスタ対のベースへの入力信号レベルを設定する。これによって、出力振幅より低い耐圧をもつトランジスタを適用することができる。  As described above, cascode-connected transistors Q3 and Q4 are provided. In addition, signals whose levels are inverted in synchronization with the signals input to the switching transistors Q1 and Q2 are input to the transistors Q3 and Q4. Furthermore, when the output is at a high level (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the voltage applied to the transistor Q3 (Q4) cascode-connected to the switching transistor Q1 (Q2) The input signal level to the base of the cascode-connected transistor pair is set so as to be equally divided into the emitter-collector voltage and the emitter-collector voltage of the cascode-connected transistor. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
（第２実施形態）
　図3に本発明の第２実施形態にかかるドライバー回路１２の回路図を示す。また、図4A～図4Dには、動作を説明するための各端子の波形を示す。図3に示すドライバー回路１２は、入力バッファ回路2（本発明における第１の増幅手段）と、２つのバッファ回路3、4（本発明における第２の増幅手段および第３の増幅手段）及び差動回路を用いて構成された出力回路１３で構成されている。入力バッファ回路2では、入力端子IN0に入力された単相のデータ信号が両相の差動データ信号に変換されて、２つのバッファ回路3、4に入力される。出力回路1３は、差動回路で構成されており、スイッチングトランジスタ対Q1、Q2、これらのスイッチングトランジスタQ1,Q2にそれぞれカスコード接続されたトランジスQ3、Q4、接地端子GND、電源電圧VEE、変調器を駆動する振幅を持つ信号を出力する差動出力端子OUT、OUTB、トランジスタQ3、Q4のコレクタおよび接地端子GND間に接続された負荷抵抗R1、R2、トランジスタQ1、Q2のエミッタと電源電圧VEEの間に接続された定電流源CSから構成されている。 (Second Embodiment)
FIG. 3 shows a circuit diagram of the driver circuit 12 according to the second embodiment of the present invention. 4A to 4D show waveforms of terminals for explaining the operation. The driver circuit 12 shown in FIG. 3 includes an input buffer circuit 2 (first amplification means in the present invention), two buffer circuits 3 and 4 (second amplification means and third amplification means in the present invention), and a difference. The output circuit 13 is configured using a dynamic circuit. In the input buffer circuit 2, the single-phase data signal input to the input terminal IN0 is converted into a differential data signal of both phases and input to the two buffer circuits 3 and 4. The output circuit 13 is composed of a differential circuit, and includes a pair of switching transistors Q1 and Q2, transistors Q3 and Q4 cascode-connected to these switching transistors Q1 and Q2, ground terminal GND, power supply voltage VEE, and a modulator, respectively. Between differential output terminals OUT and OUTB that output signals with the driving amplitude, load resistors R1 and R2 connected between the collectors of the transistors Q3 and Q4 and the ground terminal GND, and the emitters of the transistors Q1 and Q2 and the power supply voltage VEE It is comprised from the constant current source CS connected to.
　スイッチングトランジスタ対Q1、Q2のベースには、バッファ回路3の差動出力（本発明における第１の信号および第２の信号）が接続されている。また、カスコード接続されたトランジスタ対Q3、Q4のベースには、バッファ回路3の差動出力とはそれぞれレベルが反転したバッファ回路4の差動出力（本発明における第３の信号および第４の信号）が接続されている。ここで、例えば4.6V以上の出力振幅を出力する場合について、動作を説明する。出力回路1３の電源電圧VEEを-7Vとする。入力バッファ回路2の入力端にHIGHレベルが0V、LOWレベル-0.5Vの信号が入力される（図4B参照）と、出力回路１３のスイッチングトランジスタ対Q1、Q2には、HIGHレベルが-5.1V、LOWレベルが-5.5Vの信号が、バッファ回路3を通して入力される。一方、出力回路1３のカスコード接続されたトランジスタ対Q3、Q4には、HIGHレベルが-2.4V、LOWレベルが-4.2Vの信号が、バッファ回路4を通して増幅されて入力される。この場合、スイッチングトランジスタQ1（Q2）への入力信号と、カスコード接続されたトランジスタQ3（Q4）への入力信号は、それぞれ論理が反転しているが同期が取られている。図4A～図4Dは各端子の波形を示している。出力回路１３の出力端子OUTBには、4.6V振幅の出力波形が得られている（図4A参照）。一方、スイッチングトランジスタQ1のエミッタ-コレクタ間にかかる電圧VCEと、カスコード接続されたトランジスタQ3のエミッタ-コレクタ間にかかる電圧VCEは、3V以下になっている（図4C及び図4D参照）。 The differential outputs of the buffer circuit 3 (the first signal and the second signal in the present invention) are connected to the bases of the switching transistor pair Q1, Q2. The bases of the cascode-connected transistor pairs Q3 and Q4 have differential outputs of the buffer circuit 4 whose levels are inverted from the differential outputs of the buffer circuit 3 (the third signal and the fourth signal in the present invention). ) Is connected. Here, for example, the operation will be described in the case of outputting an output amplitude of 4.6 V or more. The power supply voltage VEE of the output circuit 13 is set to -7V. When a signal with a HIGH level of 0V and a LOW level of -0.5V is input to the input terminal of the input buffer circuit 2 (see FIG. 4B), the switching transistor pair Q1, Q2 of the output circuit 13 has a HIGH level of -5.1V. A signal whose LOW level is −5.5 V is input through the buffer circuit 3. On the other hand, a signal having a HIGH level of −2.4 V and a LOW level of −4.2 V is amplified and inputted through the buffer circuit 4 to the cascode-connected transistor pair Q3 and Q4 of the output circuit 13. In this case, the input signal to the switching transistor Q1 (Q2) and the input signal to the cascode-connected transistor Q3 (Q4) are synchronized, although the logic is inverted. 4A to 4D show waveforms at each terminal. An output waveform with an amplitude of 4.6 V is obtained at the output terminal OUTB of the output circuit 13 (see FIG. 4A). On the other hand, the voltage VCE applied between the emitter and collector of the switching transistor Q1 and the voltage VCE applied between the emitter and collector of the cascode-connected transistor Q3 are 3 V or less (see FIGS. 4C and 4D).
　以上、説明したように、カスコード接続されたトランジスタを出力回路に設ける。また、出力回路の前段にあるバッファ回路で、スイッチングトランジスタに入力される信号と同期してレベルが反転した信号を生成してカスコード接続されたトランジスタに入力する。その際、スイッチングトランジスタの入力レベルがLOWレベルの時（すなわち、スイッチングトランジスタQ1(Q2)のエミッターコレクタ間電圧が最大時）に、スイッチングトランジスタのエミッタ－コレクタ間電圧VCEとカスコード接続されたトランジスタのエミッタ－コレクタ間電圧VCEが均等になるように、カスコード接続されたトランジスタのベースへの入力信号レベルを設定する。これによって、出力振幅より低い耐圧のトランジスタを適用することができる。 As described above, a cascode-connected transistor is provided in the output circuit. In addition, the buffer circuit in the preceding stage of the output circuit generates a signal whose level is inverted in synchronization with the signal input to the switching transistor and inputs the signal to the cascode-connected transistor. At that time, when the input level of the switching transistor is LOW (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the emitter of the transistor cascode-connected with the emitter-collector voltage VCE of the switching transistor. Set the input signal level to the base of the cascode-connected transistors so that the collector-to-collector voltage VCE is equal. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
（第３実施形態）
　図5に本発明の第3実施形態にかかるドライバー回路１４を示す。また、図6A～図6D、図7A～図7Cには、動作を説明するための各端子の波形を示す。図5に示すドライバー回路１４は、差動回路で構成されており、スイッチングトランジスタ対Q1、Q2、これらのトランジスタ対Q1、Q2にカスコード接続された2つのトランジス対Q3、Q4およびQ5、Q6、接地端子GND、電源電圧VEE、変調器を駆動する振幅を持つ信号を出力する差動出力端子OUT、OUTB、負荷抵抗R1、R2、定電流源CSから構成されている。また、INCASとINCASBはカスコード接続されたトランジスタQ5とQ6の各ベースに接続された入力端子、INCAS1、INCAS1Bは、カスコード接続されたトランジスタQ3とQ4の各ベースに接続された入力端子、INとINBは、スイッチングトランジスタQ1とQ2の各ベースに入力される入力信号が加えられる端子である。 (Third embodiment)
FIG. 5 shows a driver circuit 14 according to a third embodiment of the present invention. FIGS. 6A to 6D and FIGS. 7A to 7C show waveforms of terminals for explaining the operation. The driver circuit 14 shown in FIG. 5 is composed of a differential circuit, and includes a pair of switching transistors Q1, Q2, two transistor pairs Q3, Q4 and Q5, Q6 cascode-connected to these transistor pairs Q1, Q2, ground It consists of a terminal GND, a power supply voltage VEE, differential output terminals OUT and OUTB that output a signal having an amplitude for driving the modulator, load resistors R1 and R2, and a constant current source CS. INCAS and INCASB are input terminals connected to the bases of cascode-connected transistors Q5 and Q6, INCAS1 and INCAS1B are input terminals connected to the bases of cascode-connected transistors Q3 and Q4, and IN and INB Is a terminal to which an input signal input to each base of the switching transistors Q1 and Q2 is applied.
　これらの入力信号（図６Ｂ参照）と同期してレベルが反転された信号が、カスコード接続されたトランジスタ対Q5とQ6に接続された入力端子INCASおよびINCASBに加えられる（図6C参照）。また、入力端子INCAS、INCASBに加えられる信号と同期し、同相で、レベルが異なる信号が、カスコード接続されたトランジスタ対Q3とQ4に接続された入力端子INCAS1、INCAS1Bに加えられる（図６Ｄ参照）。 The signal whose level is inverted in synchronization with these input signals (see FIG. 6B) is applied to the input terminals INCA and INCASB connected to the cascode-connected transistor pair Q5 and Q6 (see FIG. 6C). In addition, signals having the same phase and different levels are applied to the input terminals INCAS1 and INCAS1B connected to the cascode-connected transistor pairs Q3 and Q4 in synchronization with the signals applied to the input terminals INCAS and INCASB (see FIG. 6D). .
　ここで、例えば3.5V以上の出力振幅を出力する場合について、動作を説明する。電源電圧VEEを-7Vとする。スイッチングトランジスタQ1とQ2に接続された入力端子INとINBに、HIGHレベル-5.1V、LOWレベル-5.4Vの信号を与える（図６Ｂ参照）。また、カスコード接続されたトランジスタ対Q5とQ6に接続された入力端子INCASとINCASBにそれぞれ入力端子INとINBへ与えられる信号に同期してレベルが反転したHIGHレベル-1.4V、LOWレベル-3.3Vの信号を与える（図６Ｃ参照）。また、カスコード接続されたトランジスタ対Q3とQ4に接続された入力端子INCAS1とINCAS1Bには、同じく入力端子INとINBへ与えられる信号に同期してレベルが反転したHIGHレベル-3.4V、LOWレベル-4.6Vの信号を与える（図６Ｄ参照）。図6A～図6D、図7A～図7Cに各端子における信号波形を示す。出力端子OUT（OUTB）には3.5Vの振幅を持つ信号が現れている（図6A参照）。一方、スイッチングトランジスタQ1とQ2のエミッタ-コレクタ間電圧VCEは、2V以下になっている（図7A参照）。また、カスコード接続されたトランジスタQ5とQ6のエミッタ-コレクタ間電圧VCEも2V以下になっており（図7B参照）、カスコード接続されたトランジスタQ3とQ4のエミッタ-コレクタ間電圧VCEも２V以下になっている（図7C参照）。従って、使用するトランジスタとしては、2VのVCE耐圧を有するものを適用することができる。 Here, for example, the operation will be described in the case of outputting an output amplitude of 3.5 V or more. Set the power supply voltage VEE to -7V. Signals of HIGH level -5.1V and LOW level -5.4V are given to input terminals IN and INB connected to switching transistors Q1 and Q2 (see FIG. 6B). Also, HIGH level -1.4V, LOW level -3.3V, with the levels inverted in synchronization with the signals applied to input terminals IN and INB, respectively, at input terminals INCA and INCASB connected to cascode-connected transistor pair Q5 and Q6 (See FIG. 6C). Similarly, the input terminals INCA1 and INCAS1B connected to the cascode-connected transistor pair Q3 and Q4 have a HIGH level −3.4V, a LOW level − whose level is inverted in synchronization with the signal applied to the input terminals IN and INB. A signal of 4.6V is applied (see FIG. 6D). 6A to 6D and FIGS. 7A to 7C show signal waveforms at the respective terminals. A signal having an amplitude of 3.5 V appears at the output terminal OUT (OUTB) (see FIG. 6A). On the other hand, the emitter-collector voltage VCE of the switching transistors Q1 and Q2 is 2 V or less (see FIG. 7A). Also, the emitter-collector voltage VCE of the cascode-connected transistors Q5 and Q6 is 2V or less (see FIG. 7B), and the emitter-collector voltage VCE of the cascode-connected transistors Q3 and Q4 is also 2V or less. (See Figure 7C). Accordingly, a transistor having a VCE breakdown voltage of 2 V can be used as a transistor to be used.
　以上、説明したように、２つのカスコード接続されたトランジスタ対を設ける。また、スイッチングトランジスタ対に入力される信号と同期してレベルが反転した信号をカスコード接続されたトランジスタ対に入力する。さらに、出力がHIGHレベルの時（すなわち、スイッチングトランジスタQ1(Q2)のエミッターコレクタ間電圧が最大時）に、スイッチングトランジスタとこのスイッチングトランジスタにカスコード接続した２個のトランジスタにかかる電圧が、スイッチングトランジスタのエミッタ-コレクタ間電圧VCEと２つのカスコード接続されたトランジスタのエミッタ-コレクタ間電圧VCEに均等に分割されるように、カスコード接続されたトランジスタ対への入力信号レベルを設定する。これによって、出力振幅より低い耐圧をもつトランジスタを適用することができる。
　なお、上述した説明では、スイッチングトランジスタにカスコード接続されたトランジスタの数を２としたが、これ以外の数のトランジスタをスイッチングトランジスタにカスコード接続しても良い。 As described above, two cascode-connected transistor pairs are provided. Further, a signal whose level is inverted in synchronization with a signal input to the switching transistor pair is input to the cascode-connected transistor pair. Furthermore, when the output is at a high level (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the voltage applied to the switching transistor and the two transistors cascode-connected to the switching transistor is The input signal level to the cascode-connected transistor pair is set so as to be equally divided into the emitter-collector voltage VCE and the emitter-collector voltage VCE of the two cascode-connected transistors. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
In the above description, the number of transistors that are cascode-connected to the switching transistors is two, but other numbers of transistors may be cascode-connected to the switching transistors.
（第４実施形態）
　図8に、本発明の第４実施形態にかかるドライバー回路を示す。図8に示すドライバー回路は、エミッタフォロワ回路5a、5b（本発明における第１の増幅手段および第２の増幅手段）と、出力回路１５から構成されている。出力回路１５は、差動回路を用いて構成されており、スイッチングトランジスタ対Q1、Q2（本発明における第１のスイッチングトランジスタおよび第２のスイッチングトランジスタ）、カスコード接続されたトランジス対Q3、Q4、Q5、Q6、Q7、Q8（本発明における第１のトランジスタおよび第２のトランジスタ）、接地端子GND、電源電圧VEE、変調器を駆動する振幅を持つ信号を出力する差動出力端子OUT、OUTB、負荷抵抗R1、R2、定電流源CSから構成されている。エミッタフォロワ回路5aは、入力端子IN、入力トランジスタQ9、Q11と、レベルシフトのダイオード（トランジスタをダイオード接続したもの）D1、D3、D5、D7、D9と、電流源抵抗R3、R5で構成される。また、エミッタフォロワ回路5bは、入力端子INB、入力トランジスタQ10、Q12と、レベルシフトのダイオードD2、D4、D6、D8、D10と、電流源抵抗R4、R6で構成されている。 (Fourth embodiment)
FIG. 8 shows a driver circuit according to a fourth embodiment of the present invention. The driver circuit shown in FIG. 8 includes emitter follower circuits 5a and 5b (first amplifying means and second amplifying means in the present invention) and an output circuit 15. The output circuit 15 is configured using a differential circuit, and includes a switching transistor pair Q1, Q2 (first switching transistor and second switching transistor in the present invention), a cascode-connected transistor pair Q3, Q4, Q5. , Q6, Q7, Q8 (first transistor and second transistor in the present invention), ground terminal GND, power supply voltage VEE, differential output terminals OUT, OUTB for outputting a signal having an amplitude for driving the modulator, load It consists of resistors R1, R2 and a constant current source CS. The emitter follower circuit 5a includes an input terminal IN, input transistors Q9 and Q11, level shift diodes (transistors that are diode-connected) D1, D3, D5, D7, and D9, and current source resistors R3 and R5. . The emitter follower circuit 5b includes an input terminal INB, input transistors Q10 and Q12, level shift diodes D2, D4, D6, D8, and D10, and current source resistors R4 and R6.
　出力回路１５のスイッチングトランジスタ対Q1、Q2のベースには、エミッタフォロワ回路5a、5bの出力（本発明における第１信号および第３信号）が接続されている。また、出力回路１５のカスコード接続されたトランジスタQ3、Q5、Q7には、エミッタフォロワ回路5bのレベルシフトのダイオードD8、D6、D4のエミッタの信号（本発明における複数の第４信号）が加えられる。さらに、出力回路１５のカスコード接続されたトランジスタQ4、Q6、Q8には、エミッタフォロワ回路5aのレベルシフトのダイオードD7、D5、D3のエミッタの信号（本発明における複数の第２信号）が加えられる。これにより、スイッチングトランジスタQ1に入力される信号とレベルが反転した信号がトランジスタQ3、Q5、Q7へ加えられる。同様に、スイッチングトランジスタQ2に入力される信号とレベルが反転した信号がトランジスタQ4、Q6、Q8へ加えられる。また、出力回路1５のスイッチングトランジスタ対Q1、Q2の入力信号とカスコード接続されたトランジスタ対Q3、Q4、Q5、Q6、Q7、Q8の入力信号は配線長を調整するなどで同期をとっている。 The outputs of the emitter follower circuits 5a and 5b (the first signal and the third signal in the present invention) are connected to the bases of the switching transistor pair Q1 and Q2 of the output circuit 15. Further, the signals of the emitters of the level-shifted diodes D8, D6, D4 of the emitter follower circuit 5b (a plurality of fourth signals in the present invention) are applied to the cascode-connected transistors Q3, Q5, Q7 of the output circuit 15. . Further, the signals of the emitters of the level-shifted diodes D7, D5, and D3 of the emitter follower circuit 5a (a plurality of second signals in the present invention) are applied to the cascode-connected transistors Q4, Q6, and Q8 of the output circuit 15. . As a result, the signal input to the switching transistor Q1 and the signal whose level is inverted are added to the transistors Q3, Q5, and Q7. Similarly, a signal whose level is inverted from that of the signal input to the switching transistor Q2 is applied to the transistors Q4, Q6, and Q8. The input signals of the transistor pairs Q3, Q4, Q5, Q6, Q7, and Q8 that are cascode-connected to the input signals of the switching transistor pair Q1 and Q2 of the output circuit 15 are synchronized by adjusting the wiring length.
　ここで、各トランジスタの動作を説明する。出力回路１５のスイッチングトランジスタ対Q1、Q2は、定電流源CSの電流を切り替えるように働く。一方、カスコード接続されたトランジスタQ3、Q5、Q7（Q4、Q6、Q8）の入力信号は、スイッチングトランジスタQ1（Q2）の入力信号と同期しているが論理レベルが反転している。また、トランジスタQ3、Q5、Q7（Q4、Q6、Q8）の入力信号は、エミッタフォロワ回路5b(5a)のダイオードD4、D6、D8、D10(D3、D5、D7、D9)を用いて入力信号レベルが決定される。それゆえ、トランジスタQ1の入力信号がLOWレベルの場合（すなわち、トランジスタQ2のベースへの入力信号がHIGHレベルの場合）には、差動出力端子OUTBがHIGHレベルになると共に、トランジスタQ1、Q3、Q5、Q7にはVCEとしてダイオードD4、D6、D8、D10を用いて分割された均等の電圧がかかることになる。従って、必要な出力振幅に対して、より低い電圧（出力振幅の約１／４の電圧）がトランジスタQ1、Q3、Q5、Q7のエミッタ－コレクタ間にかかることになる。 Here, the operation of each transistor will be described. The switching transistor pair Q1, Q2 of the output circuit 15 functions to switch the current of the constant current source CS. On the other hand, the input signals of the cascode-connected transistors Q3, Q5, Q7 (Q4, Q6, Q8) are synchronized with the input signal of the switching transistor Q1 (Q2), but the logic level is inverted. The input signals of transistors Q3, Q5, Q7 (Q4, Q6, Q8) are input signals using diodes D4, D6, D8, D10 (D3, D5, D7, D9) of emitter follower circuit 5b (5a). The level is determined. Therefore, when the input signal of the transistor Q1 is LOW level (that is, when the input signal to the base of the transistor Q2 is HIGH level), the differential output terminal OUTB becomes HIGH level and the transistors Q1, Q3, Q5 and Q7 are applied with an equal voltage divided by using diodes D4, D6, D8, and D10 as VCE. Therefore, a lower voltage (a voltage of about 1/4 of the output amplitude) is applied between the emitter and collector of the transistors Q1, Q3, Q5, and Q7 with respect to the required output amplitude.
　以上、説明したように、カスコード接続されたトランジスタ対を出力回路に複数設ける。また、出力回路の前段にあるエミッタフォロワ回路のレベルシフトダイオードでレベルを変えた信号を生成して、スイッチングトランジスタ対に入力される信号と同期してレベルが反転した信号をスイッチングトランジスタ対にカスコード接続されたトランジスタ対に入力する。こうした構成を採ることによって、スイッチングトランジスタの入力レベルがLOWレベルの時（すなわち、スイッチングトランジスタQ1(Q2)のエミッターコレクタ間電圧が最大時）に、スイッチングトランジスタのVCEとスイッチングトランジスタにカスコード接続されたトランジスタのVCEが均等になり、出力振幅より低い耐圧をもつトランジスタを適用することができる。 As described above, a plurality of cascode-connected transistor pairs are provided in the output circuit. Also, a signal whose level is changed by the level shift diode of the emitter follower circuit in the previous stage of the output circuit is generated, and the signal whose level is inverted in synchronization with the signal input to the switching transistor pair is cascode connected to the switching transistor pair Input to the transistor pair. By adopting such a configuration, when the input level of the switching transistor is LOW level (that is, when the voltage between the emitter and the collector of the switching transistor Q1 (Q2) is maximum), the transistor which is cascode-connected to the switching transistor VCE Therefore, a transistor having a withstand voltage lower than the output amplitude can be applied.
　なお、ここではカスコード接続された複数のトランジスタの入力レベルを変えるために、複数のレベルシフトダイオードを持つエミッタフォロワ回路を用いたが、その他の方法でも良い。また、上述した説明では、スイッチングトランジスタにカスコード接続されたトランジスタの数を３としたが、これ以外の数のトランジスタをスイッチングトランジスタにカスコード接続しても良い。その場合、レベルシフトダイオードの数もスイッチングトランジスタにカスコード接続されたトランジスタの数に合わせて適宜変更する。 Here, an emitter follower circuit having a plurality of level shift diodes is used to change the input level of a plurality of cascode-connected transistors, but other methods may be used. In the above description, the number of transistors that are cascode-connected to the switching transistors is three. However, other numbers of transistors may be cascode-connected to the switching transistors. In that case, the number of level shift diodes is appropriately changed according to the number of transistors cascode-connected to the switching transistors.
（第５実施形態）
　図９は、本発明の第５実施形態によるドライバー回路１６の構成を示す回路図である。この図に示すドライバー回路１６は分布型回路によって構成されている。具体的には、ドライバー回路１６は、入力端子IN、入力端子INCAS、入力側分布定数伝送線路19（本発明における入力側伝送線路）、入力終端抵抗Rin（本発明における入力側終端回路）、入力側バイアス回路18a、エミッタ接地トランジスタQ9（本発明における増幅回路）、トランジスタQ9にカスコード接続されたトランジスタQ10、トランジスタQ10の入力側分布定数伝送線路21、入力側分布定数伝送線路２１の終端回路（終端抵抗）Rincas、トランジスタQ10のバイアス回路18b、出力側分布定数伝送線路20（本発明における出力側伝送線路）、出力終端抵抗Rout（本発明における出力側終端回路）、出力側バイアス回路18c、出力端子OUTから構成される。なお、Vbin1およびVbin2はバイアス電圧であり、VEEは電源電圧である。 (Fifth embodiment)
FIG. 9 is a circuit diagram showing a configuration of the driver circuit 16 according to the fifth embodiment of the present invention. The driver circuit 16 shown in this figure is constituted by a distributed circuit. Specifically, the driver circuit 16 includes an input terminal IN, an input terminal INCAS, an input-side distributed constant transmission line 19 (input-side transmission line in the present invention), an input termination resistor Rin (input-side termination circuit in the present invention), an input Side bias circuit 18a, common-emitter transistor Q9 (amplifier circuit in the present invention), transistor Q10 cascode-connected to transistor Q9, input-side distributed constant transmission line 21 of transistor Q10, termination circuit for input-side distributed constant transmission line 21 (termination) Resistor) Rincas, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20 (output side transmission line in the present invention), output termination resistor Rout (output side termination circuit in the present invention), output side bias circuit 18c, output terminal Consists of OUT. Vbin1 and Vbin2 are bias voltages, and VEE is a power supply voltage.
　このような分布型回路（分布型増幅器）においては、入力端子INから入力された信号は、入力側分布定数伝送線路１９を入力終端抵抗Rinの方向（順方向）に伝搬していく。このように伝搬していく信号の大部分はトランジスタQ9に順々に分配され、増幅される。各トランジスタQ9に入力された信号は、各トランジスタに流れる電流に応じて増幅され、出力側分布定数伝送線路20を経て出力端子OUTの方向に伝搬していく。また、入力端子INから出力端子OUTまでのそれぞれの伝搬経路における電気長が等しくなるように選ばれるため、各トランジスタQ9で増幅された信号は上記出力側分布定数伝送線路20で順々に合成され、出力端子OUTから増幅した信号が出力される。一方、トランジスタQ9にカスコード接続されたトランジスタQ10には、入力端子INから入力される信号と同期して論理が反転した信号が入力端子INCASから入力される。ここで、カスコード接続されたトランジスタQ10の入力側分布定数伝送線路21は、各エミッタ接地トランジスタQ9に入力される信号とトランジスタQ10に入力される信号が同期して分配されるように設定される。 In such a distributed circuit (distributed amplifier), a signal input from the input terminal IN propagates through the input-side distributed constant transmission line 19 in the direction of the input termination resistor Rin (forward direction). Most of the signals propagating in this way are sequentially distributed to the transistor Q9 and amplified. The signal input to each transistor Q9 is amplified according to the current flowing through each transistor, and propagates through the output-side distributed constant transmission line 20 in the direction of the output terminal OUT. Further, since the electrical lengths in the respective propagation paths from the input terminal IN to the output terminal OUT are selected to be equal, the signals amplified by the transistors Q9 are sequentially synthesized by the output-side distributed constant transmission line 20. The amplified signal is output from the output terminal OUT. On the other hand, a transistor whose logic is inverted in synchronization with a signal input from the input terminal IN is input from the input terminal INCAS to the transistor Q10 which is cascode-connected to the transistor Q9. Here, the input-side distributed constant transmission line 21 of the cascode-connected transistor Q10 is set so that the signal input to each emitter grounded transistor Q9 and the signal input to the transistor Q10 are distributed in synchronization.
　次に、本発明の第５実施形態の動作について説明する。図１０Ａ～図１０Ｅは、各端子における信号波形を示す。電源電圧VEEを5Vとする。また、エミッタ接地トランジスタQ9側の入力端子INに、HIGHレベル1.0V、LOWレベル0.5Vの信号を与える（図１０Ｃ参照）。さらに、カスコード接続されたトランジスタQ10側の入力端子INCASに対して、入力端子INに与えられる信号と同期して位相が反転したHIGHレベル2.8V、LOWレベル1.6Vの信号を与える（図１０Ｂ参照）。
　出力端子OUTには4.0Vの振幅を持つ信号（図１０Ａ参照）が現れている。一方、エミッタ接地トランジスタQ9のエミッタ-コレクタ間電圧VCEは、最大2.6Vになっている（図１０Ｅ参照）。また、カスコード接続されたトランジスタQ10のエミッタ-コレクタ間電圧VCEも最大2.6V以下になっている（図１０Ｄ参照）。従って、使用するトランジスタQ9、Q10として、3VのVCE耐圧を有するものを適用することができる。 Next, the operation of the fifth embodiment of the present invention will be described. 10A to 10E show signal waveforms at each terminal. The power supply voltage VEE is 5V. Further, a signal having a HIGH level of 1.0 V and a LOW level of 0.5 V is applied to the input terminal IN on the grounded emitter transistor Q9 side (see FIG. 10C). Furthermore, a HIGH level 2.8V signal and a LOW level 1.6V signal whose phases are inverted in synchronization with a signal applied to the input terminal IN are applied to the cascode-connected input terminal INCAS on the transistor Q10 side (see FIG. 10B). .
A signal (see FIG. 10A) having an amplitude of 4.0 V appears at the output terminal OUT. On the other hand, the emitter-collector voltage VCE of the common-emitter transistor Q9 is 2.6 V at the maximum (see FIG. 10E). Further, the emitter-collector voltage VCE of the cascode-connected transistor Q10 is also a maximum of 2.6 V or less (see FIG. 10D). Accordingly, transistors having a VCE breakdown voltage of 3 V can be applied as the transistors Q9 and Q10 to be used.
　以上説明したように、分布型回路によって構成されたドライバー回路において、カスコード接続されたトランジスタQ10を設ける。また、エミッタ接地トランジスタQ9に入力される信号と同期して位相が反転した信号をトランジスタQ10へ入力する。さらに、出力がHIGHレベルの時に、エミッタ接地トランジスタQ9とカスコード接続したトランジスタQ10にかかる電圧が、エミッタ接地トランジスタQ9のエミッタ－コレクタ間電圧とカスコード接続されたトランジスタQ10のエミッタ－コレクタ間電圧に均等に分割されるように、カスコード接続されたトランジスタの入力信号レベルを設定する。これによって、出力振幅より低い耐圧をもつトランジスタを適用することができる。 As described above, the cascode-connected transistor Q10 is provided in the driver circuit configured by the distributed circuit. Further, a signal whose phase is inverted in synchronization with the signal input to the grounded emitter transistor Q9 is input to the transistor Q10. Furthermore, when the output is at a high level, the voltage applied to the transistor Q10 cascode-connected to the common-emitter transistor Q9 is equal to the emitter-collector voltage of the common-emitter transistor Q9 and the emitter-collector voltage of the cascode-connected transistor Q10. The input signal level of the cascode-connected transistors is set so as to be divided. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
（第６実施形態）
　図１１に本発明の第６実施形態にかかるドライバー回路22の回路図を示す。また、図１２Ａ～図１２Ｃには、動作を説明するための各端子の波形を示す。図１１に示すドライバー回路は、差動回路23（本発明における第１の増幅手段）と、分布型回路によって構成された出力回路17で構成されている。差動回路23では、入力端子INとINBに差動のデータ信号が入力され、出力回路17を駆動するための利得と振幅を持った差動のデータ信号（本発明における第１の信号、第２の信号）が出力される。ここで、差動回路23の前段に単相のデータ信号を差動のデータ信号に変換する入力バッファ回路を設けても良い。なお、差動回路23において、R1、R2は負荷抵抗、Q1、Q2はトランジスタ、CSは定電流源である。 (Sixth embodiment)
FIG. 11 shows a circuit diagram of a driver circuit 22 according to the sixth embodiment of the present invention. 12A to 12C show waveforms at each terminal for explaining the operation. The driver circuit shown in FIG. 11 includes a differential circuit 23 (first amplifying means in the present invention) and an output circuit 17 configured by a distributed circuit. In the differential circuit 23, a differential data signal is input to the input terminals IN and INB, and a differential data signal having a gain and an amplitude for driving the output circuit 17 (the first signal and the first signal in the present invention). 2 signal) is output. Here, an input buffer circuit for converting a single-phase data signal into a differential data signal may be provided in the preceding stage of the differential circuit 23. In the differential circuit 23, R1 and R2 are load resistors, Q1 and Q2 are transistors, and CS is a constant current source.
　出力回路17は、分布型回路で構成されている。具体的には、出力回路１７は、入力側分布定数伝送線路19、入力終端抵抗Rin、入力側バイアス回路18a、エミッタ接地トランジスタQ9、エミッタ接地トランジスタQ9にカスコード接続されたトランジスタQ10、トランジスタQ10の入力側分布定数伝送線路21、トランジスタQ10の入力側分布定数伝送線路21の終端回路（終端抵抗）Rincas、トランジスタQ10のバイアス回路18b、出力側分布定数伝送線路20、出力終端抵抗Rout、出力側バイアス回路18ｃ、出力端子OUTから構成されている。 The output circuit 17 is a distributed circuit. Specifically, the output circuit 17 includes an input side distributed constant transmission line 19, an input termination resistor Rin, an input side bias circuit 18a, a common emitter transistor Q9, a transistor Q10 cascode-connected to the common emitter transistor Q9, and an input of the transistor Q10. Side distributed constant transmission line 21, termination circuit (termination resistor) Rincas of input side distributed constant transmission line 21 of transistor Q10, bias circuit 18b of transistor Q10, output side distributed constant transmission line 20, output termination resistor Rout, output side bias circuit 18c and an output terminal OUT.
　エミッタ接地トランジスタ（スイッチングトランジスタ）Q9の入力には、差動回路23の出力の一方がバイアス回路18ａと入力側分布定数伝送線路19を介して接続されている。また、カスコード接続されたトランジスタ対Q10の入力には、差動回路23の出力の他方がバイアス回路18ｂと入力側分布定数伝送線路21を介して接続されている。出力回路17のエミッタ接地トランジスタ（スイッチングトランジスタ）Q9とカスコード接続されたトランジスタ対Q10には、それぞれ位相が反転した信号が入力される。 One of the outputs of the differential circuit 23 is connected to the input of the grounded emitter transistor (switching transistor) Q9 via the bias circuit 18a and the input-side distributed constant transmission line 19. The other of the outputs of the differential circuit 23 is connected to the input of the cascode-connected transistor pair Q10 via the bias circuit 18b and the input-side distributed constant transmission line 21. A signal whose phase is inverted is input to the transistor pair Q10 cascode-connected to the grounded emitter transistor (switching transistor) Q9 of the output circuit 17.
　ここで、例えば4.0Vの出力振幅を出力する場合について、動作を説明する。差動回路23の負荷抵抗R1、R2と定電流源CSを調整して、差動回路23の出力端からHIGHレベルが0V、LOWレベル-1.0Vの信号が出力されるように設定する。出力回路17の電源電圧VEEを5Vとし、エミッタ接地トランジスタQ9の入力側のバイアス回路１８ａのバイアス電圧Vbin1を0.5Vに設定すると、エミッタ接地トランジスタQ9にはHIGHレベル1.0V、LOWレベル0Vの信号が入力される。一方、エミッタ接地トランジスタQ9にカスコード接続されたトランジスタQ10の入力側のバイアス回路１８ｂにおけるバイアス電圧Vbin2を2.2Vに設定すると、カスコード接続されたトランジスタQ10にはHIGHレベル2.7V、LOWレベル1.7Vの信号が入力される。この場合、エミッタ接地トランジスタQ9の入力信号と、カスコード接続されたトランジスタQ10の入力信号は、それぞれ位相が反転し同期が取られた信号である。
　図１２Ａ～図１２Ｃに各端子の波形を示している。出力回路17の出力端子OUTには、4V振幅の出力波形が得られている（図１２Ａ参照）。一方、エミッタ接地トランジスタQ9のエミッタ-コレクタ間にかかる電圧VCE（図１２Ｃ参照）と、カスコード接続されたトランジスタQ10のエミッタ-コレクタ間にかかる電圧VCE（図１２Ｂ参照）は、3V以下になっている。 Here, for example, the operation will be described in the case of outputting an output amplitude of 4.0V. The load resistors R1 and R2 of the differential circuit 23 and the constant current source CS are adjusted so that a signal with a HIGH level of 0 V and a LOW level of -1.0 V is output from the output terminal of the differential circuit 23. When the power supply voltage VEE of the output circuit 17 is set to 5V and the bias voltage Vbin1 of the bias circuit 18a on the input side of the grounded emitter transistor Q9 is set to 0.5V, the grounded transistor Q9 receives a signal of HIGH level 1.0V and LOW level 0V. Entered. On the other hand, when the bias voltage Vbin2 in the bias circuit 18b on the input side of the transistor Q10 cascode-connected to the grounded-emitter transistor Q9 is set to 2.2V, a signal of HIGH level 2.7V and LOW level 1.7V is applied to the cascode-connected transistor Q10. Is entered. In this case, the input signal of the grounded-emitter transistor Q9 and the input signal of the cascode-connected transistor Q10 are signals whose phases are inverted and synchronized.
12A to 12C show waveforms at each terminal. An output waveform having a 4V amplitude is obtained at the output terminal OUT of the output circuit 17 (see FIG. 12A). On the other hand, the voltage VCE (see FIG. 12C) applied between the emitter and collector of the grounded-emitter transistor Q9 and the voltage VCE (see FIG. 12B) applied between the emitter and collector of the cascode-connected transistor Q10 are 3V or less. .
　以上、説明したように、分布型回路によって構成された出力回路にカスコード接続されたトランジスタを設ける。また、出力回路の前段にある差動回路から出力される信号は、エミッタ接地トランジスタに入力される信号と位相が反転した信号をカスコード接続されたトランジスタに入力するように設定する。さらに、エミッタ接地トランジスタの入力レベルがLOWレベルの時に、スイッチングトランジスタのエミッタ－コレクタ間電圧VCEとカスコード接続されたトランジスタのエミッタ－コレクタ間電圧VCEが均等になるように、カスコード接続されたトランジスタの入力信号レベルを設定する。これによって、出力振幅より低い耐圧のトランジスタを適用することができる。  As described above, a cascode-connected transistor is provided in an output circuit constituted by a distributed circuit. Further, the signal output from the differential circuit in the previous stage of the output circuit is set so that a signal whose phase is inverted from that of the signal input to the grounded emitter transistor is input to the cascode-connected transistor. In addition, when the input level of the common-emitter transistor is LOW, the input of the cascode-connected transistor is such that the emitter-collector voltage VCE of the switching transistor and the emitter-collector voltage VCE of the cascode-connected transistor are equal. Set the signal level. Thereby, a transistor having a breakdown voltage lower than the output amplitude can be applied.
　なお、上記各実施形態では、トランジスタをバイポーラトランジスタで構成したが、MOS等のFETで構成しても良い。また、上記各実施形態では光通信の送信器で用いられる変調器を駆動するドライバー回路について述べたが、出力振幅に対して耐圧の小さいトランジスタを使用する論理回路や、無線装置の送信器に用いられる電力増幅器にも適用することができる。 In each of the above embodiments, the transistor is formed of a bipolar transistor, but may be formed of a FET such as a MOS. In each of the above embodiments, a driver circuit that drives a modulator used in a transmitter for optical communication has been described. The present invention can also be applied to a power amplifier.
　また、上記各実施形態によるドライバー回路は、次のような共通の概念を有している。すなわち、入力信号が入力されるトランジスタにカスコード接続されたトランジスタを設ける。また、カスコード接続されたトランジスタの入力に前記トランジスタの入力信号に同期し、かつ、位相が反転した信号を入力する。また、前記トランジスタのエミッタ-コレクタ電圧が最大時において（出力がHIGHレベルの時）、前記トランジスタとカスコード接続したトランジスタからなる回路の両端にかかる電圧が、前記トランジスタのエミッタ－コレクタ間電圧とカスコード接続したトランジスタのエミッタ-コレクタ間電圧に分割される。そして、こうした共通の概念を差動回路によって構成されたドライバー回路や分布型回路によって構成されたドライバー回路に適用している。 The driver circuit according to each of the above embodiments has the following common concept. That is, a cascode-connected transistor is provided for a transistor to which an input signal is input. In addition, a signal that is synchronized with the input signal of the transistor and whose phase is inverted is input to the input of the cascode-connected transistor. Further, when the emitter-collector voltage of the transistor is maximum (when the output is at a high level), the voltage applied to both ends of the circuit composed of the transistor connected to the transistor in cascode is connected to the emitter-collector voltage of the transistor in cascode connection. Is divided into the emitter-collector voltage of the transistor. Such a common concept is applied to a driver circuit constituted by a differential circuit and a driver circuit constituted by a distributed circuit.
　以上、実施形態を参照して本発明を説明したが、本発明は上述した実施形態に限定されるものではない。本発明の構成や詳細には、本発明の範囲内で当業者が理解し得る様々な変更を加えることができる。 The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
　この出願は、２００８年４月２５日に出願された日本出願特願２００８－１１５８４５号および２００９年４月１６日に出願された日本出願特願２００９－９９９６７号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2008-115845 filed on Apr. 25, 2008 and Japanese Patent Application No. 2009-99967 filed on Apr. 16, 2009. , The entire disclosure of which is incorporated herein.
　本発明は、誘電体導波路を用いた誘電体変調器や、半導体の光吸収を利用した電界吸収型半導体変調器などの外部変調器を駆動するドライバー回路に用いられる。 The present invention is used in a driver circuit for driving an external modulator such as a dielectric modulator using a dielectric waveguide or an electroabsorption semiconductor modulator using light absorption of a semiconductor.
１１、１２、１４、１６、２２…ドライバー回路 
１３、１５、１７…出力回路 
１８ａ、１８ｂ、１８ｃ…バイアス回路 
１９…入力側分布定数伝送線路 
２０…出力側分布定数伝送線路 
２１…カスコード接続トランジスタの入力側分布定数線路 
Q1、Q2、Q9…スイッチングトランジスタ 
Q3、Q4、Q5、Q6、Q7、Q8、Q10…トランジスタ
R1、R2…負荷抵抗 
Rin、Rout、Rincas…終端抵抗 
CS…定電流源 
VEE…電源電圧 
Vbin1、Vbin2…バイアス電圧 
IN、INB、INCAS、INCASB、INCAS１、INCAS１B…入力端子 
OUT、OUTB…出力端子 
GND…接地 11, 12, 14, 16, 22 ... driver circuit
13, 15, 17 ... output circuit
18a, 18b, 18c ... bias circuit
19: Input-side distributed constant transmission line
20 ... Output-side distributed constant transmission line
21 ... Cascade-connected transistor input-side distributed constant line
Q1, Q2, Q9 ... Switching transistors
Q3, Q4, Q5, Q6, Q7, Q8, Q10 ... transistor
R1, R2 ... Load resistance
Rin, Rout, Rincas ... Terminating resistor
CS… Constant current source
VEE ... Power supply voltage
Vbin1, Vbin2 ... Bias voltage
IN, INB, INCAS, INCASB, INCAS1, INCAS1B ... Input terminal
OUT, OUTB ... Output terminals
GND ... Ground

Claims (9)

  1. 　入力信号が加えられる第１のスイッチングトランジスタと、
    　前記第１のスイッチングトランジスタにカスコード接続された第１のトランジスタと
    　を具備し、 
    　前記第１のトランジスタの入力に前記第１のスイッチングトランジスタへの前記入力信号に同期し、かつ、レベルが反転した信号を入力するドライバー回路。     A first switching transistor to which an input signal is applied;
    A first transistor cascode-connected to the first switching transistor;
    A driver circuit that inputs a signal whose level is inverted and synchronized with the input signal to the first switching transistor to the input of the first transistor.
  2. 　請求項１記載のドライバー回路において、
    　前記第１のスイッチングトランジスタのエミッタ-コレクタ間電圧が最大時において、前記第１のスイッチングトランジスタと前記第１のトランジスタからなる回路の両端にかかる電圧が、前記第１のスイッチングトランジスタの前記エミッタ－コレクタ間電圧と前記第１のトランジスタのエミッタ-コレクタ間電圧に分割されるドライバー回路。     The driver circuit according to claim 1,
    When the voltage between the emitter and the collector of the first switching transistor is maximum, the voltage applied across the circuit composed of the first switching transistor and the first transistor is the emitter-collector of the first switching transistor. A driver circuit divided into an inter-voltage and an emitter-collector voltage of the first transistor.
  3. 　請求項１または２記載のドライバー回路において、
    　前記ドライバー回路は差動回路を用いて構成されたドライバー回路であって、
    　入力信号が加えられ、前記第１のスイッチングトランジスタとスイッチングトランジスタ対を構成する第２のスイッチングトランジスタと、
    　前記第２のスイッチングトランジスタにカスコード接続された第２のトランジスタと
    　をさらに具備し、
    　前記第１のトランジスタおよび前記第２のトランジスタからなるトランジスタ対を少なくとも一対具備し、
    　前記トランジスタ対の入力に前記スイッチングトランジスタ対への前記入力信号に同期し、かつ、レベルが反転した信号を入力するドライバー回路。     The driver circuit according to claim 1 or 2,
    The driver circuit is a driver circuit configured using a differential circuit,
    An input signal applied to the first switching transistor and a second switching transistor constituting a switching transistor pair;
    A second transistor cascode-connected to the second switching transistor;
    Comprising at least one transistor pair comprising the first transistor and the second transistor;
    A driver circuit that inputs a signal whose level is inverted and synchronized with the input signal to the switching transistor pair to the input of the transistor pair.
  4. 　請求項３記載のドライバー回路において、
    　入力信号を増幅する第１の増幅手段と、
    　前記第１の増幅手段の出力を増幅して、互いに位相が反転した第１の信号、第２の信号を出力する第２の増幅手段と、
    　前記第１の増幅手段の前記出力を増幅して、前記第１の信号と位相が反転した第３の信号と前記第１の信号と同相の第４の信号とを出力する第３の増幅手段と
    　をさらに具備し、
    　前記第１の信号、前記第２の信号がそれぞれ前記第１のスイッチングトランジスタ、前記第２のスイッチングトランジスタに加えられ、前記第３の信号、前記第４の信号がそれぞれ前記第１のトランジスタ、前記第２のトランジスタに加えられるドライバー回路。     The driver circuit according to claim 3,
    First amplification means for amplifying an input signal;
    A second amplifying means for amplifying the output of the first amplifying means and outputting a first signal and a second signal whose phases are mutually inverted;
    Third amplifying means for amplifying the output of the first amplifying means to output a third signal whose phase is inverted with respect to the first signal and a fourth signal in phase with the first signal. And further comprising
    The first signal and the second signal are applied to the first switching transistor and the second switching transistor, respectively, and the third signal and the fourth signal are respectively the first transistor, A driver circuit applied to the second transistor.
  5. 　請求項３または請求項４記載のドライバー回路において、
    　前記少なくとも一対のトランジスタ対は複数のトランジスタ対であって、前記スイッチングトランジスタ対への前記入力信号に同期し、かつ、レベルが反転した信号を前記複数のトランジスタ対の入力に異なったレベルで入力するドライバー回路。     In the driver circuit according to claim 3 or 4,
    The at least one transistor pair is a plurality of transistor pairs, and a signal whose level is inverted is input to the input of the plurality of transistor pairs at a different level in synchronization with the input signal to the switching transistor pair. Driver circuit.
  6. 　請求項３記載のドライバー回路において、
    　入力信号を増幅して第１信号を出力すると共に、前記入力信号に同期し、互いにレベルが異なる複数の第２信号を出力する第１の増幅手段と、
    　前記入力信号の反転信号を増幅して第３信号を出力すると共に、前記反転信号に同期し、互いにレベルが異なる複数の第４信号を出力する第２の増幅手段と
    　をさらに具備し、
    　前記少なくとも一対のトランジスタ対は複数のトランジスタ対であって、前記第１信号、前記第３信号がそれぞれ前記第１のスイッチングトランジスタ、前記第２のスイッチングトランジスタに入力信号として加えられ、前記複数の第４信号、前記複数の第３信号がそれぞれ前記複数のトランジスタ対を構成する前記第１のトランジスタのトランジスタ列、前記第２のトランジスタのトランジスタ列に入力信号として加えられるドライバー回路。      The driver circuit according to claim 3,
    A first amplifying means for amplifying an input signal and outputting a first signal, and outputting a plurality of second signals having different levels from each other in synchronization with the input signal;
    Amplifying the inverted signal of the input signal to output a third signal, and further, a second amplifying means for outputting a plurality of fourth signals having different levels in synchronization with the inverted signal;
    The at least one pair of transistors is a plurality of transistor pairs, and the first signal and the third signal are applied as input signals to the first switching transistor and the second switching transistor, respectively. 4. A driver circuit in which four signals and the plurality of third signals are applied as input signals to the transistor rows of the first transistors and the transistor rows of the second transistors, respectively, constituting the plurality of transistor pairs.
  7. 　請求項１または２記載のドライバー回路において、
    　前記ドライバー回路は、分布型回路を用いて構成されたドライバー回路であって、
    　前記分布型回路は、
    　入力側伝送線路と、
    　出力側伝送線路と、
    　前記入力側伝送線路と前記出力側伝送線路との間に順方向に接続された複数の増幅回路と、
    　前記入力側伝送線路の信号入力端と反対側に接続された入力側終端回路と、
    　前記出力側伝送線路の信号出力端と反対側に接続された出力側終端回路と
    　を具備し、
    　前記複数の増幅回路のそれぞれは前記第１のスイッチングトランジスタを含み、複数の前記第１のトランジスタが前記複数の増幅回路に含まれる複数の前記第１のスイッチングトランジスタに対応して備えられ、
    　前記入力側伝送線路を通して前記複数の増幅回路に前記入力信号が加えられ、前記複数の第１のトランジスタの入力が伝送線路で接続されたドライバー回路。     The driver circuit according to claim 1 or 2,
    The driver circuit is a driver circuit configured using a distributed circuit,
    The distributed circuit is:
    An input transmission line;
    An output transmission line;
    A plurality of amplifier circuits connected in a forward direction between the input transmission line and the output transmission line;
    An input side termination circuit connected to the opposite side of the signal input end of the input side transmission line;
    An output-side termination circuit connected to the opposite side of the signal output end of the output-side transmission line,
    Each of the plurality of amplifier circuits includes the first switching transistor, and the plurality of first transistors are provided corresponding to the plurality of first switching transistors included in the plurality of amplifier circuits,
    A driver circuit in which the input signal is applied to the plurality of amplifier circuits through the input-side transmission line, and the inputs of the plurality of first transistors are connected by the transmission line.
  8. 　請求項７記載のドライバー回路において、
    　前記入力信号を増幅して互いに位相が反転した第１の信号、第２の信号を出力する第１の増幅手段をさらに具備し、
    　前記第１の信号が前記入力側伝送線路を通して前記第１のスイッチングトランジスタに加えられ、前記第２の信号が前記伝送線路を通して前記第１のトランジスタに加えられるドライバー回路。     The driver circuit according to claim 7,
    A first amplifying means for amplifying the input signal and outputting a first signal and a second signal whose phases are mutually inverted;
    A driver circuit in which the first signal is applied to the first switching transistor through the input transmission line, and the second signal is applied to the first transistor through the transmission line.
  9. 　入力信号をスイッチングトランジスタへ加え、
    　前記スイッチングトランジスタへの前記入力信号に同期し、かつ、レベルが反転した信号を前記スイッチングトランジスタにカスコード接続されたトランジスタの入力へ加える方法。     Apply the input signal to the switching transistor,
    A method of adding a signal, which is synchronized with the input signal to the switching transistor and whose level is inverted, to an input of a transistor that is cascode-connected to the switching transistor.
PCT/JP2009/058171 2008-04-25 2009-04-24 Driver circuit WO2009131215A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014050087A (en) * 2012-09-04 2014-03-17 Renesas Electronics Corp Differential output circuit and semiconductor device
JP2014072553A (en) * 2012-09-27 2014-04-21 Asahi Kasei Electronics Co Ltd Operational amplifier and pipelined a/d converter having the same
JP2016054542A (en) * 2015-11-27 2016-04-14 ルネサスエレクトロニクス株式会社 Differential output circuit and semiconductor device
US11290073B1 (en) * 2020-11-20 2022-03-29 Synaptics Incorporated Self-biased differential transmitter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228430A (en) * 1983-06-10 1984-12-21 Hitachi Ltd Semiconductor circuit
JPH03270408A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Semiconductor integrated circuit
JPH05291844A (en) * 1992-04-10 1993-11-05 Olympus Optical Co Ltd Level shift circuit
JP2004297165A (en) * 2003-03-25 2004-10-21 Toshiba Corp Analog / digital conversion circuit and communication apparatus
JP2007180797A (en) * 2005-12-27 2007-07-12 Matsushita Electric Ind Co Ltd Level shift circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228430A (en) * 1983-06-10 1984-12-21 Hitachi Ltd Semiconductor circuit
JPH03270408A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Semiconductor integrated circuit
JPH05291844A (en) * 1992-04-10 1993-11-05 Olympus Optical Co Ltd Level shift circuit
JP2004297165A (en) * 2003-03-25 2004-10-21 Toshiba Corp Analog / digital conversion circuit and communication apparatus
JP2007180797A (en) * 2005-12-27 2007-07-12 Matsushita Electric Ind Co Ltd Level shift circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014050087A (en) * 2012-09-04 2014-03-17 Renesas Electronics Corp Differential output circuit and semiconductor device
JP2014072553A (en) * 2012-09-27 2014-04-21 Asahi Kasei Electronics Co Ltd Operational amplifier and pipelined a/d converter having the same
JP2016054542A (en) * 2015-11-27 2016-04-14 ルネサスエレクトロニクス株式会社 Differential output circuit and semiconductor device
US11290073B1 (en) * 2020-11-20 2022-03-29 Synaptics Incorporated Self-biased differential transmitter

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