JP2004297165A - Analog / digital conversion circuit and communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital conversion circuit and a communication apparatus capable of reducing the power consumption furthermore. <P>SOLUTION: While an analog power supply voltage 120 of 2.5 V is applied to an analog circuit section 100, a digital power supply voltage 130 of 1.5 V lower than the analog power supply voltage 120 is applied to a digital circuit section 200 and a clock processing circuit 300. Further, an analog switch drive circuit 140 is provided at a position close to an analog switch circuit 105, and an analog switch drive signal 141 supplied from the clock processing circuit 300 is boosted just before the analog switch circuit 105 and fed to the analog switch circuit 105. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog / digital conversion circuit and a communication device including the analog / digital conversion circuit.
[0002]
[Prior art]
In an analog / digital conversion circuit (hereinafter, referred to as an A / D conversion circuit), a circuit for handling an analog signal (hereinafter, referred to as an analog circuit) and a circuit for handling a digital signal (hereinafter, referred to as a digital circuit) are provided. Mixed on a common semiconductor chip. In recent years, semiconductor devices are required to operate with low power consumption, operate at high speed and with high accuracy, and the like. A / D conversion circuits provided in communication devices and the like, whose demand has been rapidly increasing in recent years, are no exception.
[0003]
In order to reduce the power consumption of the A / D conversion circuit, it is effective to lower the power supply voltage as much as possible. In fact, the power supply voltage of an A / D conversion circuit as one semiconductor device has been gradually reduced due to recent advances in semiconductor technology. However, focusing on the analog circuit and the digital circuit in the A / D conversion circuit, respectively, the technical difficulty for lowering the power supply voltage differs between the two.
[0004]
That is, the operating power supply voltage of the complementary field effect transistor generally used for the clock processing circuit and the digital output signal processing unit is 3.3 V in 1997 and 2001 as described in Non-Patent Document 1. It is expected that the voltage will drop further in the future, such as 1.5 V and 0.6 V in 2012.
[0005]
On the other hand, when the operating power supply voltage of the analog circuit is lowered, the gain of the amplifier is lowered, and the signal / noise ratio is degraded, which hinders high-speed and high-precision operation. Another problem is that the ON resistance of the analog switch circuit increases and it is difficult to turn on / off the switch. Therefore, it can be said that it is difficult for the current semiconductor technology to reduce the power supply voltage of the analog circuit with respect to the digital circuit.
[0006]
Since it is difficult to lower the operating voltage of the analog circuit as described above, many of the existing A / D conversion circuits operate the entire circuit with one power supply voltage as disclosed in, for example, Non-Patent Document 1 below. Take the configuration to make it. However, in such a configuration, since a drive voltage higher than the originally required value is supplied to the digital circuit, various adverse effects such as a decrease in operation speed are exerted.
[0007]
In some A / D conversion circuits, the operating power supply voltage is changed between an analog circuit and a digital circuit (for example, see Patent Document 1 below). FIG. 63 of this document discloses a configuration in which the power supply voltage for a digital circuit is made lower than the power supply voltage for an analog circuit to promote a reduction in overall power consumption.
[0008]
However, it is not possible to read in detail the handling of clock signals and clock processing circuits from the contents of this document. As shown in FIG. 63, the clock signal generated by the timing generation circuit 32 is boosted to about 5 V by the level converter 30 outside the analog circuit 201 and is input into the analog circuit 201. That is, the clock signal is boosted outside the analog circuit 201 and then supplied to the analog circuit 201. This means that the analog switch drive signal having a large amplitude follows a relatively long path before reaching the analog switch circuit or the like in the analog circuit 201, and therefore, the power consumption caused by the parasitic capacitance between circuit wirings and the like. May increase.
[0009]
[Patent Document 1]
JP-A-6-283980 (for example, paragraph numbers [0373] to [0379], FIG. 63)
[0010]
[Non-patent document 1]
ISSC, 1999, pp. 599-606 (IEEE Journal of Solid State Circuits Vol. 34 No. 5 May. 1999, p599-p606 A 1.5-V, 10-bit, 14). .3-MS / s CMOS Pipeline Analog-to-Digital Converter)
[0011]
[Non-patent document 2]
ISSC, 1995, pp. 166-172 (IEEE Journal of Solid State Circuits Vol. 30 No. 3 Mar. 1995, p166-p172 A 10b, 20 Msample / s, 35mW Pi. / D Converter)
[0012]
[Problems to be solved by the invention]
As described above, the conventional A / D conversion circuit has a disadvantage that the operation power consumption is relatively large.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an analog / digital conversion circuit and a communication device capable of further reducing power consumption.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, an analog / digital conversion circuit according to the present invention comprises an analog circuit operating under a first operating power supply voltage (for example, 2.5 V supplied from an analog power supply voltage 120). For example, the analog circuit unit 100) operates under a second operating power supply voltage (for example, a voltage of 1.5 V supplied from the digital power supply voltage 130) lower than the first operating power supply voltage, and A clock circuit (for example, a clock processing circuit 300) that generates a clock signal to be supplied to the circuit, wherein the analog circuit converts an input analog signal into a digital signal (for example, the analog signal processing unit 101). An analog switch unit (for example, an analog switch circuit 105) for controlling the operation of the analog processing unit; Boosts the click signal, characterized in that it comprises a switch driver for generating a driving signal for controlling on / off the analog switch section (e.g., the analog switch drive circuit 104).
[0014]
By taking such measures, the analog circuit and the clock circuit can be respectively driven at the minimum necessary voltage, thereby reducing power consumption. The voltage for driving the analog circuit and the clock circuit may be generated inside the analog / digital conversion circuit or may be supplied from outside.
[0015]
Further, in the present invention, the clock signal is boosted by the switch drive unit, and a drive signal for controlling on / off of the analog switch unit is generated. In such a configuration, by arranging the switch drive unit preferably near the analog switch unit, the length of the circuit wiring through which the boosted drive signal passes is minimized, and the parasitic capacitance between the wirings is reduced. The resulting power consumption can be minimized. Therefore, power consumption can be further reduced.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a communication device including an A / D conversion circuit according to the present invention. This communication apparatus is applied to a system employing a multi-level QAM modulation scheme such as 64QAM or 256QAM. This communication device includes an antenna 40, a hybrid circuit 50, a receiving device 10, a transmitting device 20, and a control unit 19. The transmission signal provided to the transmission device 20 is subjected to multi-level QAM modulation and output from the antenna 40 via the hybrid circuit 50. The multi-level QAM modulated signal arriving at antenna 40 is provided to receiving apparatus 10 via hybrid circuit 50, and a demodulated received signal is output.
[0017]
The receiving apparatus 10 includes a high-frequency receiving circuit (RF / IF) 12, a quadrature demodulator 13, A / D conversion circuits 14-1 and 14-2, resamplers 15-1 and 15-2, and an adaptive equalizer. 16-1 and 16-2, carrier (carrier) reproducing units 17-1 and 17-2, and a decoding processing unit 18.
[0018]
The QAM modulated signal arriving at the antenna 40 is filtered and low-noise-amplified in a high-frequency receiving circuit (RF / IF) 12, frequency-converted, and converted to an intermediate frequency signal. This intermediate frequency signal is subjected to filtering processing, AGC processing, and the like, and is input to the quadrature demodulator 13.
[0019]
The intermediate frequency signal supplied to the quadrature demodulator 13 is quadrature-demodulated, and a mutually orthogonal I-channel (I-ch) and Q-channel (Q-ch) complex baseband signal is output. The baseband signals of each channel are input to A / D conversion circuits 14-1 and 14-2, respectively, and are converted into digital signals.
[0020]
The digital signals of each channel are input to resamplers 15-1 and 15-2, respectively, resampled at a predetermined sampling rate and sampling timing, and synchronized with each other. This makes it possible to arbitrarily design the sampling rates of the A / D conversion circuits 14-1 and 14-2.
[0021]
Outputs of the resamplers 15-1 and 15-2 are supplied to adaptive equalizers 16-1 and 16-2, respectively, and subjected to processing for compensating delay distortion and reducing intersymbol interference. Outputs of the adaptive equalizers 16-1 and 16-2 are supplied to carrier reproducing units 17-1 and 17-2, respectively, are dropped to baseband by the reproduced carriers, and residual carrier components (carrier frequency errors) and The phase offset is removed. Then, the obtained complex baseband signal is subjected to QAM decoding in the decoding processing unit 18.
[0022]
Update processing of resampling timings and sampling frequencies in resamplers 15-1 and 15-2, input / output timings and tap coefficients in adaptive equalizers 16-1 and 16-2, input processing in carrier reproducing units 17-1 and 17-2. The output timing and the reproduction method are flexibly controlled by the control unit 19. The control unit 19 is realized by a rewritable device such as a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and a PLD (Programmable Logic Device), and can easily change parameters and control contents.
[0023]
The adaptive equalizers 16-1 and 16-2 are realized by including a shift register, a MAC (product-sum operation unit) and the like for handling signals in the digital signal domain. The number of taps in the shift register is optimized according to the system specifications.
[0024]
FIG. 2 is a circuit block diagram showing an embodiment of the A / D conversion circuit according to the present invention. This A / D conversion circuit is realized as an integrated semiconductor chip or the like, and can be suitably used as, for example, the A / D conversion circuits 14-1 and 14-2 in the communication device of FIG.
[0025]
The A / D conversion circuit in FIG. 2 includes an analog circuit section 100, a digital circuit section 200, and a clock processing circuit 300. The analog power supply voltage 120 of 2.5 V is supplied to the analog circuit section 100. A digital power supply voltage of 1.5 V is supplied to the digital circuit section 200 and the clock processing circuit 300.
[0026]
The analog circuit section 100 includes an analog signal processing section 101, an analog switch circuit 105, and an analog switch drive circuit 104. The analog switch drive circuit 104 is patterned near the analog switch circuit 105, preferably at a position adjacent to the analog switch circuit 105.
[0027]
The digital circuit unit 200 includes a digital signal processing unit 102. The clock processing circuit 300 supplies the analog switch drive signal 141 to the analog switch drive circuit 104.
[0028]
In FIG. 2, when an analog signal 110 having a PP (Peak to Peak) voltage of, for example, 1 V is input to the analog circuit unit 100, the analog signal 110 is converted into a digital signal by an analog signal processing unit 101, and is converted to a digital circuit unit 200. Is entered. The digital signal processing unit 102 of the digital circuit unit 200 performs a predetermined code conversion process on the digital signal from the analog signal processing unit 101 and outputs the digital signal as a digital signal 111.
[0029]
The clock processing circuit 300 performs processing such as clock timing control and non-overlap on an externally input 1.5 V input clock signal 140 to generate an analog switch drive signal 141, and converts the analog switch drive signal 141 into an analog switch drive signal. The signal is supplied to the circuit 104. The voltage of the generated analog switch drive signal 141 becomes 1.5V.
[0030]
The analog switch drive circuit 104 generates the analog switch drive signal 142 by boosting the analog switch drive signal 141 to almost the voltage value of the analog power supply voltage 120, that is, about 2.5V. The analog switch drive signal 142 is supplied to the adjacent analog switch circuit 105 via a minimum wiring path, and controls on / off of the analog switch circuit 105.
[0031]
FIG. 3 is a circuit diagram showing a configuration example of the analog switch driving circuit 104 of FIG. This circuit comprises two P-channel field-effect transistors 301, 302, each having a gate connected to the drain of the other. The analog power supply voltage 120 of 2.5 V is supplied to the sources of the P-channel field-effect transistors 301 and 302.
[0032]
The NAND gate 303 is connected to the drain of the P-channel field-effect transistor 301, and the connection point is defined as an output node 360. An AND gate 304 is connected to the drain of the P-channel field-effect transistor 302, and the connection point is an output node 361.
[0033]
NAND gate 303 includes an N-channel field-effect transistor 305 having a drain connected to output node 360, and an N-channel field-effect transistor 306 having a drain connected to the source of N-channel field-effect transistor 305 and having a source grounded. Prepare. The AND gate 304 includes two N-channel field effect transistors 307 and 308 each having a drain connected to the output node 361 and a source grounded.
[0034]
The gates of the N-channel field effect transistors 305 and 307 are input nodes 340 and 341 respectively. The gates of the N-channel field effect transistors 306 and 308 are input nodes 350 and 351 respectively.
[0035]
The non-inverted signal and the inverted signal of the analog switch drive signal 141 from the clock processing circuit 300 in FIG. 2 are input to the input nodes 340 and 341, respectively. To the input nodes 350 and 351, a non-inverted signal and an inverted signal of the digital signal 112 passing through the digital signal processing unit 102 from the analog signal processing unit 101 in FIG.
[0036]
Next, the operation in the configuration of FIG. 3 will be described for a plurality of cases.
[Case 1] When digit "1" is input to input nodes 340 and 350
In this case, N-channel field effect transistors 305 and 306 are turned on, and output node 360 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 302 is increased, and the P-channel field-effect transistor 302 is turned on, so that the output node 361 becomes about 2.5V. The digit "0" is input to the input nodes 341 and 351. Therefore, the N-channel field-effect transistors 307 and 308 are turned off, and the P-channel field-effect transistor 301 is turned off because the gate-source voltage is small. As a result, the voltages of output nodes 360 and 361 are maintained.
[0037]
[Case 2] When digit "0" is input to input nodes 340 and 350
In this case, since digit “1” is input to input nodes 341 and 351, N-channel field effect transistors 307 and 308 are turned on, and output node 361 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 301 increases, and the P-channel field-effect transistor 301 is turned on, so that the output node 360 becomes about 2.5V. Further, the N-channel field-effect transistors 305 and 306 turn off, and the P-channel field-effect transistor 302 turns off because the gate-source voltage is small. As a result, the voltages of output nodes 360 and 361 are maintained.
[0038]
[Case 3] When digit “0” is input to input node 340 and digit “1” is input to input node 350
In this case, since the digit “1” is input to the input node 341, the N-channel field-effect transistor 307 is turned on, and the output node 361 becomes about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 301 increases, and the P-channel field-effect transistor 301 turns on, so that the output node 360 becomes about 2.5V. Further, the N-channel field-effect transistor 305 is turned off, and the P-channel field-effect transistor 302 is turned off because the gate-source voltage is small. As a result, the voltages of output nodes 360 and 361 are maintained.
[0039]
[Case 4] When digit “1” is input to input node 340 and digit “0” is input to input node 350
In this case, since the digit “1” is input to the input node 351, the N-channel field-effect transistor 308 is turned on, and the output node 361 becomes about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 301 increases, and the P-channel field-effect transistor 301 is turned on, so that the output node 360 becomes about 2.5V. Further, the N-channel field-effect transistor 306 turns off, and the P-channel field-effect transistor 302 turns off because the gate-source voltage is small. As a result, the voltages of output nodes 360 and 361 are maintained.
[0040]
As can be seen from the results of [Case 1] to [Case 4], signals input from input nodes 340 and 350 are subjected to a NAND operation, and the result is output from output node 360. Further, a logical product (AND) operation is performed on signals input from input nodes 340 and 350, and the result is output from output node 361. Further, the voltage of the input signal is boosted from 1.5V to 2.5V.
[0041]
Therefore, according to the configuration of FIG. 3, according to the state of digital output signal 112 input from input nodes 350 and 351 (ie, whether it is “0” or “1”), output nodes 360 and 361 It is possible to select whether or not to output the analog switch drive signal 141. That is, it is possible to control whether or not the on / off operation of the analog switch circuit 105 is performed. Thus, for example, by using the circuit of FIG. 3 to select an analog switch circuit of a D / A conversion circuit in a pipeline type A / D conversion circuit or a delta sigma circuit, the circuit scale can be reduced. become.
[0042]
As described above, in the present embodiment, the analog power supply voltage 120 of 2.5 V is supplied to the analog circuit unit 100, whereas the digital circuit unit 200 and the clock processing circuit 300 are supplied with the lower 1.5 V power supply voltage. A digital power supply voltage 130 is supplied. Further, an analog switch drive circuit 104 is provided at a position close to the analog switch circuit 105, and boosts the analog switch drive signal 141 supplied from the clock processing circuit 300 immediately before reaching the analog switch circuit 105 and supplies it to the analog switch circuit 105. I am trying to do it.
[0043]
With this configuration, the clock processing circuit 300 is driven by 1.5 V, which is the same as the digital power supply voltage 130, and the minimum necessary voltage is supplied to the digital circuit unit 100 and the clock processing circuit 300. Can be suppressed to a minimum.
[0044]
Further, the analog switch drive signal 141 propagates on the circuit wiring until just before the analog switch circuit 105 at 1.5 V. For this reason, the length of the circuit wiring through which the analog switch drive signal 141 having the amplitude of 2.5 V propagates in the analog circuit section 100 can be significantly reduced as compared with the existing A / D conversion circuit. Therefore, power consumption due to parasitic capacitance between circuit wirings can be reduced, and power consumption can be further suppressed.
[0045]
The analog switch driving circuit 104 according to the present embodiment includes P-channel field-effect transistors 301 and 302 each having a source to which the analog switch driving signal 141 is supplied and a gate connected to each drain, respectively. The NAND gate 303 is connected to the drain of the transistor 301, and the AND gate 304 is connected to the drain of the P-channel field-effect transistor 302.
[0046]
According to such a configuration, the analog switch drive signal 141 is boosted to a voltage required for on / off control of the analog switch circuit 105, and the analog switch circuit 104 is switched according to the state of the digital output signal 112. Can be realized in the circuit of one analog switch driving circuit 104. This makes it possible to simplify the circuit configuration of the A / D conversion circuit.
[0047]
(Modification 1 of analog switch driving circuit 104)
FIG. 4 is a circuit diagram showing another configuration example of the analog switch driving circuit 104 of FIG. This circuit comprises two P-channel field-effect transistors 401, 402, each having a gate connected to the other's drain. The analog power supply voltage 120 of 2.5 V is supplied to the sources of the P-channel field effect transistors 401 and 402.
[0048]
An XOR gate 403 and an XNOR gate 404 are connected to the drains of the P-channel field effect transistors 401 and 402, respectively. XOR gate 403 includes N-channel field-effect transistors 405, 406, and 407, and XNOR gate 404 includes N-channel field-effect transistors 408, 409, and 410.
[0049]
The drains of the N-channel field-effect transistors 405 and 409 are connected to the drain of the P-channel field-effect transistor 401. The drains of the N-channel field-effect transistors 406 and 408 are both connected to the drain of the P-channel field-effect transistor 402.
[0050]
The sources of the N-channel field-effect transistors 405 and 406 are both connected to the drain of the N-channel field-effect transistor 407. The source of N-channel field effect transistor 407 is grounded.
[0051]
The sources of the N-channel field-effect transistors 408 and 409 are both connected to the drain of the N-channel field-effect transistor 410. The source of N-channel field effect transistor 410 is grounded.
[0052]
Further, the gates of N-channel field-effect transistors 405 and 408 are connected to each other, and this connection point is used as input node 440. The gates of the N-channel field effect transistors 406 and 409 are connected to each other, and this connection point is referred to as an input node 441. The gates of the N-channel field-effect transistors 407 and 410 are input nodes 450 and 451, respectively. The output node 460 is connected to the drain of the P-channel field-effect transistor 401, and the output node 461 is connected to the drain of the P-channel field-effect transistor 402.
[0053]
The non-inverted signal and the inverted signal of the analog switch drive signal 141 from the clock processing circuit 300 in FIG. 2 are input to the input nodes 440 and 441, respectively. To the input nodes 450 and 451, a non-inverted signal and an inverted signal of the digital signal 112 passing through the digital signal processing unit 102 from the analog signal processing unit 101 in FIG.
[0054]
Next, the operation in the configuration of FIG. 4 will be described for a plurality of cases.
[Case 1] When digit "1" is input to input nodes 440 and 450
In this case, N-channel field effect transistors 405 and 407 are turned on, and output node 460 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 402 is increased, and the P-channel field-effect transistor 402 is turned on, so that the output node 461 becomes about 2.5V. The digit "0" is input to the input nodes 441 and 451. Therefore, the N-channel field-effect transistors 406 and 410 are turned off, and the P-channel field-effect transistor 401 is turned off because the gate-source voltage is small. As a result, the voltages of output nodes 460 and 461 are maintained.
[0055]
[Case 2] When digit "0" is input to input nodes 440 and 450
In this case, since digit “1” is input to input nodes 441 and 451, N-channel field effect transistors 409 and 410 are turned on, and output node 460 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 402 is increased, and the P-channel field-effect transistor 402 is turned on, so that the output node 461 becomes about 2.5V. Further, the N-channel field-effect transistors 406 and 408 turn off, and the P-channel field-effect transistor 401 turns off because the gate-source voltage is small. As a result, the voltages of output nodes 460 and 461 are maintained.
[0056]
[Case 3] When digit “0” is input to input node 440 and digit “1” is input to input node 450
In this case, since digit “1” is input to input node 441, N-channel field effect transistors 406 and 407 are turned on, and output node 461 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 401 increases, and the P-channel field-effect transistor 401 turns on, so that the output node 460 becomes about 2.5V. The N-channel field-effect transistor 405 is turned off, and since the digit “0” is input to the input node 451, the N-channel field-effect transistor 410 is turned off, and the P-channel field-effect transistor 401 is gate-source The inter-voltage is small and turns off. As a result, the voltages of output nodes 460 and 461 are maintained.
[0057]
[Case 4] When digit “1” is input to input node 440 and digit “0” is input to input node 450
In this case, since digit “1” is input to input node 451, N-channel field effect transistors 408 and 410 are turned on, and output node 461 is at about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 401 increases, and the P-channel field-effect transistor 401 turns on, so that the output node 460 becomes about 2.5V. Also, the N-channel field-effect transistor 407 is turned off, and since the digit “0” is input to the input node 441, the N-channel field-effect transistor 409 is turned off, and the P-channel field-effect transistor 402 is gate-source The inter-voltage is small and turns off. As a result, the voltages of output nodes 460 and 461 are maintained.
[0058]
As can be seen from the results of [Case 1] to [Case 4], signals input from input nodes 440 and 450 are subjected to an exclusive OR (XOR) operation, and the result is output from output node 460. . Also, signals input from input nodes 440 and 450 are subjected to a negative exclusive OR (XNOR) operation, and the result is output from output node 461. Further, the voltage of the input signal is boosted from 1.5V to 2.5V.
[0059]
Therefore, according to the configuration of FIG. 4, it is also possible to select whether or not to output the analog switch drive signal 141 according to the state of the digital output signal 112 input from the input nodes 450 and 451. This makes it possible to obtain the same effect as the configuration of FIG.
[0060]
(Modification 2 of analog switch driving circuit 104)
FIG. 5 is a circuit diagram showing another configuration example of the analog switch driving circuit 104 of FIG. This circuit comprises two P-channel field-effect transistors 501 and 502, each gate connected to the other's drain, respectively. The analog power supply voltage 120 of 2.5 V is supplied to the sources of the P-channel field-effect transistors 501 and 502.
[0061]
The drain of the P-channel field-effect transistor 501 is connected to the drain of an N-channel field-effect transistor 503 as a NOT gate. The source of this N-channel field effect transistor 503 is grounded, and the gate is connected to input node 540. The drain of the P-channel field-effect transistor 502 is connected to the drain of an N-channel field-effect transistor 504 as a NOT gate. The source of this N-channel field effect transistor 504 is grounded, and the gate is connected to input node 541. Further, output nodes 560 and 561 are connected to the drains of the P-channel field effect transistors 501 and 502, respectively.
[0062]
The non-inverted signal and the inverted signal of the analog switch drive signal 141 from the clock processing circuit 300 in FIG. 2 are input to the input nodes 540 and 541, respectively. The signals output from the output nodes 560 and 561 are input to the analog switch driving circuit 104 in FIG.
[0063]
Next, the operation in the configuration of FIG. 5 will be described in two cases.
[Case 1] When digit "1" is input to input node 540
In this case, the N-channel field effect transistor 503 turns on, and the output node 560 becomes about 0V. Then, the gate-source voltage of the P-channel field-effect transistor 502 is increased, and the P-channel field-effect transistor 502 is turned on, so that the output node 561 becomes about 2.5V. Since digit “0” is input to input node 541, N-channel field-effect transistor 504 is turned off. In addition, the P-channel field-effect transistor 501 has a small gate-source voltage and is turned off. As a result, the voltages of output nodes 560 and 561 are maintained.
[Case 2] When digit "0" is input to input node 540
In this case, output node 560 is at about 2.5V and output node 561 is at about 0V.
[0064]
As can be seen from the results of [Case 1] and [Case 2], the signal input from input node 540 is subjected to a NOT (NOT) operation, and the result is output from output node 560. The signal input from input node 541 is output from output node 561 as it is. The voltage of the input signal is boosted from 1.5V to 2.5V.
[0065]
Therefore, according to the configuration of FIG. 5, it is possible to select whether to output the analog switch drive signal 141 itself according to the state of the analog switch drive signal 141 input from the input nodes 540 and 541. . With this configuration, it is also possible to obtain the same effect as the configuration shown in FIGS.
[0066]
Note that the present invention is not limited to the above embodiment. For example, in FIG. 2, a plurality of voltage sources and a plurality of voltage values may be used for the analog power supply voltage 120 and the digital power supply voltage 130, respectively. Further, the operating voltage of the digital circuit unit 200 and the operating voltage of the clock processing circuit 300 may be different.
[0067]
The configuration of each logic gate in FIGS. 3 to 5 is not limited to the illustrated one, and another circuit capable of performing a logical operation may be used as necessary. As described above, the present invention can include various embodiments. Therefore, the present invention can be limited only by the invention specifying matters described in the claims that are appropriate from the above disclosure. It should not be understood that the description and drawings forming part of the disclosure in the above embodiments limit the present invention. From the above disclosure, those skilled in the art will recognize various alternative embodiments, examples, and operations. The technology seems to be understood.
[0068]
That is, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components in the implementation stage without departing from the scope of the invention. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Further, components of different embodiments may be appropriately combined.
[0069]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an analog / digital conversion circuit and a communication device capable of further reducing power consumption.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an embodiment of a communication device including an A / D conversion circuit according to the present invention.
FIG. 2 is a circuit block diagram showing an embodiment of an A / D conversion circuit according to the present invention.
FIG. 3 is a circuit diagram showing a configuration example of an analog switch driving circuit 104 in FIG. 2;
FIG. 4 is a circuit diagram showing another configuration example of the analog switch driving circuit 104 of FIG. 2;
FIG. 5 is a circuit diagram showing another configuration example of the analog switch driving circuit 104 of FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Receiving apparatus, 12 ... High frequency receiving circuit, 13 ... Quadrature demodulator, 14-1, 14-2 ... Analog / digital (A / D) conversion circuit, 15-1, 15-2 ... Resampler, 16-1, 16-2: Adaptive equalizer, 17-1, 17-2: Carrier reproducing unit, 18: Decoding processing unit, 19: Control unit, 20: Transmitting device, 30: Level converter, 32: Timing generation circuit, 40 ... Antenna, 50 hybrid circuit, 100 analog circuit section, 101 analog signal processing section, 102 digital signal processing section, 104 analog switch drive circuit, 105 analog switch circuit, 120 analog power supply voltage, 130 digital Power supply voltage, 200: digital circuit section, 201: analog circuit, 300: clock processing circuit, 301, 302: P-channel field effect Transistors, 303 NAND gates, 304 AND gates, 305 to 308 N-channel field effect transistors, 340, 341, 350, 351 input nodes, 360, 361 output nodes, 401, 402 P-channel field effect transistors 403 XOR gate, 404 XNOR gate, 405-410 N-channel field effect transistor, 440, 441, 450, 451 input node, 460, 461 output node, 501, 502 P channel field effect transistor, 503 504... N-channel field effect transistors, 540, 541... Input nodes, 560, 561.

Claims (6)

An analog circuit operating under a first operating power supply voltage;
A clock circuit that operates under a second operating power supply voltage lower than the first operating power supply voltage and generates a clock signal to be supplied to the analog circuit;
The analog circuit includes an analog processing unit that converts an input analog signal into a digital signal, an analog switch unit that controls the operation of the analog processing unit, and controls on / off of the analog switch unit by boosting the clock signal. An analog / digital conversion circuit, comprising: a switch driving unit that generates a driving signal to be driven. 2. The analog / digital conversion circuit according to claim 1, further comprising a digital circuit that operates under a third operation power supply voltage lower than said first operation power supply voltage. The analog switch unit includes:
First and second field-effect transistors each having a source supplied with the first operating power supply voltage and a gate connected to the drain of each other;
A NAND gate connected to the drain of the first field effect transistor;
2. The analog / digital conversion circuit according to claim 1, further comprising: an AND gate connected to a drain of the second field effect transistor. The analog switch unit includes:
First and second field-effect transistors each having a source supplied with the first operating power supply voltage and a gate connected to the drain of each other;
An exclusive OR gate connected to the drains of the first and second field effect transistors;
2. The analog / digital conversion circuit according to claim 1, further comprising: a NOT-OR gate connected to drains of the first and second field-effect transistors. The analog switch unit includes:
First and second field-effect transistors each having a source supplied with the first operating power supply voltage and a gate connected to the drain of each other;
A first NOT gate connected to the drain of the first field effect transistor;
2. The analog / digital conversion circuit according to claim 1, further comprising a second NOT gate connected to a drain of the second field effect transistor. A communication device comprising an analog / digital conversion circuit, wherein an analog reception signal is digitized by the analog / digital conversion circuit, and then the carrier is reproduced and demodulated.
The analog / digital conversion circuit includes:
An analog circuit operating under a first operating power supply voltage;
A clock circuit that operates under a second operation power supply voltage lower than the first operation power supply voltage and generates a clock signal to be supplied to the analog circuit;
The analog circuit includes:
An analog processing unit that converts an input analog signal into a digital signal;
An analog switch unit for controlling the operation of the analog processing unit;
And a switch drive section for boosting the clock signal to generate a drive signal for controlling on / off of the analog switch section.

Images