JP4110166B2 - Power control circuit and wireless communication device - Google Patents

Description

  The present invention relates to a power control circuit and a wireless communication device, and more particularly to a power control circuit with a short rise time from a power save mode and a wireless communication device having the power control circuit.

  An integrated circuit often requires a reference voltage (reference voltage) for circuit operation. For example, the reference voltage is used as an in-phase voltage of a differential amplifier circuit, a threshold voltage of a comparison circuit, and an upper limit voltage or a lower limit voltage of an analog signal handled by an A / D conversion circuit or a D / A conversion circuit.

  An electronic device such as a mobile phone that is premised on battery driving is usually provided with a power save mode in which power supply to an integrated circuit is temporarily interrupted in order to suppress power consumption during standby.

  The operation of the integrated circuit in the power save mode will be described with reference to FIG. 10 using the receiving circuit 100 mounted on the mobile terminal as an example. The reception circuit 100 includes a reference voltage generation circuit 101 and other circuit blocks 102. The other circuit block 102 includes an A / D conversion circuit that uses the constant voltage output from the reference voltage generation circuit 101 as a reference voltage. The switches 103 and 104 can select power supply / cut-off to the voltage generation circuit 101 and other circuit blocks 102 by turning on and off, respectively. The capacitive element 105 is connected in parallel to the output of the reference voltage generation circuit 101, and suppresses fluctuation of the output voltage of the reference voltage generation circuit 101 due to causes such as noise generated in the circuit block 102. During normal operation, the capacitive element 105 is charged by the voltage generated by the reference voltage generating circuit 101, and the voltage of the capacitive element 105 is equal to the output voltage of the reference voltage generating circuit 101.

In the power save mode, as disclosed in Japanese Patent Application Laid-Open No. 2004-164566 and the like, in the conventional receiving circuit 100, both the switches 103 and 104 are turned off to cut off the power of the entire receiving circuit 100. During this time, the charge charged in the capacitor 105 leaked at a constant rate.
JP2004-164566

  In the above prior art, the connection with the power source of the reference voltage generation circuit is disconnected in the power save mode. If it is disconnected, current cannot be supplied from the reference voltage generation circuit to the capacitive element connected to the output to ground, so the charge charged in the capacitive element leaks at a constant rate, and the output voltage Deviation from the value. When returning to the normal operation from the power save mode again, in order to restore the output voltage of the reference voltage generation circuit, it is necessary to compensate for the charge leaked from the capacitive element. This time has been one of the causes for delaying the rise time when the entire integrated circuit returns to the normal operation from the power saving mode.

  The present invention has been made to solve the above-described problems, and provides a power control circuit and a wireless communication apparatus that improve the delay of the rise time when returning from the power save mode to the normal operation mode. Objective.

A wireless communication device according to an aspect of the present invention includes:
A constant voltage generator that generates and outputs a constant voltage;
A circuit block connected to the output of the constant voltage generator and using the constant voltage as a reference voltage;
A capacitive element having one end connected to the output of the constant voltage generator and the other end connected to a reference potential terminal;
A switch for turning on / off the supply of power supply voltage to the circuit block;
A comparison circuit that compares the output voltage of the constant voltage generator with a threshold voltage and generates a first signal indicating whether the output voltage is equal to or lower than the threshold voltage ;
A signal input unit for inputting a second signal indicating whether the switch is on or off ;
When the first signal indicates that the output voltage is less than or equal to the threshold voltage or when the second signal indicates that the switch is on, power is supplied to the constant voltage generator, When the first signal indicates that the output voltage is greater than the threshold voltage and the second signal indicates that the switch is off, the supply of power to the constant voltage generator is stopped. A power control unit;
Is provided.

  According to the present invention, the delay of the rise time when returning from the power save mode to the normal operation mode can be improved.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit block showing a first embodiment relating to a power control circuit of the present invention.

  As shown in FIG. 1, a power control circuit (integrated circuit) 200 according to the present embodiment includes a reference voltage generation circuit 201 that outputs a constant voltage and other circuit blocks 202.

  The circuit block 202 includes a circuit (for example, an A / D conversion circuit) that performs a circuit operation using the constant voltage output from the reference voltage generation circuit 201 as a reference voltage.

  A constant voltage (reference voltage) output from the reference voltage generation circuit 201 is supplied from the output terminal 205 to the circuit block 202. Examples of the reference voltage include an upper limit voltage or a lower limit voltage of an analog signal handled by the A / D conversion circuit, or an intermediate voltage between a power supply voltage and a ground voltage supplied to the circuit block 202.

  The switch 204 is connected between the circuit block 202 and the power source. When the switch 204 is turned on, the circuit block 202 and the power source are short-circuited and opened when the switch 204 is turned off.

  The switch 203 is connected to either the terminal a or the terminal b. It is assumed that the current flowing through the reference voltage generation circuit 201 is larger when the switch 203 is connected to the terminal a than when the switch 203 is connected to the terminal b. That is, when the switch 203 is connected to the terminal a, more power is supplied to the reference voltage generation circuit 201 than when the switch 203 is connected to the terminal b.

  A capacitance element 206 is connected to the output of the reference voltage generation circuit 201 in a grounded manner. More specifically, one end of the capacitive element 206 is connected to the output of the reference voltage generation circuit 201, and the other end is connected to a reference potential terminal to which a reference potential (for example, ground potential) is applied.

  A circuit configuration example of the reference voltage generation circuit 201 is shown as a reference voltage generation circuit 300 in FIG. The power supply voltage is divided by the resistor 301 and the resistor 302 to create a desired constant voltage V1 and input to the voltage follower circuit 303. Since the input impedance of the voltage follower circuit 303 is large and the current flowing from the resistor strings 301 and 302 to the voltage follower circuit 303 can be ignored, the voltage V1 is kept constant. The voltage follower circuit 303 outputs a voltage V1 ′ that substantially matches the input voltage V1. A capacitive element 304 is added in parallel to the output of the voltage follower circuit 303. The capacitive element 304 functions as a bypass capacitor (bypass capacitor) and can suppress fluctuations in the output voltage V1 ′ of the reference voltage generation circuit 201 due to, for example, noise in the circuit block 202. However, in order to set the output voltage of the reference voltage generation circuit 201 to V1 ′, it is necessary to charge the capacitor 304 with a charge corresponding to the output voltage V1 ′. The capacitor 304 corresponds to the capacitor 206 in FIG.

  The amplifier circuit used for the voltage follower circuit 303 has a circuit configuration such as the amplifier circuit 400 of FIG. The amplifier circuit 400 includes a main part (constant voltage generation part) 401 and a power control part 409. 2 is input to the input terminal IN, and the voltage V1 'of FIG. 2 is output from the output terminal OUT. The NMOS transistor 402 supplies a bias current to a main part 401 composed of an input differential pair (NMOS transistors M1, M2) and an active load (PMOS transistors M3, M4). The NMOS transistor 403 has a gate terminal and a drain terminal connected in common. The gate terminals of the NMOS transistor 402 and the NMOS transistor 403 are commonly connected to form a current mirror circuit. A current source 405 is connected to the drain terminal of the NMOS transistor 403 via the NMOS transistor 404, and a current source 406 is connected to the drain terminal of the NMOS transistor 403. The structure of the main part 401 is as follows. The drain terminal of the NMOS transistor M1 and the drain terminal of the PMOS transistor M3 are connected. The drain terminal of the NMOS transistor M2 and the drain terminal of the PMOS transistor M4 are connected. The gate terminals of the PMOS transistors M3 and M4 are connected in common, and these gate terminals are connected to the drain terminal of the PMOS transistor M3. The gate terminal of the NNOS transistor M2 is connected to the drain terminal of the NMOS transistor M2 and the output terminal OUT. The source terminals of the PMOS transistors M3 and M4 are commonly connected to the power supply. The source terminals of the NMOS transistors M1 and M2 are commonly connected to the drain terminal of the NMOS transistor 402.

  The NMOS transistor 404 functions as a switch, and the NMOS transistor 403 and the current source 405 are short-circuited / opened by the voltage of the gate terminal 407. When the voltage of the gate terminal 407 becomes high level, the NMOS transistor 403 and the current source 405 are short-circuited, and two currents of the current sources 405 and 406 flow to the NMOS transistor 403. When the voltage of the gate terminal 407 becomes low level, the NMOS transistor 403 and the current source 405 are opened, and only the current of the current source 406 flows to the NMOS transistor 403. For example, if the currents of the current sources 405 and 406 are equal, the bias current flowing from the NMOS transistor 402 to the main part 401 is halved when the voltage at the gate terminal 407 is at a low level compared to when the voltage at the gate terminal 407 is at a high level. The case where the switch 203 in FIG. 1 is connected to a / b corresponds to the case where the voltage of the gate terminal 407 is high level / low level.

  When the mode is shifted to the power save mode, the switch 204 is turned off to open the circuit block 202 and the power source. At the same time, the connection of the switch 203 is switched from the terminal a to the terminal b, and the bias current flowing through the reference voltage generation circuit 201 is reduced. In this way, the charge leaked from the capacitor 304 during the power save mode is not biased in the reference voltage generation circuit 201 without disconnecting the connection between the reference voltage generation circuit 201 and the power supply as in the conventional case and with low power consumption. Can be supplemented with current. Therefore, even when the normal operation is resumed from the power save mode, the time required to recharge the voltage of the capacitor 304 to V1 ′ can be shortened, and the rise time of the reference voltage generation circuit can be shortened.

  By the way, as described above, the circuit block 202 of FIG. 1 is realized as an A / D conversion circuit, for example. An example of the A / D conversion circuit is a pipeline type A / D converter. A pipeline type A / D converter is formed by cascading conversion stages for converting an input analog signal into a digital signal. Each conversion stage is a switched capacitor circuit, and is mainly composed of an operational amplifier, a capacitive element, and a switch. The switched capacitor circuit creates two states, a sample mode and a hold mode, by turning on / off the switch, and outputs an input signal while alternately repeating these two modes. In the case of a pipeline type A / D converter, one conversion stage can be applied as the circuit block 202. An example in which the conversion stage is used as the circuit block 202 is briefly shown below.

  FIG. 4 is a block diagram showing the configuration of the conversion stage.

  As described above, this conversion stage has a sample mode and a hold mode.

In the sample mode, the conversion stage charges the input signals Vi to the capacitive elements Cs and Cf. FIG. 4 shows a state in the sample mode, in which the switch S ₁ is grounded and the switches S ₂ and S ₃ are connected to the input signal Vi side.

In the hold mode, an output signal Vo corresponding to the voltage of the input signal charged in the sample mode is output. At this time, the operation of the switch, the switch S ₁ is turned off, the switch S ₂ is connected to the output side of the operational amplifier 31, the switch S ₃ is, DAC (Digital-to-Analog Converter: D / A converter) side Connected to. In DAC, MUX (multiplexer) input to and + Vref to zero, among the reference voltage -Vref, any one is selected and via a switch S ₃ reference voltage that is selected to the capacitance Cs Is output. Which reference voltage is selected depends on the voltage of the input signal Vi input in the sample mode. More specifically, the input signal Vi is input to the preamplifiers 32 and 33 in the sample mode, and the outputs of the preamplifiers 32 and 33 are input to the latch 34. The state of the latch 34 is determined in three stages according to the inputs from the preamplifiers 32 and 33, and which reference voltage is selected according to the state of the latch 34 is determined. The output voltage Vo differs depending on the reference voltage. The output voltage Vo is determined by the following equation.

  Here, the reference voltage input to the MUX (multiplexer) is generated by the circuit 300 of FIG. For example, three circuits 300 are prepared, + Vref is generated by the first circuit, 0 is generated by the second circuit, and -Vref is generated by the third circuit. Here, 0 indicates an intermediate voltage between the power supply voltage and the ground potential, and the absolute value | Vref | of ± Vref indicates 1/4 of the difference voltage between the power supply voltage and 0. The charge charged in the capacitor 304 in the circuit 300 moves between the capacitor Cs in the hold mode, and the charge of the capacitor 304 becomes excessive or insufficient. In this embodiment, part of this excess and deficiency is compensated by supplying current from the voltage follower circuit 303 to the capacitor 304.

  That is, when the power of the voltage follower circuit 303 is completely cut off in the power save mode, current supply to the capacitor 304 cannot be performed. In general, there is a charge leakage from a capacitive element at a constant rate for a fixed time, and the charged charge gradually disappears. Therefore, when shifting from the power save mode to the normal operation mode, the A / D converter (or the conversion stage) cannot operate normally until the voltage follower 303 completes the leakage charge, and the rise time becomes longer. End up. Increasing the current supply capability of the voltage follower circuit 303 can shorten the rise time, but this increases the power consumption of the entire circuit. Therefore, as in the present embodiment, when a current sufficient to compensate the leakage charge is supplied to the voltage follower circuit 303 in the power save mode, the rise time is shortened and the power of the voltage follower circuit 303 during normal operation is reduced. Can be reduced.

  FIG. 5 is a block diagram showing a configuration of a wireless communication apparatus incorporating the integrated circuit of FIG. Each of the A / D converters 14-1 and 14-2 in FIG. 5 corresponds to the integrated circuit in FIG. 1, and the circuit block 202 in the integrated circuit corresponds to an A / D conversion circuit.

  This communication apparatus is applied to a system that employs a multi-level QAM modulation scheme such as 64QAM or 256QAM. The communication device includes an antenna 40, a hybrid circuit 50, a receiving device 10, a transmitting device 20, and a control unit 19. The transmission signal given to the transmission device 20 is subjected to multilevel QAM modulation and output from the antenna 40 via the hybrid circuit 50. The multilevel QAM modulated signal arriving at the antenna 40 is given to the receiving device 10 via the hybrid circuit 50, and a demodulated received signal is output.

  The receiving apparatus 10 includes a high frequency receiving circuit (RF / IF) 12, an orthogonal demodulator 13, A / D converters 14-1 and 14-2, resamplers 15-1 and 15-2, and an adaptive equalizer. 16-1, 16-2, carrier (carrier wave) reproducing units 17-1, 17-2, and a decoding processing unit 18.

  The control unit 19 includes A / D conversion circuits 14-1 and 14-2, resamplers 15-1 and 15-2, adaptive equalizers 16-1 and 16-2, and a carrier (carrier wave) reproducing unit 17- 1, 17-2 and the transmission device 20 are controlled.

  The QAM modulated signal arriving at the antenna 40 is subjected to filtering and low-noise amplification in a high-frequency receiving circuit (RF / IF) 12, and then converted into an intermediate frequency signal. This intermediate frequency signal is subjected to filtering processing, AGC processing, and the like, and is input to the quadrature demodulator 13.

  The intermediate frequency signal supplied to the quadrature demodulator 13 is quadrature demodulated, and a complex baseband signal of I channel (I-ch) and Q channel (Q-ch) orthogonal to each other is output. The baseband signals of each channel are input to A / D conversion circuits 14-1 and 14-2, respectively, and converted into digital signals.

  The digital signals of the respective channels are input to the resamplers 15-1 and 15-2, resampled at a predetermined sampling rate and sampling timing, and synchronized with each other. This makes it possible to arbitrarily design the sampling rates of the A / D conversion circuits 14-1 and 14-2.

  The outputs of the resamplers 15-1 and 15-2 are given to adaptive equalizers 16-1 and 16-2, respectively, and subjected to processing for compensating for delay distortion and reducing intersymbol interference. The outputs of the adaptive equalizers 16-1 and 16-2 are respectively supplied to the carrier reproducing units 17-1 and 17-2, and dropped to the baseband by the carrier reproducing units 17-1 and 17-2. (Carrier frequency error) and phase offset are removed. Thus, the obtained complex baseband signal is QAM decoded in the decoding processing unit 18.

  Resample timing and sampling frequency in the resamplers 15-1 and 15-2, input / output timing and tap coefficient update processing in the adaptive equalizers 16-1 and 16-2, input in the carrier regeneration units 17-1 and 17-2 The output timing, the reproduction method, and the like are flexibly controlled by the control unit 19. The control unit 19 is realized by a rewritable device such as a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), or a PLD (Programmable Logic Device), and can easily change parameters and control contents.

  The adaptive equalizers 16-1 and 16-2 are implemented by including a shift register, a MAC (product-sum operation unit) and the like in order to handle signals in the digital signal region. The number of taps in the shift register is optimized according to the system specifications.

  In the above, the control unit 19 controls the switches 203 and 204 (see FIG. 1) in each of the A / D converters 14-1 and 14-2 according to the power save mode and the normal operation mode.

  FIG. 6 is a flowchart for explaining control processing of the switches 203 and 204 by the control unit 19.

  In the normal operation mode, the control unit 19 connects the switch 203 to the terminal a (for example, sets the voltage at the gate terminal 407 in FIG. 3 to high level) and turns on the switch 204 (A1). When the operation of the wireless communication device is finished (YES in A2), the operation is finished. If not (NO in A2), it is determined whether or not the mode is shifted to the power saving mode (A3). When shifting to the power saving mode (YES in A3), the switch 203 is connected to the terminal b (for example, the voltage of the gate terminal 407 is set to the low level), and the switch 204 is turned off (A4). If it has not changed to power save mode (NO in A3) or after A4, it is determined whether it has changed to normal operation mode (A5), and if it has not changed (NO in A5), it returns to A2. When the transition is made, the switch 203 is connected to the terminal a (or the connection to the terminal a is maintained), and the switch 204 is turned on (or the on state is maintained) (A6).

  As described above, according to the present embodiment, in the power save mode, the circuit block that uses the output voltage of the reference voltage generation circuit as the reference voltage disconnects the connection with the power supply as in the conventional case, but the reference voltage generation circuit For this reason, the power supply is not cut off completely, and less power is supplied than in normal operation, so that the current continues to be supplied to the capacitive element. Delay can be improved.

(Second Embodiment)
The description overlapping with the above-described embodiment is omitted for the sake of brevity.

  FIG. 7 is a circuit block diagram showing a second embodiment relating to the power control circuit of the present invention.

  The power control circuit (integrated circuit) 500 in FIG. 7 is different from the integrated circuit 200 in FIG. 1 in a switch 507 connected between the reference voltage generation circuit 501 and the power source.

  The switch 507 is switched by a clock signal 503 input from an external clock source. When the clock signal 503 is at a high level, the switch 507 is turned on, and the reference voltage generation circuit 501 and the power supply are short-circuited. When the clock signal 503 is at a low level, the switch 507 is turned off, and the reference voltage generation circuit 501 and the power source are opened.

  During normal operation, the switch 507 is always on. In the power save mode, the switch 507 is repeatedly turned on / off by a clock signal. At this time, a current smaller than that during normal operation is supplied to the reference voltage generation circuit 501 as an average value.

  In this way, it is possible to compensate for the charge leaked from the capacitive element 506 connected in parallel to the output of the reference voltage generation circuit 501 even in the power save mode. Therefore, even when the mode is shifted again from the power save mode to the normal operation, the time required for recharging the capacitor 506 can be shortened, and the rise time of the reference voltage generation circuit 501 can be shortened. Also, if you want to increase the rise time of the reference voltage generator circuit 501, change the duty ratio of the clock signal to be input, such as extending the on time longer than usual, so that the reference voltage can be met according to the requirements of the electronic equipment to be used. The rise time of the generation circuit 501 can be flexibly changed.

  As the reference voltage generation circuit 501, for example, the reference voltage generation circuit 300 of FIG. 2 can be used. As an amplifier circuit used for the voltage follower circuit 303 in the reference voltage generation circuit 300, for example, an amplifier circuit 600 shown in FIG. 8 can be used. The amplifier circuit 600 includes a main part 601 and a power control part 609. A main part 601 and NMOS transistors 602 and 603 in the amplifier circuit 600 are the same as those in the amplifier circuit 400 of FIG.

  Depending on the high level / low level of the voltage at the input terminal 606 of the inverter circuit 605, the NMOS transistors 607 and 608 used as switches are turned on / off, so that it is possible to select whether or not to apply a bias current to the main part 601. More specifically, when the voltage at the input terminal 606 is at a high level, the NMOS transistor 607 is turned on, and the current of the current source 604 flows through the NMOS transistor 603. When a current flows through the NMOS transistor 603, a current also flows through the NMOS transistor 602 constituting the current mirror circuit. A current flowing through the NMOS transistor 602 is supplied as a bias current of the main part 601. At this time, the NMOS transistor 608 is off and no current flows through the NMOS transistor 608. On the other hand, when the voltage at the input terminal 606 is at a low level, the NMOS transistor 607 is turned off and the NMOS transistor 608 is turned on. Then, since the gate terminal of the NMOS transistor 602 is connected to the ground (GND) via the NMOS transistor 608, the drain current of the NMOS transistor 602 does not flow, and the bias current of the main part 601 is cut off. The voltage at the input terminal 606 continues to supply a bias current to the main part 601 by keeping the normal operation at a high level. On the other hand, in the power save mode, a clock signal is input to the input terminal 606, and supply / cut-off of the bias current to the main part 601 is repeated. Thus, the function of the switch 507 in FIG. 7 can be realized.

(Third embodiment)
The description overlapping with the above-described embodiment is omitted for the sake of brevity.

  FIG. 9 is a circuit block diagram showing a third embodiment relating to the power control circuit of the present invention.

  As shown in FIG. 9, a power control circuit (integrated circuit) 700 according to the present embodiment has a comparison circuit 703 added to the output of the reference voltage generation circuit 701. The switch 702 is turned on / off according to the output result of the comparison circuit 703. The threshold voltage of the comparison circuit 703 is designed to be, for example, a voltage V3 that approximately matches the output voltage V1 ′ of the reference voltage generation circuit 701. The voltage V3 is generated by, for example, resistance division by the resistors 708 and 709 and is input to the comparison circuit 703. The output of the comparison circuit 703 is at a high level when the voltage at the output terminal 704 is equal to or lower than the voltage V3, and is at a low level otherwise. The switch 702 is also designed to be turned on / off by an external signal input from the input terminal 705. For example, the output signal of the comparison circuit 703 and the external signal input from the input terminal 705 are input to the OR circuit 707 having two inputs, and the switch 702 is turned on / off by the output of the OR circuit 707. Thereby, the switch 702 is turned on when one of the input signals of the OR circuit 707 is at a high level. As a circuit configuration of the reference voltage generation circuit 701, for example, the circuit shown in FIG. 8 can be used.

  During normal operation, the external signal input from the input terminal 705 is set to high level and the switch 702 is turned on, thereby short-circuiting the reference voltage generation circuit 701 and the power source. On the other hand, in the power save mode, the external signal input from the input terminal 705 is set to the low level. In this way, ON / OFF of the switch 702 is determined only by the output of the comparison circuit 703. When charge leaks from the capacitor 706 and the voltage at the output terminal 704 becomes equal to or lower than the voltage V3, the switch 702 is turned on, and current is supplied from the reference voltage generation circuit 701 to the capacitor 706. Thus, the charge charged in the capacitor 706 during normal operation is maintained even during the power save mode. Therefore, even when the mode is changed again from the power save mode to the normal operation, the time required for recharging the capacitor element 706 is shortened, so that the rise time of the reference voltage generation circuit 701 is shortened. Further, an external signal for turning on / off the switch 702 in the power save mode is not required, and the control of the electronic device can be simplified.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a diagram illustrating a circuit block configuration example of an integrated circuit according to a first embodiment. 1 is a diagram illustrating a configuration example of a reference voltage generation circuit of an integrated circuit according to a first embodiment. The figure which shows the voltage follower circuit structural example of the reference voltage generation circuit in connection with 1st Embodiment. The figure which shows the structural example of the conversion stage in a pipeline type A / D converter. FIG. 2 is a diagram illustrating a configuration example of a wireless communication device in which the integrated circuit of FIG. 1 is incorporated. The flowchart explaining the control processing of the switch by a control part. FIG. 6 is a diagram illustrating a circuit block configuration example of an integrated circuit according to a second embodiment. The figure which shows the voltage follower circuit structural example of the reference voltage generation circuit in connection with 2nd Embodiment. FIG. 10 is a diagram illustrating a circuit block configuration example of an integrated circuit according to a third embodiment. The circuit block diagram of the integrated circuit used for the conventional receiving circuit.

Explanation of symbols

200, 400, 500, 600, 700 integrated circuits
201, 501, 701 Reference voltage generator
202, 502 circuit block
203, 204, 504, 507, 702 switch
205, OUT, 505, 704 output terminals
206, 304, 706 capacitors
303 voltage follower circuit
301, 302, 708, 709 resistors
401, 601 main parts
M1, M2, 402, 403, 404, 602, 603, 607 NMOS transistors
405, 406, 604 Current source
407 Gate terminal
503 clock signal
605 inverter
606 input terminal
703 comparator
705, IN input terminal
707 OR circuit
M3, M4 PMOS transistors

Claims (3)

A constant voltage generator that generates and outputs a constant voltage;
A circuit block connected to the output of the constant voltage generator and using the constant voltage as a reference voltage;
A capacitive element having one end connected to the output of the constant voltage generator and the other end connected to a reference potential terminal;
A switch for turning on / off the supply of power supply voltage to the circuit block;
A comparison circuit that compares the output voltage of the constant voltage generator with a threshold voltage and generates a first signal indicating whether the output voltage is equal to or lower than the threshold voltage ;
A signal input unit for inputting a second signal indicating whether the switch is on or off ;
When the first signal indicates that the output voltage is less than or equal to the threshold voltage or when the second signal indicates that the switch is on, power is supplied to the constant voltage generator, When the first signal indicates that the output voltage is greater than the threshold voltage and the second signal indicates that the switch is off, the supply of power to the constant voltage generator is stopped. A power control unit;
Power control circuit with   The power control circuit according to claim 1, wherein the circuit block is an A / D conversion circuit.   A wireless communication apparatus comprising an A / D converter including the power control circuit according to claim 2, wherein an analog received signal is digitized and demodulated by the A / D converter.

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