JPS59228430A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To decrease the element size of defferential transistor (TR) and to improve the dielectric strength by providing a TR in series between a collector of the differential TR and a power supply voltage in a differential input type level converting circuit. CONSTITUTION:A constant current source having a TRQ3 is connected to the differential TR comprising TRs Q11, Q12, Q2 and resistors R1, R2 so as to constitute the level converting circuit. TRs Q4, Q5 are inserted separately between the TRs Q11, Q12 and the resistor R1 and between the TRQ2 and the resistor R2 and the bases are connected to a low potential being lower than a power supply voltage VCC. A voltage applied between the emitter and collector of the differential pair TRs is reduced by providing the TRs Q4, Q5.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technique that is particularly effective when applied to semiconductor circuit technology.
Regarding a level conversion circuit for converting to an L level signal, I! ! The present invention relates to a technique effective for use in a level conversion circuit suitable for being integrated into a semiconductor integrated circuit.

[Background technology]

The present invention will be described in detail based on studies conducted by the inventor.

When configuring a system such as a computer by combining a logic LSI (large-scale integrated circuit) and memory, the logic LSI is replaced with an EO, which has a faster operating speed than a TTL (transistor-transistor-logic) circuit, in order to speed up the system.
L (emitter coupled logic) circuit or O
It may be configured using a logic circuit called ML (current mode logic).

However, since memories are generally TTL level integrated circuits, it has been found that when a system is configured by a logic LSI consisting of an EOL circuit and a TTL level memory, a level conversion circuit is required between the two.

Figure 1 shows that in such a case, the EOL level signal of -0.9 to -1.7V is converted to a TTL level signal of +0.3 to 3.7V. 1 shows an example of the configuration of a level conversion circuit developed by the inventor of the present invention prior to the present invention. However, in the level conversion circuit shown in Figure 1, the differential input circuit consists of differential transistors Q and Q.
, are connected to a positive power supply voltage Vcc such as +5V, and a resistor R3 on the emitter side of the constant current transistor Q3 is connected to a negative power supply voltage v0 such as -5.2V. Therefore, transistor Q++Q
There is a possibility that a voltage of 7V or more may be applied between the collector and emitter of No. 2.

However, in recent years, there has been an increasing demand for higher speed LSIs, and therefore it is desired that the level conversion circuit shown in FIG. 1 also be faster. Therefore,
It is conceivable to increase the speed of level conversion by miniaturizing the LSI and reducing the element dimensions of transistors Q+ and Q-.

However, when LSIs are miniaturized and the element dimensions of transistors Q1 and Q2 are reduced, the withstand voltage of the transistors decreases. The inventor of the present invention has clarified that there is a problem in that the withstand voltage is insufficient and it is not possible to withstand a potential difference of 7μ.

[Purpose of the invention]

One object of the present invention is to provide a semiconductor circuit that can handle high potential differences using low-voltage transistors.

One object of the present invention is to provide a semiconductor integrated circuit with small element dimensions.

One object of the present invention is to provide a semiconductor circuit that operates at high speed.

One object of the present invention is to provide a level conversion circuit that can operate at high speed.

One object of the present invention is to provide a level conversion circuit suitable for semiconductor integrated circuits.

One object of the present invention is to provide a level conversion technique suitable for high integration.

One object of the present invention is to provide high-voltage circuit technology suitable for high-speed logic circuits.

The above and other objects and novel features of the present invention include:
It will become clear from Description 2 of this specification and the attached drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides a differential input type level conversion circuit in which, for example, a new transistor is provided between the collector of the differential transistor and the power supply voltage, and is connected in series with the differential transistor, and the base of the added transistor is connected in series with the differential transistor. By applying a constant voltage lower than the power supply voltage, such as the ground potential of the circuit, to the circuit, the potential difference applied between the collector and emitter of the differential transistor is reduced, thereby reducing the element size of the differential transistor. The above object is achieved by preventing the differential transistor from being destroyed even if the withstand voltage of the differential transistor decreases as the speed increases.

The present invention will be specifically explained below using the drawings.

〔Example〕

FIG. 2 shows an embodiment of a level conversion circuit according to the present invention. In the figure, QotQt is a differential transistor forming a differential input circuit, and although not particularly limited, in this embodiment, an input transistor Q12 is provided in parallel with the transistor Qo, and the transistors Qo and QI! The input signals vIn1 and vin2 are applied to the bases of .

Moreover, the input i signal vi is connected to the base of the differential transistor Q.
By applying the Luherno reference voltage vref, which is approximately intermediate between the low level and the high level of n, as a logic threshold, it is possible to perform logic operations simultaneously with level conversion.

Common emitter and power supply voltage of the above differential transistors Q, I and Q10. A constant current transistor Q and a resistor R8 are connected between the constant current transistor Q and the resistor R8, as in the case of FIG. Transistor Q3 has a constant reference voltage Vr at its base.
By applying ef2, it operates as a constant current source.

Further, in this embodiment, the differential transistors Qo and Q
Separate transistors Q4 and Q, J are provided between the collectors of 2 and the resistors R+-R4, respectively, and are connected in series with the transistors Q+++Q+t. At the bases of these transistors Qo and Q+t, there is a power supply voltage (2), such as the ground potential of the circuit. A voltage of one foot lower than that is applied.

Therefore, for example, if the power supply voltage Vcc is +5■, the emitter voltage of transistors Q4 and Q is -07V, which is lower than the ground potential (0■), which is the base potential, by the base-emitter voltage of 0.7V. Therefore, a maximum voltage of about 5.7 cm is applied between the collector and emitter when transistors Q and Q2 are off.

On the other hand, for the differential transistor Q++, the collector voltage is <-0.7V as mentioned above, and the emitter voltage is -0.
If the voltage is set to 8 to -1.6V, then the base-emitter voltage is lowered by 0.7V to about -1.5 to -2.3V. Therefore, a maximum voltage of only about -1.6 V is applied between the collector and emitter of the differential transistor Qn.

Also, for the differential transistor Q, the base is -1, which is approximately halfway between the high level and low level of the input signal v1n.
, 2 to -1, 3■, the collector voltage is 10.7V and the emitter voltage is -1 which is 70 minutes lower than the reference voltage ref1.
,9 to -2,OV, only a voltage of -1,2 to -1,3■ is applied between the collector and emitter.

In this way, in the above embodiment, the differential transistor Q++
e Q+t+ Q2 is of course a new transistor Q-
= Regarding Qa, there is also 5 between the collector and emitter.
．． No voltage of 7 or higher is applied. Therefore, the withstand voltage of the transistor can be lowered compared to the circuit shown in FIG. 1, so the element size of the transistor Qn*Q+t+Q can be reduced to speed up the level conversion operation.

Furthermore, in this case, a new transistor Q4 is added between the collector of the differential transistor Q+z (L and the resistors R, , R2).
Even if transistors Q and Q are inserted, transistors Q4 and Q,
The ground potential is applied to the base, and it is always turned on. Therefore, from a circuit perspective, transistor Q4
This is the same as not having transistors Q4 and Q, and the circuit of the embodiment has transistors Q4 and Q.

It has the same logical operation as a temporary one, and its operation speed is not slowed down.

Therefore, input signal vin1. When both vtn2 are brought to low level, the transistor Qot Ql! is cut off, current flows through the differential transistor Q, and the output V
. U, is set to a low level of 2 to 3 V due to the voltage drop across the resistor R7. However, when at least one of the input signals vin1 and vin2 is brought to the high level, the transistor (Ql or Q+t) is turned on, current flows through the resistor R7, and the transistor Q is cut off. Therefore, the output V. ut is the power supply voltage ■c
It is set to a level such as +5V, which is close to c.

In this case, the output V. The low level of ut is determined by the resistance value of the resistor R3, and in the embodiment, it can be lowered to a range that does not saturate the transistor Q, and the output V. It is possible to lower U to about -0.5 .

〔effect〕

By connecting a transistor whose base is grounded in cascade between the differential pair transistor and a resistor connected in cascade to the collector, the voltage applied between the emitter and collector of the differential pair transistor can be reduced, resulting in a low breakdown voltage. With these transistors, it is possible to construct a circuit that can handle high potential differences.

By constructing a circuit such as the one described above using a semiconductor integrated circuit with reduced element dimensions, it is possible to construct a circuit that is highly integrated and can handle a large potential difference.

Further, by reducing the element dimensions, a semiconductor integrated circuit capable of high-speed operation can be provided.

In a differential input type level conversion circuit, separate transistors are connected in series between a pair of differential transistors and one power supply voltage of the circuit, and the control terminal (base) of this new transistor is Since we applied a constant voltage lower than the above power supply voltage,
The voltage applied between the terminals of the differential transistor is reduced, which reduces the element dimensions of the transistors that make up the level conversion circuit and increases the speed of the circuit. Even if the withstand voltage of the differential transistor is reduced, A voltage higher than the withstand voltage is not applied, and the element is prevented from being destroyed. As a result, a circuit that takes advantage of high-speed element performance due to miniaturization of LSI including a level conversion circuit can be realized.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, as shown in FIG. 3, the level conversion circuit converts the input buffer circuit A, the internal logic section B at the EOL level, and the output signal of the logic section B into 'DT, L, and output levels. The present invention can be applied to an interface LSI such as a memory driver, which includes an output circuit 0.

Note that when the present invention is applied to the above-mentioned interface LSI, the output circuit section is provided with a plurality of output circuits each having different output characteristics in accordance with the characteristics of the circuit to be connected, such as a memory element. Only one level conversion circuit as described above can be provided in front of these plurality of output circuits so that they can be shared.

Further, it is also possible to provide the above-mentioned interface LSI with a circuit that drives a memory element or the like and converts a TTL level signal outputted therefrom back to an EOL level.

Note that in the above embodiment, the differential transistors Q1. .

A ground potential is applied to the bases of transistors Q4 and Q, which are connected in series between Q and resistors R, R, but is not limited to this, and is lower than the power supply voltage ■cc. You can use any other constant voltage if you have one.

Furthermore, although the embodiment has described a level conversion circuit configured with bipolar transistors, this invention
It can also be applied to a level conversion circuit made of SFET.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to a level conversion circuit in an ECL circuit, which is the background field of application, but the invention is not limited thereto. It can be applied to logic circuits, etc.

The present invention can be applied at least to a circuit that handles all high potential differences using low-voltage transistors.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration example of a differential input type level conversion circuit developed by the present inventor prior to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a level conversion circuit according to the present invention, FIG. 3 is a block diagram showing a configuration example of an interface LSI including the level conversion circuit of the present invention. Qn*Qt...differential transistor, Q3...constant current transistor, Q4*Qs...transistor, R,, R,...resistance, vin...input voltage, vo
ut...Output voltage. Figure 1 1rEt (-6,2'F) Figure 2 1000E Figure 3

Claims (1)

[Claims] 1. A level converter circuit equipped with a differential input circuit having a pair of differential transistors, wherein separate transistors are connected in series between the differential transistors and the 10,000 power supply voltage terminals of the circuit, A semiconductor circuit in which a constant voltage lower than the power supply voltage is applied to a control terminal of the transistor.