JPH02126720A - Transistor circuit - Google Patents

Abstract

PURPOSE:To prevent the increase of the current consumption and the malfunction and to obtain a high action margin by providing a resistance element between the base and emitter of a transistor of an output circuit. CONSTITUTION:Between the base and emitter of a Tr Q1 of an output circuit 2 of a BiCMOS circuit combining a CMOSFET circuit and a bipolar transistor Tr, a resistance element R is connected. Thus, when the output of a CMOS gate comes to an 'H' level, after the output terminal of the circuit 2 rises up to VCC-phiBE by the Tr Q1, further, it is charged through a resistance element R and rises up to a power source potential VCC completely. When the output of the CMOS gate comes to an 'L' level, the Tr Q1 is turned off, a Tr Q2 is turned on, the output terminal is reduced to the phiBE, thereafter, further, completely falls through the resistance element R and an (n) channel MOSFETM2 in which the CMOS gate is turned on, to a ground potential VSS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a transistor circuit, and particularly to a BiCMO3 circuit that combines a CMOS circuit and a bipolar transistor.

(Prior Art) BiCMOS circuits are attracting attention as they have both the low power consumption characteristics of CMOS circuits and the high driving performance characteristics of bipolar transistors, and are used in gate arrays, various logic integrated circuits,
It has come to be used in high-speed DRAM, high-speed SRAM, etc.

FIG. 6 shows a B1CMOS inverter which is an example of the basic configuration of a conventional BiCMO3 circuit. The p-channel MOS transistor M1 and the n-channel MOS transistor M2 are
The CMOS inverter 1 is made up of B4. A first npn bipolar transistor Q1 and a second npn bipolar transistor Q2, which are totem-pole connected between a power supply VCC and a ground VSS, constitute an output circuit 2. The base of the first bipolar transistor Q1 is a CMOS inverter 1
It is controlled by the potential of the output terminal (node A) of. 1st
An n-channel 1-lock OS transistor M3 is connected between the output terminal (node B) of the output circuit 2, which is the connection terminal between the emitter of the bipolar transistor Q1 and the collector of the second bipolar transistor Q2, and the base of the second bipolar transistor Q2. It is connected. The gate of this MOS transistor M3 is controlled by the input terminal potential of the CMOS inverter 1. This MOS transistor M3 is C
It functions to short-circuit between the collector and base of the second bipolar transistor Q2 according to the input signal of the MOS inverter 1. In other words, this MOS transistor M3 is
transmitting the emitter potential of the first bipolar transistor Q1 to the base of the second bipolar transistor Q2;
This is an on-drive MOS transistor for turning on the second bipolar transistor Q2. An n-channel MOS transistor M4 is connected between the base of the second bipolar transistor Q2 and the ground, and its gate is controlled by the potential of the node A. This M
The OS transistor M4 functions to discharge the base charge of the second bipolar transistor Q2 according to the output of the CMOS inverter 1, and can be said to be a MOS transistor for off-driving the second bipolar transistor Q2.

FIG. 7 shows the operating waveforms of such an iCMOS inverter. Here, a case is shown in which Vcc = 5V, Vss = OV, and a clock with an amplitude of 5V is applied as the input signal Vln. When the input signal Vin changes from H" level (5V) to "L" level (OV), node A, which is the output terminal of CMOS inverter 1, is charged to Vcc = 5V by p-channel MO8 transistor M1. As a result, the output circuit The first bipolar transistor Q1 of No. 2 is turned on.At this time, the off-drive MOS transistor M3 is off, and the off-drive MOS transistor M4 is turned on.
is turned on, the base charge of the second bipolar transistor Q2 constituting the output circuit 2 is extracted through the MOS transistor M4, and the second bipolar transistor Q2 is turned off. As a result, the output signal Vout becomes 'H1 level.

Next, when the human input signal Vln of the CMOS inverter 1 becomes "H" level, the node A becomes "L" level, and the first bipolar transistor Q+ is turned off.At this time, M
OS transistor M3 is turned on and transmits the potential of node B to the base of second bipolar transistor Q2. In other words, the second bipolar transistor Q2 is in an on state with its collector and base short-circuited and diode-connected. Furthermore, MOS transistor M4 is turned off. As a result, the output signal Vout becomes "L" level.

In the above operation, the "H" level of the output signal v out does not rise to the power supply potential of 5V, as shown in FIG. 7, but remains at about 4.3V. This means that even if the base potential of the first bipolar transistor Q1 reaches 5mm, the base-emitter voltage remains at the built-in voltage (φBE-0.7V).
) or below, it turns off. Also, the output signal v
“L” for out.

As shown in FIG. 7, the level did not decrease to OV, but 0.
It stops at around 7V. This is because the second bipolar transistor Q2 is turned on with a diode connection, so that the on-voltage is limited by the built-in voltage φBE between the base and emitter.

In this way, in the conventional B1CMOS inverter, even if a full amplitude input signal is applied, the output signal is "H".

Sufficient level is not produced on both the level side and the "L" level side.

This adversely affects the switching operation of the circuit connected to the next stage of this B1CMOS inverter. For example, consider a case where two stages of B1CMOS inverters are connected. The threshold values (absolute values) of the input stage n-channel and p-channel MOS transistors of each inverter are set equal to Vt.
Let it be h.

When Vth>φBH, no malfunction occurs even if the output of the first stage inverter, that is, the input of the second stage has an amplitude in the range from φBE to VCC-φ8E. However, vt
When h<φBH, the second stage inverter is a p-channel MOS transistor.

Both n-channel MOS transistors are always on. This means that the CMOS inverter always causes a through current to flow, resulting in an increase in current consumption. Also M
The operating margin becomes low with respect to fluctuations in the threshold voltage of the OS transistor, which may cause malfunction.

The above situation is not limited to the B1CMOS inverter, but also applies to various B1CMOS buffers to which this is applied.

(Problems to be Solved by the Invention) As described above, in the conventional B1CMOS circuit, the current consumption increases due to the amplitude limit caused by the built-in voltage between the base and emitter of the bipolar transistor that constitutes the output circuit, and the operating margin There was a problem that the

The present invention has solved these problems. The purpose is to provide a B1CMOS circuit.

[Structure of the Invention] (Means for Solving the Problems) A BiCMO8 circuit according to the present invention includes a CMOS gate, a first bipolar transistor controlled by the output of the CMOS gate, and a second bipolar transistor connected in series with the CMOS gate. an output circuit consisting of a bipolar transistor; an on-drive MOS transistor that is controlled by an input signal of a CMOS gate to turn on the second bipolar transistor by shorting the collector and base of the second bipolar transistor; and a CMOS transistor.
an off-drive MOS that turns off the second bipolar transistor by discharging the base charge of the second bipolar transistor under control of the output potential of the gate;
In addition to the basic configuration including a transistor, a resistive element is connected between the base and emitter of the first bipolar transistor.

(Function) As mentioned above, the base of the first bipolar transistor
If a resistor element is inserted between the emitters, when the output of the CMOS gate becomes "H" level, the output terminal of the output circuit is raised to VCC-φ8E by the first bipolar transistor, and then further charged through the resistor element. The voltage rises completely to the power supply potential Vcc (for example, 5V). Also CM
When the output of the OS gate goes to "L" level, the first bipolar transistor turns off, the second bipolar transistor turns on, and the output terminal drops to φBE.
After that, the resistor element and CMOS gate are turned on.
It completely drops to the ground potential VSS (for example, OV) through the channel MOS transistor. Therefore, B of the present invention
In the iCMO3 circuit, a full amplitude output is obtained, and when these are connected in cascade, a through current will not flow from the second stage onwards and the current consumption will not increase. In addition, even if there is a slight fluctuation in the threshold voltage of the MOS transistor, it will not malfunction.
A high operating margin can be obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 shows an embodiment of a B1 CMOS inverter.

Components corresponding to those in the conventional example in FIG. 6 are designated by the same reference numerals as in FIG. 6, and detailed description thereof will be omitted.

P channel MOS transistor M1 and n channel MOS
A CMOS inverter 1 made up of a transistor M2, an output circuit 2 made up of a first npn bipolar transistor Ql and a second npn bipolar transistor Q2 connected in a totem ball connection, and a diode-connected second bipolar transistor Q2 turned on and driven. The basic configuration remains the same as before, consisting of an n-channel MOS transistor M3 for on-drive and an OFF-drive MOS transistor M4 that discharges the base accumulated charge of the second bipolar transistor Q2 to turn off the second bipolar transistor Q2. . In this embodiment with such a basic configuration, a resistance element R is connected between nodes A and B, that is, between the base and emitter of the first bipolar transistor Ql forming the output circuit 2. This circuit is typically integrated with other circuits on a single semiconductor substrate.

FIGS. 2(a) to 2(d) show specific configuration examples of the resistance element R in FIG. 1. Resistance element R has node A connected to VC
When it becomes C, node B becomes V. It can be raised to 0, and when node A becomes VsS, node B becomes VSS.
It is necessary to be able to reduce the (a) is a diffusion layer resistance using an impurity diffusion layer or a polycrystalline silicon film resistance, which satisfies the above conditions.

(b) is a D-type n-channel MOS transistor whose gate and drain are commonly connected, and (c) is a D-type n-channel MOS transistor whose gate and drain are commonly connected.
The gates and sources of P-channel MOS transistors are commonly connected, and since both are D-type, the above conditions are satisfied. (d) is the VC at the gate.
E-type, n-channel MOS transistor with C applied, and E-type, p-channel MOS transistor with VSS applied to the gate.
An OS transistor is connected in parallel.

When node A is at VCC, node B can rise up to VCC through the p-channel MOS transistor, and when node A is at VSS, node B can go down to VSS through the n-channel MOS transistor. In other words, although this configuration uses E type for both the p-channel and n-channel, by connecting them in parallel, it is not affected by the threshold voltage, and the change in the potential of node B corresponds to the change in potential of node A. can be completely followed.

FIG. 3 shows operating waveforms of the B1CMOS inverter of this embodiment. Human power signal Vin is “L° level (-0V)
When , CMOS inverter 1 is off and node A
is Vcc= through p-channel MOS transistor M1.
charged to 5V, the first bipolar transistor Q1
is turned on.

At this time, the off-drive MOS transistor M3 is turned on and extracts the base accumulated charge of the second bipolar transistor Q2, so the second bipolar transistor Q2 is turned off. Therefore, the output terminal is charged by the current flowing through the first bipolar transistor Ql, the p-channel MOS transistor M of the CMOS inverter 1, and the current flowing through the resistance element R. The bipolar transistor has a high load driving capability (for example, two orders of magnitude higher than that of the resistor R), and is therefore charged up to VCC-φBE mainly by the first bipolar transistor Ql. When the output signal Vout rises to this level, the first bipolar transistor Q1 is turned off, but after that, it continues to be charged by the current flowing through the p-channel MoS transistor M1 and the resistive element R, and finally V c c
= 5V "H" level output is obtained.

Next, when the input signal V1n of the CMOS inverter 1 becomes "H" level = Vcc), the output of the CMOS inverter 1 is inverted and the node A becomes "L" level.At this time, the on-drive MOS transistor M3 As a result, the base accumulated charge of the first bipolar transistor Qr is extracted through the n-channel MoS transistor M2 of the CMOS inverter 1, and the first bipolar transistor Qr is turned off.

- The bipolar transistor Q2 of the power cylinder 2 is turned on by the current flowing from the output terminal into its base through the on-drive MOS transistor M3. At this time, the output terminal is
It is discharged by the IE flowing from the collector to the emitter of the second bipolar transistor Q2, and the current flowing through the resistive element R and the n-channel MoS transistor M2 of the CMO inverter 1. For the same reason as for charging,
The second bipolar transistor Q of the two discharge currents
Since the current flowing through Q2 is larger, it is mainly dominated by the discharge from the second bipolar transistor Q2 and becomes "L".
become the level. When the “L” level potential reaches φBE, the second
The bipolar transistor Q2 is turned off, but the discharge current continues to flow through the resistor R and the MOS transistor M2, and the output "L" level potential finally drops to OV.

In this way, in the B1CMOS inverter of this embodiment, “
A full-amplitude output can be obtained at the "H" level up to the power supply potential VCC and at the "L" level up to the ground potential VSS. Therefore, according to this embodiment, there is no needless current consumption as in the conventional case, and BiCM that is strong against threshold fluctuations
An O8 circuit is obtained. Furthermore, since the only circuit element added to the conventional circuit is a resistor element, the characteristics can be greatly improved without complicating the circuit configuration.

FIG. 4 shows B i 0MO3·N of another embodiment of the present invention.
It is an AND gate. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. C in Figure 1
In this embodiment, the part of the M O inverter 1 consists of p-channel MoS transistors M, , , M, 2 and a lo-channel P
It is a two-manpower 0MO3-NAND gate 3 constructed using v10S transistors N1□ and 6M2□. In addition, in response to the fact that the CMOS gate section is powered by two people, two human power signals Vin are used as the MOS transistor for turning on the second bipolar transistor Q2.
Two MOS transistors M31 and M32 connected in series are provided, which are controlled by l and Vin2, respectively.

The operation of this B i 0 MO3-NAND gate is basically the same as that of the B1 CMOS inverter of the previous embodiment.

When the two inputs Vlnl and Vln2 are low (both are at "L" level), node A is charged to VCC,
The first bipolar transistor Q+ is turned on. Further, the off-drive MOS transistor M1,1 is turned on.

As in the previous embodiment, CMO3ΦNAND gate 3
The output terminal is completely connected to VCC through either p-channel MOS transistor MIH or Ml2 and the resistor R.
will be charged up to. Two input signals Vlnl, Vin
2 are both at the "H" level, the node A becomes the "L° level, and the first bipolar transistor Q1 is turned off. At this time, the two on-drive MOS transistors M3
1 and Ml 2 are both turned on, and the second bipolar transistor Q2 is turned on. And as in the previous embodiment, the output terminals are the resistor wire R and 0MO3-N.
MOS transistors M21 and M2□ of AND gate 3
As a result, an "L" level output up to Ov can be obtained. Therefore, this embodiment also provides a circuit with low current consumption and high operating margin.

FIG. 5 shows a BtCMOS/NOR according to another embodiment of the present invention.
It is a gate. Portions corresponding to those in FIG. 4 are designated by the same reference numerals as in FIG. 4, and detailed description thereof will be omitted.

In this embodiment, the portion corresponding to the CMOS-NAND gate 3 in FIG. 4 includes p-channel MOS transistors M11 and Ml2 connected in series, and an n-channel MOS transistor M3 connected in parallel.

It constitutes a CMOS-NOR gate 4 made of M32. Corresponding to this change, the on-drive MOS transistor receives two input signals Vinl.

Two n-channels M each controlled by VIn2
OS transistors M31 and M32 are prepared.

In this embodiment, as in the previous embodiment, the 'Hm level of the output signal changes to VCC, and the 'L'' level changes to VSS, allowing stable operation with low current consumption.

The present invention can also be applied to B i CMOS gates that are generally expanded to N inputs, not limited to two-manpower operations.

[Effects of the Invention] As described above, according to the present invention, a full amplitude output can be obtained by adding only a few circuit elements, there is no increase in current consumption due to through current, and a high operating margin can be obtained. A BiCMO3 circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a B1CMOS inverter according to an embodiment of the present invention, FIGS. 2(a) to (d) are diagrams showing examples of resistance elements used in the embodiment, and FIG. 3 is a diagram showing its operating waveform. figure,
FIG. 4 is a diagram showing a BicMOS-NAND gate of another embodiment, and FIG. 5 is a diagram showing a B1CMOS-NAND gate of still another embodiment.
FIG. 6 is a diagram showing an OR gate, FIG. 6 is a diagram showing a conventional B1 CMOS inverter, and FIG. 7 is a diagram showing its operating waveform. 1...CMOS inverter, 2...output circuit, 3...
・・CMOS-NAND gate, 4...CMOS ・
NOR gate, Ql...first bipolar transistor, Q2...second bipolar transistor, M3
, M31, M32... MOS transistor for on drive, M4, M4 l, M42... M for off drive
OS transistor. Applicant's agent Patent attorney Takehiko Suzue V 113 Figure Figure Figure Figure Figure Special Kansai

Claims (3)

[Claims] (1) An output circuit consisting of a CMOS inverter, a first bipolar transistor on the power supply side controlled by the output terminal potential of the CMOS inverter, and a second bipolar transistor on the ground side connected in series thereto; an on-drive MOS transistor for shorting the collector and base of the second bipolar transistor to turn on the second bipolar transistor under the control of the input terminal potential of the CM;
an off-drive MOS transistor for discharging the base charge of the second bipolar transistor to turn off the second bipolar transistor under the control of the output terminal potential of the OS inverter; 1. A transistor circuit comprising: a resistive element connected between emitters. (2) an output circuit consisting of a CMOS NAND gate, a first bipolar transistor on the power supply side controlled by the output terminal potential of the NAND gate, and a second bipolar transistor on the ground side connected in series thereto; a plurality of series-connected on-drive MOS transistors each controlled by a plurality of input terminal potentials of the NAND gate to short-circuit the collector and base of the second bipolar transistor to turn on the second bipolar transistor; and an off-drive M for discharging the base charge of the second bipolar transistor to turn off the second bipolar transistor under the control of the output terminal potential of the NAND gate.
A transistor circuit comprising an OS transistor and a resistance element connected between the base and emitter of the first bipolar transistor. (3) an output circuit consisting of a CMOS NOR gate, a first bipolar transistor on the power supply side controlled by the output terminal potential of the NOR gate, and a second bipolar transistor on the ground side connected in series therewith; The collector voltage of the second bipolar transistor is controlled by the plurality of input terminal potentials of the NOR gate.
Multiple on-drive MOs connected in parallel to short-circuit the bases and turn on the second bipolar transistor
an off-drive MOS transistor for discharging the base charge of the second bipolar transistor to turn off the second bipolar transistor under the control of the output terminal potential of the NOR gate;
and a resistance element connected between the base and emitter of the first bipolar transistor.