WO2009113372A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

Info

Publication number
WO2009113372A1
WO2009113372A1 PCT/JP2009/052923 JP2009052923W WO2009113372A1 WO 2009113372 A1 WO2009113372 A1 WO 2009113372A1 JP 2009052923 W JP2009052923 W JP 2009052923W WO 2009113372 A1 WO2009113372 A1 WO 2009113372A1
Authority
WO
WIPO (PCT)
Prior art keywords
coil
signal transmission
coils
chip
semiconductor device
Prior art date
Application number
PCT/JP2009/052923
Other languages
English (en)
Japanese (ja)
Inventor
宏一朗 野口
義男 亀田
源洋 中川
水野　正之
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to US12/920,452 priority Critical patent/US20110006443A1/en
Priority to JP2010502750A priority patent/JPWO2009113372A1/ja
Publication of WO2009113372A1 publication Critical patent/WO2009113372A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

Definitions

  • the present invention relates to a semiconductor device for transmitting a signal.
  • non-contact signal transmission is performed by flowing a current with data superimposed on a transmission coil formed on a silicon substrate and detecting power induced on the receiving side by an electromagnetic coupling phenomenon.
  • one or more coils whose coil surfaces are substantially parallel to the surface of the LSI chip are arranged inside the LSI, and a plurality of stacked chips are in a direction substantially perpendicular to the chip surface.
  • Non-contact signal transmission is implemented.
  • the first problem is that when a signal is transmitted in a direction substantially parallel to the chip surface using a coil, the coil area required for communication is small in the coil in which the coil surface is arranged substantially parallel to the chip surface. It will be bigger. This is because, since the direction of the magnetic flux generated by the coil is substantially perpendicular to the coil surface, in the configuration in which the coil surface is arranged substantially parallel to the chip surface, the direction of the generated magnetic flux is the communication direction. Will be orthogonal. For this reason, the generated magnetic flux cannot be effectively used.
  • the second problem is that the signal transmission coil may affect the coil arranged inside the chip for other purposes and may deteriorate the performance of the entire chip.
  • various circuits are integrated in the chip.
  • a transmission circuit, an antenna circuit for RF communication, and the like use a highly accurate coil whose parameters are finely adjusted as a part of the circuit. Therefore, the magnetic flux generated by the signal transmission coil for signal transmission leaks into these high-precision coils and changes the characteristics of the coil.
  • the circuit performance is deteriorated, and as a result, there is a possibility that the margin of the entire chip is deteriorated and the operation is deteriorated.
  • An object of the present invention is to provide a semiconductor device that solves the above-described problems.
  • the present invention provides: In a semiconductor device composed of a plurality of semiconductor integrated circuits and a plurality of coils, The plurality of coils are arranged such that the coil surfaces of the plurality of coils are substantially perpendicular to the chip surface of the semiconductor integrated circuit on which the metal film is laminated in the manufacturing process of the semiconductor device, A signal is transmitted between a pair of adjacent coils.
  • the present invention in a semiconductor device composed of a plurality of semiconductor integrated circuits and a plurality of coils, with respect to the chip surface of the semiconductor integrated circuit in which the metal film is laminated in the manufacturing process of the semiconductor device. Since the plurality of coils are arranged so that the coil surfaces of the plurality of coils are substantially perpendicular to each other, and a signal is transmitted between a pair of adjacent coils among the plurality of coils, the coil area is reduced and the inside of the chip is reduced. It is possible to reduce the influence on other coils arranged in the.
  • FIG. 5 is a diagram illustrating operation waveforms of signals in the circuit illustrated in FIG. 4. It is a figure which shows the other example of coil manufacture. It is a figure which shows the 2nd Embodiment of this invention. It is a figure which shows the 3rd Embodiment of this invention. It is a figure which shows the 4th Embodiment of this invention.
  • FIG. 1 is a diagram showing a first embodiment of the present invention.
  • this embodiment is composed of two LSI chips 11a and 11b arranged adjacent to each other, and they are arranged close to each other so that the chip side surfaces 14a and 14b face each other.
  • Signal transmission coils 12a and 12b are arranged on the LSI chips 11a and 11b that perform signal transmission, respectively.
  • the signal transmission coils 12a and 12b are arranged so that their coil surfaces are substantially perpendicular to the chip surfaces 13a and 13b, respectively.
  • the area of the coil surface of the signal transmission coil 12a may be equal to the area of the coil surface of the signal transmission coil 12b.
  • the signal transmission coils 12a and 12b arranged according to this embodiment can generate magnetic fluxes in directions substantially parallel to the chip surfaces 13a and 13b, respectively. Therefore, in signal transmission in directions substantially parallel to the chip surfaces 13a and 13b, the coupling between the coils is stronger than the coil arrangement described in the background art, and the coil area is smaller than the coil arrangement described in the background art. With a small coil, non-contact signal transmission can be achieved between the LSI chips 11a and 11b arranged adjacent to each other.
  • substantially perpendicular is not a plane that is completely perpendicular (90 degrees) to a certain plane, but may have a certain degree of inclination according to manufacturing variations and communication directions.
  • substantially horizontal and substantially parallel are not completely parallel to a certain surface (does not intersect even if the surface is expanded infinitely), and may have a certain degree of inclination depending on manufacturing variations and communication directions. good.
  • the chip surface refers to a surface substantially perpendicular to the cross-section when the chip is diced from the wafer, or a surface substantially parallel to the surface on which a metal film or the like is laminated in the manufacturing process.
  • the coil surface is a loop surface of coil wiring installed in a circular or polygonal shape.
  • the coil arrangement described in the background art is a coil arranged such that the coil surface is substantially parallel to the chip surface.
  • the signal transmission coils 12a and 12b respectively disposed inside the LSI chips 11a and 11b perform signal transmission using an electromagnetic coupling phenomenon.
  • the transmission coil transmits a signal by flowing a current on which data is superimposed.
  • the other receiving coil detects the potential induced in the coil due to the electromagnetic coupling phenomenon and restores the signal. In this way, signal transmission is realized by inducing a potential from the transmission side to the reception side.
  • FIG. 2 is a diagram showing a form in which a signal transmission coil is arranged inside the LSI chip.
  • FIG. 3 is a view showing an example of manufacturing a coil formed inside the semiconductor device.
  • the coil formed in the semiconductor device in this example was formed by a normal semiconductor device manufacturing process using one to five metal wiring layers (M1 to M5).
  • the signal transmission coils 12a and 12b shown in FIG. 2 are designed to have a diameter of several tens of micrometers, and are formed at the ends of the LSI chips 11a and 11b so that the coil surfaces are substantially perpendicular to the chip surfaces 13a and 13b, respectively. did.
  • the LSI chips 11a and 11b that perform signal transmission are arranged adjacent to each other so that the distance between the coils is about twice the coil diameter.
  • the coil may be external.
  • FIG. 4 is a circuit diagram inside the LSI chips 11a and 11b for transmitting and receiving signals.
  • a transmission control circuit 20 is connected to the transmission coil 21, and a signal is transmitted by passing a current through the transmission coil 21 based on a transmission clock (TXck) and a transmission data (TXdata) signal. Generated magnetic flux. Signal transmission can be performed by this magnetic flux.
  • TXck transmission clock
  • TXdata transmission data
  • a latch comparator 22 is connected to both ends of the receiving coil 23 to detect a voltage (Vrx) induced in the receiving coil 23.
  • Signal detection can be realized by converting the detected voltage into a digital signal (RXdata) at the timing of the reception clock (RXck).
  • RXdata digital signal
  • resistors 24 were inserted at both ends of the receiving coil 23 so that a voltage was induced in the receiving coil 23, and the intermediate potential was fixed.
  • the transmission coil 21 shown in FIG. 4 corresponds to one of the signal transmission coils 12a and 12b shown in FIG. 1 or FIG. 2, and the reception coil 23 shown in FIG. This corresponds to the one not corresponding to the transmission coil 21 of the signal transmission coils 12a, 12b shown in FIG.
  • FIG. 5 is a diagram showing operation waveforms of signals in the circuit shown in FIG.
  • transmission / reception of data “1” is realized at A timing
  • transmission / reception of “0” is realized at B timing.
  • the transmission coil 21 transmits the value of TXdata when TXck rises.
  • a positive current (Itx) is sent to the transmitting coil 21 when a data “0” is transmitted, thereby generating magnetic fluxes with different polarities depending on the transmission data. went.
  • Vrx Since a voltage in the form of differentiating the transmission current waveform is induced on the reception side (Vrx), Vrx is amplified at the rise timing of RXck using the latch comparator 22, and then converted into a digital value, and the transmission data is received data (RXdata). Realized restoration as.
  • FIG. 6 is a diagram showing another example of coil manufacturing.
  • the shape shown in FIG. 6 can also be manufactured by a normal manufacturing process.
  • the signal transmission coil 12a shown in FIG. 6 has a spiral shape and is characterized in that the number of turns in the depth direction is larger than that of the coil arrangement described in the background art. This is because the number of turns in the depth direction of the coil arrangement described in the background art is limited by the number of wiring layers, whereas the arrangement of the signal transmission coil 12a shown in FIG. The number of coils can be formed. Since the number of turns of the signal transmission coil 12a is proportional to the strength of the magnetic flux generated by the coil, increasing the number of turns generates a magnetic flux stronger than the coil having the coil arrangement described in the background art, and a long distance signal. Transmission can be realized. (Second Embodiment)
  • FIG. 7 is a diagram showing a second embodiment of the present invention.
  • the present embodiment is composed of an LSI chip 41a, a signal transmission coil 42b, and an external device 45.
  • the LSI chip 41a has a signal transmission coil 42a in the direction in which the coil surface is substantially perpendicular to the chip surface 43a (the direction in which the coil surface is substantially parallel to the chip side surface 44a). 42a was connected to the circuit shown in FIG. 4 inside the chip.
  • the signal transmission coil 42b installed outside the chip is arranged so that the coil surface thereof is substantially parallel to the coil surface of the signal transmission coil 42a.
  • the signal transmission coil 42b installed outside the chip was connected to an external device 45 for signal transmission control.
  • a feature of this embodiment is that a signal transmission coil 42b that is substantially parallel to the signal transmission coil 42a that is disposed substantially perpendicular to the chip surface 43a is disposed outside the chip.
  • this embodiment can realize non-contact signal transmission between the LSI chip 41a and the external device 45. This can be applied to various uses, for example, when inputting a signal from an external signal generator to the chip, or outputting an operation result of the chip to an external measuring instrument.
  • FIG. 8 is a diagram showing a third embodiment of the present invention.
  • the present embodiment is composed of an LSI chip 51 and a signal transmission coil 52b.
  • the LSI chip 51 has a coil 56 for a purpose other than signal transmission in which the coil surface is disposed substantially perpendicular to the chip side surface 54 and a signal transmission coil 52 a in which the coil surface is disposed substantially perpendicular to the chip surface 53.
  • the signal transmission coil 52a is disposed so that the coil surface thereof is substantially perpendicular to the coil surface of the coil 56 used for purposes other than signal transmission.
  • the coil generates a magnetic flux in a direction substantially perpendicular to the coil surface.
  • the signal transmission coil is arranged so that the direction 55 of the magnetic flux generated by the signal transmission coil 52a and the direction 55 of the magnetic flux generated by the coil 56 for purposes other than the signal transmission are orthogonal.
  • the signal transmission coils 52a and 52b perform signal transmission using the electromagnetic coupling phenomenon, but the magnetic flux generated by the signal transmission coil 52a during data transmission / reception leaks into the coil 56 for purposes other than signal transmission due to the coil arrangement of this embodiment. You can avoid it. Thereby, the potential induced as noise in the coil 56 for uses other than signal transmission can be reduced, and the influence on other functions can be reduced. This is because, for example, when the coil of this embodiment is used for an RF chip, it is possible to suppress interference of the RF signal to the receiving antenna and the transmission circuit for frequency conversion due to magnetic flux leakage, so that high chip performance is maintained. It becomes possible to do.
  • (Fourth embodiment) 9a and 9b are diagrams showing a fourth embodiment of the present invention.
  • This embodiment is composed of LSI chips 61a and 61b as shown in FIGS. 9a and 9b.
  • each LSI chip 61a, 61b has a coil surface substantially perpendicular to the chip surfaces 63a, 63b (coil surfaces with respect to the chip side surfaces 64a, 64b).
  • the signal transmission coils 62a and 62b are arranged respectively so that they are substantially parallel to each other.
  • the signal transmission coils 62a and 62b shown in FIGS. 9a and 9b are arranged with the center axes of the coils being shifted.
  • FIG. 9a shows a form in which the coil arrangement position is changed in the LSI chips 61a and 61b and the coil central axis is shifted.
  • FIG. 9B shows a form in which the coil arrangement positions in the LSI chips 61a and 61b are the same, but the arrangement relationship of the LSI chips 61a and 61b is changed and the central axis of the coil is shifted.
  • the central axes of a pair of coils that perform signal transmission may coincide with each other, but the central axes of the coils are slightly shifted as in this embodiment. May be.
  • this embodiment differs in the central axis of a pair of coils that perform signal transmission, the angle from the signal transmission is small, and signal transmission can be realized by the above method.
  • the wafer 85 before dicing is in the state of a large number of LSI chips 81.
  • Each LSI chip 81 is internally provided with a signal transmission coil 82 such that the coil surface is substantially perpendicular to the chip surface 83, and the LSI chips 81 are adjacent to each other via a scribe line (dicing line) 84. It is arranged.
  • the signal transmission coils 82 arranged in the respective LSI chips 81 perform signal transmission using an electromagnetic coupling phenomenon.
  • FIG. 10 a shows an example of signal transmission between LSI chips 81 via a plurality of signal transmission coils 82 via a scribe line 84.
  • FIG. 10B illustrates an LSI in which a signal is transmitted between LSI chips 81 via an auxiliary coil on the scribe line 84, and a signal line 86 and a signal transmission coil 82 formed on the scribe line 84.
  • a mode in which signals are transmitted to and received from the chip 81 is shown.
  • this form since this form enables signal transmission, chip inspection or the like in a wafer state can be realized.
  • 11a, 11b, and 11c are views showing a sixth embodiment of the present invention.
  • the present embodiment includes a configuration of a multichip module 76 that includes a plurality of LSI chips 71 on a connection substrate 75.
  • a signal transmission coil 72 is arranged inside the LSI chip 71 constituting the multichip module 76.
  • the signal transmission coil 72 is arranged so that the coil surface is substantially perpendicular to the chip surface 73 (so as to be substantially parallel to the chip surface 74).
  • FIG. 11 a shows a form in which LSI chips 71 are arranged adjacent to each other inside the multichip module 76.
  • FIG. 11 b shows an embodiment in which signal transmission is performed in a direction substantially parallel to the chip surface 73 between the different multichip modules 76.
  • FIG. 11 c also shows an LSI chip 71 having a signal transmission coil 72 disposed substantially perpendicular to the chip surface 73 and a signal transmission coil 72 disposed substantially parallel to the chip surface 73.
  • the multi-chip module 76 in which the LSI chip is arranged so that the signal transmission coils 72 are substantially parallel to each other is shown.
  • the signal transmission coils 72 perform signal transmission using the electromagnetic coupling phenomenon.
  • the multi-chip module 76 bonding wires and surface mounting technology are used for inter-chip signal communication. In either technology, it is necessary to take out a signal from a direction substantially perpendicular to the chip surface. There are mounting restrictions such as being unable to stack layers. In this embodiment, since non-contact signal transmission is possible in a direction substantially parallel to the chip surface, it is possible to provide a mounting method with a high degree of freedom as shown in FIGS. 11a, 11b, and 11c.
  • the present invention has the following effects.
  • the first effect is that the coil area can be reduced as compared with the coil arrangement that generates magnetic flux in a direction substantially perpendicular to the chip surface. This is because, when performing signal transmission in a direction substantially parallel to the chip surface, the coil arranged by the inventive method generates a magnetic flux in a direction substantially parallel to the chip surface.
  • the second effect is to reduce the leakage of magnetic flux into a high-precision coil with finely adjusted parameters used for applications other than inter-chip signal transmission, and to reduce the performance of transmitter circuits and antenna circuits for RF communications. It can be avoided. This is because the direction of the magnetic flux generated by the coil arranged according to the inventive method is orthogonal to the direction of the magnetic field generated by the coil inside the chip used for purposes other than inter-chip signal transmission.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

L'invention porte sur un dispositif à semi-conducteur composé d'une pluralité de circuits intégrés à semi-conducteur et d'une pluralité de bobines. Durant le processus de fabrication du dispositif à semi-conducteur, les multiples bobines sont agencées de telle manière que les surfaces de bobine sont généralement perpendiculaires à la surface avant d'une puce des circuits intégrés à semi-conducteur dans laquelle des films métalliques sont stratifiés. Un signal est transmis entre une paire de bobines adjacentes parmi la pluralité de bobines.
PCT/JP2009/052923 2008-03-13 2009-02-19 Dispositif à semi-conducteur WO2009113372A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/920,452 US20110006443A1 (en) 2008-03-13 2009-02-19 Semiconductor device
JP2010502750A JPWO2009113372A1 (ja) 2008-03-13 2009-02-19 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008064164 2008-03-13
JP2008-064164 2008-03-13

Publications (1)

Publication Number Publication Date
WO2009113372A1 true WO2009113372A1 (fr) 2009-09-17

Family

ID=41065044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/052923 WO2009113372A1 (fr) 2008-03-13 2009-02-19 Dispositif à semi-conducteur

Country Status (3)

Country Link
US (1) US20110006443A1 (fr)
JP (1) JPWO2009113372A1 (fr)
WO (1) WO2009113372A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012054535A (ja) * 2010-08-06 2012-03-15 Renesas Electronics Corp 半導体装置、電子装置、及び半導体装置の製造方法
JP2016015521A (ja) * 2010-08-06 2016-01-28 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法
WO2017010009A1 (fr) * 2015-07-16 2017-01-19 ウルトラメモリ株式会社 Élément semi-conducteur
WO2017010010A1 (fr) * 2015-07-16 2017-01-19 ウルトラメモリ株式会社 Élément à semi-conducteur
US9847305B2 (en) 2015-09-30 2017-12-19 Keio University Semiconductor chip with multilayer solenoid coil and multi-chip module comprising the same
WO2022085194A1 (fr) * 2020-10-23 2022-04-28 ウルトラメモリ株式会社 Dispositif de communication

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8525294B2 (en) * 2008-09-18 2013-09-03 Renesas Electronics Corporation Semiconductor device
JP2012023254A (ja) * 2010-07-16 2012-02-02 Toshiba Corp 半導体装置
ITVI20120145A1 (it) 2012-06-15 2013-12-16 St Microelectronics Srl Struttura comprensiva di involucro comprendente connessioni laterali
US10483343B2 (en) * 2017-06-16 2019-11-19 Huawei Technologies Co., Ltd. Inductors for chip to chip near field communication
US11854967B2 (en) * 2019-08-29 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066769A (ja) * 2004-08-30 2006-03-09 Tokyo Institute Of Technology インダクタ及びその製造方法
JP2006165287A (ja) * 2004-12-08 2006-06-22 Seiko Epson Corp 電子デバイス、パッケージ型電気回路装置、及び電子デバイスの製造方法
JP2006325031A (ja) * 2005-05-19 2006-11-30 Hiroshima Univ 信号伝達装置および信号伝達方法
JP2007165459A (ja) * 2005-12-12 2007-06-28 Mitsubishi Electric Corp マルチチップモジュール
JP2007295213A (ja) * 2006-04-25 2007-11-08 Takion Co Ltd 集積回路装置及び送信装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002261561A (ja) * 2001-02-27 2002-09-13 Matsushita Electric Ind Co Ltd フィルタ部品
PT103299B (pt) * 2005-06-29 2007-04-30 Univ Do Minho Microantena integrada sintonizável com dimensões eléctricas reduzidas e seu método de fabrico
JP5229213B2 (ja) * 2007-02-23 2013-07-03 日本電気株式会社 インダクタ結合を用いて信号伝送を行う半導体装置
JPWO2009113373A1 (ja) * 2008-03-13 2011-07-21 日本電気株式会社 半導体装置
US7760144B2 (en) * 2008-08-04 2010-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas integrated in semiconductor chips
EP2315364B1 (fr) * 2009-10-21 2016-12-07 STMicroelectronics Srl Transmission de signal par circuits résonants LC

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066769A (ja) * 2004-08-30 2006-03-09 Tokyo Institute Of Technology インダクタ及びその製造方法
JP2006165287A (ja) * 2004-12-08 2006-06-22 Seiko Epson Corp 電子デバイス、パッケージ型電気回路装置、及び電子デバイスの製造方法
JP2006325031A (ja) * 2005-05-19 2006-11-30 Hiroshima Univ 信号伝達装置および信号伝達方法
JP2007165459A (ja) * 2005-12-12 2007-06-28 Mitsubishi Electric Corp マルチチップモジュール
JP2007295213A (ja) * 2006-04-25 2007-11-08 Takion Co Ltd 集積回路装置及び送信装置

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10249565B2 (en) 2010-08-06 2019-04-02 Renesas Electronics Corporation Semiconductor device that transfers an electric signal with a set of inductors
JP2016015521A (ja) * 2010-08-06 2016-01-28 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法
US9461103B2 (en) 2010-08-06 2016-10-04 Renesas Electronics Corporation Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device
JP2018026577A (ja) * 2010-08-06 2018-02-15 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法
JP2012054535A (ja) * 2010-08-06 2012-03-15 Renesas Electronics Corp 半導体装置、電子装置、及び半導体装置の製造方法
WO2017010009A1 (fr) * 2015-07-16 2017-01-19 ウルトラメモリ株式会社 Élément semi-conducteur
WO2017010010A1 (fr) * 2015-07-16 2017-01-19 ウルトラメモリ株式会社 Élément à semi-conducteur
JPWO2017010009A1 (ja) * 2015-07-16 2018-02-22 ウルトラメモリ株式会社 半導体素子
JPWO2017010010A1 (ja) * 2015-07-16 2018-03-01 ウルトラメモリ株式会社 半導体素子
US10269734B2 (en) 2015-07-16 2019-04-23 Ultramemory Inc. Semiconductor element
US9847305B2 (en) 2015-09-30 2017-12-19 Keio University Semiconductor chip with multilayer solenoid coil and multi-chip module comprising the same
WO2022085194A1 (fr) * 2020-10-23 2022-04-28 ウルトラメモリ株式会社 Dispositif de communication
JP7493267B2 (ja) 2020-10-23 2024-05-31 ウルトラメモリ株式会社 通信装置

Also Published As

Publication number Publication date
JPWO2009113372A1 (ja) 2011-07-21
US20110006443A1 (en) 2011-01-13

Similar Documents

Publication Publication Date Title
WO2009113372A1 (fr) Dispositif à semi-conducteur
US7768790B2 (en) Electronic circuit
EP1388988A2 (fr) Bobine à l'échelle d'une puce et isolateur basé sur ceux-ci
JP5366932B2 (ja) 超高速信号送受信
JP4784773B2 (ja) 伝送方法、インターフェース回路、半導体装置、半導体パッケージ、半導体モジュールおよびメモリモジュール
US8648614B2 (en) Electronic circuit testing apparatus
US9053950B2 (en) Electronic circuit
EP2302850A1 (fr) Isolateurs de signal utilisant des micro-transformateurs
US20120319912A1 (en) Communication device and semiconductor chip
US11437350B2 (en) Semiconductor device
JP2010212682A (ja) コイルトランスデューサにおける電磁干渉の最小化
CN104022113A (zh) 一种基于微型变压器的堆叠式数字隔离器
JP2005203657A (ja) 半導体装置
JP2007165459A (ja) マルチチップモジュール
JP7455424B2 (ja) 情報処理装置
CN101452932A (zh) 半导体装置、其制造方法以及使用该半导体装置的信号发送/接收方法
JPWO2008102814A1 (ja) インダクタ結合を用いて信号伝送を行う半導体装置
JP2017069456A (ja) 半導体チップ及びマルチチップモジュール
JP6686048B2 (ja) 半導体装置
US10269734B2 (en) Semiconductor element
WO2007145086A1 (fr) Dispositif à semiconducteur, émetteur de signal et méthode de transmission de signal
Kadomoto et al. Wixi: An inter-chip wireless bus interface for shape-changeable chiplet-based computers
JP2011041066A (ja) 磁気結合方式を用いた信号伝達装置
US20120012842A1 (en) Semiconductor device having function of transmitting/receiving
JP7278016B2 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09718575

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12920452

Country of ref document: US

Ref document number: 2010502750

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09718575

Country of ref document: EP

Kind code of ref document: A1