WO2009092424A2 - Structure semi-conductrice et procédé de production d'une structure semi-conductrice - Google Patents

Structure semi-conductrice et procédé de production d'une structure semi-conductrice Download PDF

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Publication number
WO2009092424A2
WO2009092424A2 PCT/EP2008/010639 EP2008010639W WO2009092424A2 WO 2009092424 A2 WO2009092424 A2 WO 2009092424A2 EP 2008010639 W EP2008010639 W EP 2008010639W WO 2009092424 A2 WO2009092424 A2 WO 2009092424A2
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WO
WIPO (PCT)
Prior art keywords
emitter
region
passivation
semiconductor structure
metallization
Prior art date
Application number
PCT/EP2008/010639
Other languages
German (de)
English (en)
Other versions
WO2009092424A3 (fr
Inventor
Oliver Schultz
Jan Benick
Martin Hermle
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Albert-Ludwigs-Universität Freiburg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V., Albert-Ludwigs-Universität Freiburg filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority to EP08871574A priority Critical patent/EP2235758A2/fr
Publication of WO2009092424A2 publication Critical patent/WO2009092424A2/fr
Publication of WO2009092424A3 publication Critical patent/WO2009092424A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a semiconductor structure according to the preamble of claim 1 and to a method for producing a semiconductor structure according to the preamble of claim 14.
  • the present invention relates to a semiconductor structure in which the
  • Semiconductor substrate having an n-doped base region and an at least partially adjacent p-doped emitter region for forming an emitter / base pn junction.
  • the emitter region extends at least partially approximately parallel to a surface of the semiconductor substrate, which is referred to below as "emitter surface”.
  • the semiconductor structure further comprises an n-type metallization and a p-type metallization, wherein the n-type metallization is electrically conductively connected to the base region and the p-type metallization is connected to the emitter region.
  • Charge carriers can thus be removed from the base region via the n-type metallization and from the emitter region via the p-type metallization or fed to the electronic component.
  • the emitter and base are not electrically conductively connected via the pn junction, and accordingly, the n-type metallization is not electrically connected to the emitter region and the p-type metallization is not electrically conductively connected to the base region.
  • semiconductor structures are fabricated such that a silicon wafer is used as the semiconductor substrate, with the silicon wafer already having a fundamental doping, in the case of the present invention an n-type fundamental doping.
  • an emitter region is generated, for example, by means of diffusion of foreign atoms, so that a pn junction is formed between the p-doped emitter and the n-doped base.
  • the electrical passivation of the surface on which the emitter is arranged is of very great importance for a high quality of the component. Electrical passivation here means that the lowest possible recombination rate should be achieved in the region of the surface to be passivated.
  • the invention is therefore based on the object to provide a semiconductor structure and a method for their preparation, so that a good passivation of the emitter surface is achieved, or with conventional methods, a high electrical passivation quality of the emitter surface can be achieved.
  • the invention relates in particular to semiconductor structures in which an n-doped silicon wafer is used as the semiconductor substrate in which a p-doped emitter region is produced on an emitter surface by means of diffusion.
  • semiconductor materials within the scope of the invention are those in which an emitter surface of a semiconductor substrate P-type emitter region is arranged to form an emitter / base pn junction with an n-doped base.
  • the invention is based on the finding that a plurality of passivation methods is known for the passivation of surfaces of a semiconductor substrate, on which an n-doped region is directly arranged, whereas the passivation of a surface of a semiconductor substrate, to which a p-doped region immediately adjoins adjacent, comparatively difficult to implement.
  • a passivation effect are suitable: These include, for. Amorphous silicon, amorphous silicon carbide, silicon nitride, alumina and especially silicon oxide. These methods also lead to n-doped areas, which have a highly doped surface (doping concentrations> 10 18 cm "3 ) at very low surface recombination rates and thus to a good passivation effect.
  • the semiconductor structure according to the invention comprises, as already described in the known semiconductor structures, an n-type metallization and a p-type metallization as well as a semiconductor substrate with an n-doped base region and an at least partially adjacent p-doped emitter region for forming an emitter-base pn junction.
  • the emitter region extends at least partially approximately parallel to a surface of the semiconductor substrate, which is referred to below as "emitter surface”.
  • the n-type metallization is electrically connected to the base region and the p-type metallization to the emitter region.
  • the semiconductor structure additionally comprises an n-doped passivation region. This is arranged at least partially between the emitter surface and the emitter region.
  • the passivation region is electrically connected to neither the n-metallization nor the p-metallization.
  • the semiconductor structure according to the invention thus basically has the properties of a semiconductor structure known per se with an n-doped base and a p-doped emitter. It is crucial that at least partially the emitter surface of the semiconductor substrate
  • Passivation region between emitter surface and emitter region is arranged.
  • a passivation region / emitter-pn junction is formed so that the emitter is not electrically conductively connected to the emitter surface and thus electrically from the surface and any recombination centers at the emitter surface, for example by impurities or defects shielded in the crystal structure.
  • the emitter surface is thus at least partially covered by the n-doped passivation region, which can be passivated much more effectively and cost-effectively using known methods, as compared to a p-doped region reaching directly up to the surface.
  • the semiconductor structure according to the invention thus makes it possible to form a semiconductor structure with an n-doped base and a p-doped emitter, in which case the effective passivation for n-doped surfaces can be used for passivation of the emitter surface.
  • the passivation region is embodied in such a way that a passivation region / emitter pn junction is formed that runs essentially parallel to the emitter surface of the semiconductor substrate.
  • the emitter surface of the semiconductor substrate is at least partially covered by a passivation layer in the region in which the passivation region extends along the emitter surface.
  • a passivation layer in the region in which the passivation region extends along the emitter surface.
  • the previously described known passivation layers containing silicon in particular layers of amorphous silicon or amorphous silicon carbide or silicon nitride or silicon dioxide are advantageous.
  • a large number of the industrially manufactured semiconductor structures are made of silicon, advantageously the semiconductor substrate is therefore a silicon wafer.
  • the passivation region is comparatively thin, ie. H. the Passivitations Scheme is formed such that the passivation region / emitter pn junction is substantially parallel to the emitter surface, at a distance of a maximum of 5 microns.
  • Investigations by the Applicant have shown that, in particular, a distance of 2 ⁇ m, in particular a distance of between 0.1 ⁇ m and 0.5 ⁇ m, from the emitter surface are advantageous.
  • the semiconductor structure according to the invention is thus constructed such that, in a section approximately perpendicular to the emitter surface starting from the emitter surface, first the passivation region, then the passivation region / emitter pn junction, then the emitter region, then the emitter / base pn Transition and finally the base follows.
  • the distance of the emitter / base pn junction to the emitter surface is thus always greater than the distance of the passivation region / emitter pn junction to the emitter surface.
  • the emitter region is designed such that the
  • Emitter / base pn junction substantially parallel to the emitter surface runs, at a distance of at most 5 .mu.m, in particular between 1 .mu.m and 3 .mu.m to the emitter surface.
  • the base region has a doping concentration in the range 10 14 cm “3 to 10 16 cm “ 3 , in particular, that the base region is doped by means of phosphorus.
  • the emitter region typically has an increasing distance to
  • the emitter region has a peak doping concentration, ie a maximum doping concentration of at least 10 18 cm -3 , in particular the emitter region is advantageously produced by means of boron diffusion.
  • the passivation region advantageously has a peak doping concentration of at least 10 18 cm -3 .
  • the passivation region is produced by diffusion of phosphorus.
  • the semiconductor structure according to the invention is particularly suitable for
  • a typical solar cell includes a semiconductor structure comprising n-type metallization and p-type metallization, and a semiconductor substrate.
  • the semiconductor substrate has a front side as described above Coupling of electromagnetic radiation and a substantially parallel to the front back.
  • the semiconductor structure of the solar cell is a semiconductor structure according to the invention as described above, so that the
  • Emitter region is at least partially shielded by the passivation of the emitter surface.
  • the emitter is located at a solar cell immediately at the front for coupling electromagnetic radiation.
  • the emitter surface of the semiconductor structure according to the invention is the front for coupling electromagnetic radiation.
  • the solar cell according to the invention therefore has a p-type metallization on the front side, which partially covers the front side of the solar cell.
  • the front side of the solar cell has at least one front side contact region covered by the p metallization, in which the emitter region is arranged directly on the emitter surface of the semiconductor substrate and the p metallization is electrically conductively connected to the emitter region.
  • the passivation region does not extend over the entire front side of the solar cell, but the solar cell has at least one front contact region in which the emitter region directly adjoins the emitter surface of the semiconductor substrate and at least on the emitter surface in this region partially the p-type metallization, which is electrically connected to the emitter region, so that charge carriers can be removed from the emitter via the p-type metallization.
  • the intermediate Passivitations Symposium the intermediate Passivitations
  • solar cell structures are known in which both the p- and the n-metallization are located on the back of the solar cell and in the For example, emitter arranged in the region of the front side of the solar cell is electrically conductively connected to the p-metallization on the rear side of the solar cell through holes in the semiconductor substrate.
  • the passivation region covers approximately the entire front side of the solar cell, so that the emitter region is electrically shielded over the entire front side of the solar cell and recombination losses are avoided.
  • the n-type metallization is arranged on the rear side of the solar cell and electrically conductively connected to the base of the solar cell.
  • the invention further relates to a method for producing a semiconductor structure, in which a p-emitter region is generated on an emitter surface of an n-doped semiconductor substrate, to form an emitter / base pn junction.
  • n-passivation region is generated on the emitter surface, which is arranged at least partially between emitter surface and emitter region.
  • p-emitter region and / or passivation region are generated by means of diffusion of dopants.
  • the passivation region is formed by generating an overcompensation of the emitter region. This means that initially the emitter is formed directly adjacent to the emitter surface of the semiconductor substrate. Subsequently, an n-doping is carried out at least partially on the emitter surface, which corresponds to at least one of the p-type doping of the emitter
  • the overcompensation is generated by diffusion through the emitter surface.
  • the emitter surface of the semiconductor structure is at least partially covered with a passivation layer.
  • This passivation layer is advantageously a silicon-containing layer, in particular a layer of amorphous silicon or amorphous silicon carbide or silicon nitride or silicon dioxide.
  • a front side metallization is applied to the emitter surface, which at least partially covers the emitter surface.
  • this comprises the following method steps:
  • a p-doped emitter region is diffused on an emitter surface of an n-doped semiconductor substrate.
  • a masking layer is applied to the emitter surface, which partially covers the emitter surface.
  • a passivation region is diffused in the regions of the emitter surface which are not covered by the masking layer.
  • the passivation region is generated by overcompensation of the emitter region.
  • a p-type metallization is applied to the emitter front side of the semiconductor substrate at least in the regions in which the emitter region is arranged directly on the emitter front side.
  • the masking layer at which regions of the emitter surface the passivation region is arranged and at which regions the emitter region extends directly to the emitter surface, so that it makes contact with the p-metallization can be and thus an electrically conductive connection between p-type metallization and emitter is made.
  • the masking layer is produced in a per se known method by means of photolithography or using an inkjet printing process.
  • step B it is likewise within the scope of the invention to produce the masking layer in step B by means of screen printing methods known per se.
  • a passivation layer is advantageously applied over the entire surface of the emitter surface or at least on the emitter surface in the passivation region.
  • the passivation layer is applied between step C and D.
  • step D p-metallization is applied in an advantageous embodiment of the method according to the invention on the entire surface of the emitter surface covering passivation layer. Subsequently, the p-type metallization is electrically conductively connected through the passivation layer to the underlying emitter region. This is possible for example by a temperature step in which the p-
  • Metallization due to the action of heat passes through the passivation layer and generates a contact with the emitter region, so that the emitter region is electrically conductively connected to the p-type metallization.
  • FIG. 1 shows an embodiment of a method according to the invention with a schematic representation of the manufacturing process of a
  • FIG. 1 a semiconductor structure is shown in FIGS. A to F, wherein the figures show the production process of a semiconductor structure according to the invention shown schematically in FIG.
  • a solar cell is produced, which comprises a semiconductor structure according to the invention and is produced in a method according to the invention.
  • Starting material is an n-doped silicon wafer 1, which is doped approximately homogeneously with a doping concentration of about 10 15 cm '3 .
  • the n-doped region of the silicon wafer 1 thus represents the base region.
  • a p-doped emitter region 2 is located in the upper region of the silicon wafer 1, so that an emitter / base pn junction 2 a is formed between the base region and the emitter region 2.
  • the emitter region is produced in which an indiffusion of boron atoms is carried out via an emitter surface 2b of the silicon wafer 1.
  • the peak concentration of the emitter is about 10 18 cm "3 .
  • the emitter surface 2b is oxidized by thermal treatment in an oxygen atmosphere, so that a masking layer 3 of silicon dioxide is formed on the emitter surface 2b.
  • This further has the advantage that, when this masking layer 3 is formed, the boron atoms in the emitter region 2 are driven deeper into the silicon wafer 1 with respect to the emitter surface 2b.
  • the masking layer 3 is locally structured by adding parts of the
  • Masking layer 3 are removed. This is possible, for example, by local application of a lacquer layer 4, as shown in FIG.
  • the lacquer layer 4 is applied in the regions in which the emitter region 2 is to extend directly to the emitter surface 2b in the finished solar cell.
  • the lacquer layer 4 can be applied for example by means of screen printing, as well as the application of the lacquer layer by means of photolithography or an inkjet printing process is conceivable.
  • the Masking layer is removed in the areas where it is not covered by the lacquer layer and then the lacquer layer is removed again.
  • the structuring of the masking layer 3 can also take place in that the masking layer 3 is partially removed by laser radiation or by mechanical action.
  • a passivation region / emitter pn junction 5a forms between passivation region 5 and emitter region 2.
  • the above-described emitter region 2 and passivation region 5 diffusions were carried out in such a way that the emitter / base pn junction 2 a is at a distance of approximately 3 ⁇ m from the emitter surface 2 b and runs approximately parallel to this surface 2 b.
  • the passivation region / emitter pn junction 5a is located at a distance of approximately 0.3 ⁇ m from the emitter surface 2b and likewise runs approximately parallel to it.
  • the majority of the emitter surface 2b is now covered by the n-doped passivation region 5 and can therefore be passivated using the conventionally known methods for n-doped surfaces.
  • the p-doped emitter region 2 is electrically shielded from the emitter surface 2b by the passivation region 5 and in particular the passivation region / emitter pn junction 5a, except those regions in which the emitter region 2 directly adjoins the emitter surface 2b.
  • the masking layer 3 is first removed completely and then a passivation layer 6 is applied to the entire emitter surface 2b.
  • This passivation layer can be, for example, a silicon dioxide layer produced by thermal oxidation.
  • the passivation layer 6 reduces the surface recombination rate at the emitter surface 2b and thus further increases the efficiency of the solar cell.
  • a p-type metallization 7 on the front of the solar cell i. applied to the passivation layer 6, so that the p-type metallization 7 partially covers the front of the solar cell.
  • the p-type metallization 7 is applied at least partially in the regions in which the emitter region 2 directly reaches the emitter surface 2b.
  • the p-type metallization 7 is passed through the passivation layer 6 by means of heat, so that an electrically conductive connection between p-type metallization 7 and emitter region 2 is formed and the emitter region 2 is thus contacted.
  • the invention makes it possible to produce solar cells from silicon wafers, wherein the solar cells have a p-doped emitter on the side facing the light irradiation and surface passivation can be achieved there using standard methods for n-doped surfaces.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne une structure semi-conductrice comprenant une métallisation de type p (7), ainsi qu'un substrat à semi-conducteurs et une zone de base dopée n et une zone émettrice dopée p (2) qui jouxte au moins en partie la précédente par dessus, afin de former une jonction pn émission/base. La zone émettrice (2) s'étend au moins en partie approximativement parallèlement à une surface émettrice (2b) du support à semi-conducteurs et la métallisation de type n est reliée de manière électroconductrice à la zone de base, la métallisation de type p étant reliée quant à elle de manière électroconductrice à la zone émettrice (2). L'invention se caractérise en ce que la structure semi-conductrice comprend en outre une zone de passivation dopée n (5) qui est aménagée au moins en partie entre la surface émettrice (2b) et la zone émettrice (2). La zone de passivation (5) n'est reliée de manière électroconductrice ni à la métallisation de type n ni à la métallisation de type p. L'invention concerne également un procédé pour produire une structure semi-conductrice de ce type.
PCT/EP2008/010639 2008-01-21 2008-12-15 Structure semi-conductrice et procédé de production d'une structure semi-conductrice WO2009092424A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP08871574A EP2235758A2 (fr) 2008-01-21 2008-12-15 Structure semi-conductrice et procédé de production d'une structure semi-conductrice

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008005398.8 2008-01-21
DE102008005398A DE102008005398A1 (de) 2008-01-21 2008-01-21 Halbleiterstruktur und Verfahren zur Herstellung einer Halbleiterstruktur

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WO2009092424A2 true WO2009092424A2 (fr) 2009-07-30
WO2009092424A3 WO2009092424A3 (fr) 2009-09-24

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US8603900B2 (en) 2009-10-27 2013-12-10 Varian Semiconductor Equipment Associates, Inc. Reducing surface recombination and enhancing light trapping in solar cells
DE102010026331A1 (de) * 2010-07-07 2012-02-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Materialabtrag an Festkörpern

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US5053083A (en) * 1989-05-08 1991-10-01 The Board Of Trustees Of The Leland Stanford Junior University Bilevel contact solar cells

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
HOEX B ET AL: "Excellent passivation of highly doped p-type Si surfaces by the negative-charge-dielectric Al2O3" APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, Bd. 91, Nr. 11, 11. September 2007 (2007-09-11), Seiten 112107-112107, XP012099144 ISSN: 0003-6951 *
J. BENICK, A. LEIMENSTOLL, O. SCHULTZ: "Comprehensive studies of passivation quality on boron diffused silicon surfaces" 22ND EUROPEAN PHOTOVOLTAIC SOLAR ENERGY CENFERENCE AND EXHIBITION 2007, 3. September 2007 (2007-09-03), - 7. September 2007 (2007-09-07) Seiten 1-4, XP002532441 Milan, Italy *
JAN BENICK, OLIVER SCHULTZ-WITTMANN, JONAS SCHÖN, STEFAN W. GLUNZ: PHYSICA STATUS SOLIDI-RAPID RESEARCH LETTERS, Bd. 2, Nr. 4, 7. Juli 2008 (2008-07-07), Seiten 145-147, XP002532331 *
NARASIMHA S ET AL: "Back surface field and emitter passivation effects in the record high efficiency n-type dendritic web silicon solar cell" CONFERENCE RECORD OF THE 26TH IEEE PHOTOVOLTAIC SPECIALISTS CONFERENCE 19970929; 19970929 - 19971003 NEW YORK, NY : IEEE, US, 29. September 1997 (1997-09-29), Seiten 235-238, XP010267770 ISBN: 978-0-7803-3767-1 *
See also references of EP2235758A2 *
VETTER M ET AL: "Investigation of the Surface Passivation of P+-Type Si Emitters by PECVD Silicon Carbide Films" PHOTOVOLTAIC ENERGY CONVERSION, CONFERENCE RECORD OF THE 2006 IEEE 4TH WORLD CONFERENCE ON, IEEE, PI, 1. Mai 2006 (2006-05-01), Seiten 1271-1274, XP031007546 ISBN: 978-1-4244-0016-4 *

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DE102008005398A1 (de) 2009-07-30
EP2235758A2 (fr) 2010-10-06
WO2009092424A3 (fr) 2009-09-24

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