WO2009075316A1 - 記憶装置および情報再記録方法 - Google Patents

記憶装置および情報再記録方法 Download PDF

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Publication number
WO2009075316A1
WO2009075316A1 PCT/JP2008/072489 JP2008072489W WO2009075316A1 WO 2009075316 A1 WO2009075316 A1 WO 2009075316A1 JP 2008072489 W JP2008072489 W JP 2008072489W WO 2009075316 A1 WO2009075316 A1 WO 2009075316A1
Authority
WO
WIPO (PCT)
Prior art keywords
recording
value
δvwl
resistance
small
Prior art date
Application number
PCT/JP2008/072489
Other languages
English (en)
French (fr)
Inventor
Tomohito Tsushima
Tsunenori Shiimoto
Shuichiro Yasuda
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to US12/747,413 priority Critical patent/US8213214B2/en
Publication of WO2009075316A1 publication Critical patent/WO2009075316A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0071—Write using write potential applied to access device gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Semiconductor Memories (AREA)

Abstract

　記録の際の抵抗値レベルの調整能力を向上させ、安定したベリファイ制御を行うことのできる記憶装置を提供する。トランジスタ２０の制御端子２０ｃに対して第２電源２２から供給されるＶＷＬを、ＷＬ調整回路２４によって、ベリファイ制御による再記録毎に増加（増加分ΔＶＷＬ）させる。可変抵抗素子１０が多値記録可能である場合には、ΔＶＷＬは多値情報の抵抗値レベル毎に異なる値とする。すなわち、ΔＶＷＬは、電流による可変抵抗素子１０の記録抵抗の変化幅の大小関係に応じて異なる値とされ、記録抵抗の変化幅が大きい（トランジスタ２０のソース・ゲート間電圧ＶＧＳが小さい）領域では少なく、記録抵抗の変化幅が小さい（ＶＧＳが大きい）領域では多くなる。
PCT/JP2008/072489 2007-12-12 2008-12-11 記憶装置および情報再記録方法 WO2009075316A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/747,413 US8213214B2 (en) 2007-12-12 2008-12-11 Storage device and information rerecording method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-320579 2007-12-12
JP2007320579A JP4356786B2 (ja) 2007-12-12 2007-12-12 記憶装置および情報再記録方法

Publications (1)

Publication Number Publication Date
WO2009075316A1 true WO2009075316A1 (ja) 2009-06-18

Family

ID=40755556

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072489 WO2009075316A1 (ja) 2007-12-12 2008-12-11 記憶装置および情報再記録方法

Country Status (3)

Country Link
US (1) US8213214B2 (ja)
JP (1) JP4356786B2 (ja)
WO (1) WO2009075316A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441868B2 (en) 2010-04-09 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory having a read circuit

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5151439B2 (ja) * 2007-12-12 2013-02-27 ソニー株式会社 記憶装置および情報再記録方法
US8331128B1 (en) 2008-12-02 2012-12-11 Adesto Technologies Corporation Reconfigurable memory arrays having programmable impedance elements and corresponding methods
JP5044617B2 (ja) 2009-08-31 2012-10-10 株式会社東芝 不揮発性半導体記憶装置
US8614911B2 (en) * 2011-12-22 2013-12-24 International Business Machines Corporation Energy-efficient row driver for programming phase change memory
JP6162931B2 (ja) * 2012-06-19 2017-07-12 ソニーセミコンダクタソリューションズ株式会社 記憶素子および記憶装置
US9047945B2 (en) 2012-10-15 2015-06-02 Marvell World Trade Ltd. Systems and methods for reading resistive random access memory (RRAM) cells
US9042159B2 (en) * 2012-10-15 2015-05-26 Marvell World Trade Ltd. Configuring resistive random access memory (RRAM) array for write operations
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
WO2014070852A1 (en) 2012-10-31 2014-05-08 Marvell World Trade Ltd. Sram cells suitable for fin field-effect transistor (finfet) process
CN105190760B (zh) 2012-11-12 2018-04-24 马维尔国际贸易有限公司 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元
JP6251885B2 (ja) * 2013-04-26 2017-12-27 パナソニックＩｐマネジメント株式会社 抵抗変化型不揮発性記憶装置およびその書き込み方法
US9544864B1 (en) * 2016-03-07 2017-01-10 Panasonic Liquid Crystal Display Co., Ltd. Data transmission system and receiving device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11110977A (ja) * 1997-10-06 1999-04-23 Sony Corp 不揮発性半導体記憶装置
JP2007018615A (ja) * 2005-07-08 2007-01-25 Sony Corp 記憶装置及び半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4113493B2 (ja) * 2003-06-12 2008-07-09 シャープ株式会社 不揮発性半導体記憶装置及びその制御方法
JP4670252B2 (ja) 2004-01-20 2011-04-13 ソニー株式会社 記憶装置
KR100621636B1 (ko) * 2005-06-01 2006-09-07 삼성전자주식회사 워드 라인 전압 발생 회로 및 그것을 갖는 불 휘발성메모리 장치
JP4475174B2 (ja) * 2005-06-09 2010-06-09 ソニー株式会社 記憶装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11110977A (ja) * 1997-10-06 1999-04-23 Sony Corp 不揮発性半導体記憶装置
JP2007018615A (ja) * 2005-07-08 2007-01-25 Sony Corp 記憶装置及び半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441868B2 (en) 2010-04-09 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory having a read circuit

Also Published As

Publication number Publication date
US20100259968A1 (en) 2010-10-14
US8213214B2 (en) 2012-07-03
JP4356786B2 (ja) 2009-11-04
JP2009146479A (ja) 2009-07-02

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