WO2008114716A1 - Ｓｒａｍ装置 - Google Patents

Ｓｒａｍ装置 Download PDF

Info

Publication number
WO2008114716A1
WO2008114716A1 PCT/JP2008/054720 JP2008054720W WO2008114716A1 WO 2008114716 A1 WO2008114716 A1 WO 2008114716A1 JP 2008054720 W JP2008054720 W JP 2008054720W WO 2008114716 A1 WO2008114716 A1 WO 2008114716A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
transistor
controlling
field effect
sram device
Prior art date
Application number
PCT/JP2008/054720
Other languages
English (en)
French (fr)
Inventor
Shinichi Ouchi
Meishoku Masahara
Original Assignee
National Institute Of Advanced Industrial Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute Of Advanced Industrial Science And Technology filed Critical National Institute Of Advanced Industrial Science And Technology
Priority to JP2009505192A priority Critical patent/JP5035335B2/ja
Priority to US12/531,780 priority patent/US20100110774A1/en
Publication of WO2008114716A1 publication Critical patent/WO2008114716A1/ja
Priority to US13/295,398 priority patent/US8243501B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)

Abstract

　起立した半導体薄板の両面に電気的に切り離されたトランジスタ駆動用のゲート及びしきい値制御用のゲートを有する４端子型ダブルゲート電界効果トランジスタを選択トランジスタとして用い、上記選択トランジスタのしきい値制御用ゲートに対して書き込み動作時には、読み出しの動作にある際よりも、しきい値電圧を下げるような電圧を入力することを特徴とし、書き込み余裕、読み出し余裕の双方を大きくすることが可能なＳＲＡＭ装置である。
PCT/JP2008/054720 2007-03-20 2008-03-14 Ｓｒａｍ装置 WO2008114716A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009505192A JP5035335B2 (ja) 2007-03-20 2008-03-14 Ｓｒａｍ装置
US12/531,780 US20100110774A1 (en) 2007-03-20 2008-03-14 Sram device
US13/295,398 US8243501B2 (en) 2007-03-20 2011-11-14 SRAM device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-072903 2007-03-20
JP2007072903 2007-03-20

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/531,780 A-371-Of-International US20100110774A1 (en) 2007-03-20 2008-03-14 Sram device
US13/295,398 Continuation US8243501B2 (en) 2007-03-20 2011-11-14 SRAM device

Publications (1)

Publication Number Publication Date
WO2008114716A1 true WO2008114716A1 (ja) 2008-09-25

Family

ID=39765824

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/054720 WO2008114716A1 (ja) 2007-03-20 2008-03-14 Ｓｒａｍ装置

Country Status (3)

Country Link
US (2) US20100110774A1 (ja)
JP (1) JP5035335B2 (ja)
WO (1) WO2008114716A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010135585A (ja) * 2008-12-05 2010-06-17 Sony Corp 半導体装置およびその製造方法
US20120201072A1 (en) * 2010-11-16 2012-08-09 Texas Instruments Incorporated Sram cell having an n-well bias
KR20120090001A (ko) 2010-12-28 2012-08-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 기억 장치
KR20120092003A (ko) 2010-12-28 2012-08-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 기억 장치
JP5382886B2 (ja) * 2009-07-29 2014-01-08 独立行政法人産業技術総合研究所 Ｓｒａｍセル

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5278971B2 (ja) 2010-03-30 2013-09-04 独立行政法人産業技術総合研究所 Ｓｒａｍ装置
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
KR102178732B1 (ko) 2013-12-20 2020-11-13 삼성전자주식회사 반도체 소자
US9548138B2 (en) * 2014-09-02 2017-01-17 Macronix International Co., Ltd. Test method for memory
KR102352153B1 (ko) 2015-03-25 2022-01-17 삼성전자주식회사 집적회로 장치 및 이의 제조 방법
KR20210024912A (ko) * 2019-08-26 2021-03-08 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
US20210391462A1 (en) * 2020-06-15 2021-12-16 Korea Advanced Institute Of Science And Technology Single Transistor with Double Gate Structure for Adjustable Firing Threshold Voltage, and Neuromorphic System Using the Same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005174960A (ja) * 2003-12-05 2005-06-30 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005260607A (ja) * 2004-03-11 2005-09-22 National Institute Of Advanced Industrial & Technology 二重絶縁ゲート電界効果トランジスタを用いたｃｍｏｓ回路
JP2007103629A (ja) * 2005-10-04 2007-04-19 Renesas Technology Corp 半導体記憶装置
JP2007201107A (ja) * 2006-01-25 2007-08-09 Toshiba Corp 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6606267B2 (en) * 1998-06-23 2003-08-12 Sandisk Corporation High data rate write process for non-volatile flash memories
US7378710B2 (en) * 2002-12-19 2008-05-27 International Business Machines Corporation FinFET SRAM cell using inverted FinFET thin film transistors
JP2005167163A (ja) 2003-12-05 2005-06-23 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
US7532501B2 (en) * 2005-06-02 2009-05-12 International Business Machines Corporation Semiconductor device including back-gated transistors and method of fabricating the device
US20070183185A1 (en) * 2006-01-11 2007-08-09 The Regents Of The University Of California Finfet-based sram with feedback
FR2898432B1 (fr) * 2006-03-10 2008-04-11 Commissariat Energie Atomique Cellules memoire en technologie cmos double-grille dotee de transistors a deux grilles independantes
US7400525B1 (en) * 2007-01-11 2008-07-15 International Business Machines Corporation Memory cell with independent-gate controlled access devices and memory using the cell
US7408800B1 (en) * 2007-05-03 2008-08-05 International Business Machines Corporation Apparatus and method for improved SRAM device performance through double gate topology
US7710765B2 (en) * 2007-09-27 2010-05-04 Micron Technology, Inc. Back gated SRAM cell

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005174960A (ja) * 2003-12-05 2005-06-30 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005260607A (ja) * 2004-03-11 2005-09-22 National Institute Of Advanced Industrial & Technology 二重絶縁ゲート電界効果トランジスタを用いたｃｍｏｓ回路
JP2007103629A (ja) * 2005-10-04 2007-04-19 Renesas Technology Corp 半導体記憶装置
JP2007201107A (ja) * 2006-01-25 2007-08-09 Toshiba Corp 半導体装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010135585A (ja) * 2008-12-05 2010-06-17 Sony Corp 半導体装置およびその製造方法
US8362565B2 (en) 2008-12-05 2013-01-29 Sony Corporation Memory element with small threshold voltage variance and high-speed logic element with low power consumption
JP5382886B2 (ja) * 2009-07-29 2014-01-08 独立行政法人産業技術総合研究所 Ｓｒａｍセル
US20120201072A1 (en) * 2010-11-16 2012-08-09 Texas Instruments Incorporated Sram cell having an n-well bias
US10629250B2 (en) * 2010-11-16 2020-04-21 Texas Instruments Incorporated SRAM cell having an n-well bias
KR20120090001A (ko) 2010-12-28 2012-08-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 기억 장치
KR20120092003A (ko) 2010-12-28 2012-08-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 기억 장치
US8674351B2 (en) 2010-12-28 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor memory device
US9263471B2 (en) 2010-12-28 2016-02-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor memory device
US9698169B2 (en) 2010-12-28 2017-07-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor memory device

Also Published As

Publication number Publication date
US20100110774A1 (en) 2010-05-06
US8243501B2 (en) 2012-08-14
JP5035335B2 (ja) 2012-09-26
JPWO2008114716A1 (ja) 2010-07-01
US20120057398A1 (en) 2012-03-08

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