WO2009072509A1 - 試験装置およびキャリブレーション方法 - Google Patents

試験装置およびキャリブレーション方法 Download PDF

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Publication number
WO2009072509A1
WO2009072509A1 PCT/JP2008/071928 JP2008071928W WO2009072509A1 WO 2009072509 A1 WO2009072509 A1 WO 2009072509A1 JP 2008071928 W JP2008071928 W JP 2008071928W WO 2009072509 A1 WO2009072509 A1 WO 2009072509A1
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WO
WIPO (PCT)
Prior art keywords
unit
voltage
tested device
testing apparatus
signal
Prior art date
Application number
PCT/JP2008/071928
Other languages
English (en)
French (fr)
Inventor
Shigeki Takizawa
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to JP2009544686A priority Critical patent/JP5279724B2/ja
Priority to CN2008801194929A priority patent/CN101889212A/zh
Publication of WO2009072509A1 publication Critical patent/WO2009072509A1/ja

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　被試験デバイスを試験する試験装置であって、複数の信号生成部および被試験デバイスの良否を判定する判定部を備え、それぞれの信号生成部は、被試験デバイスの対応するピンに試験信号を供給するドライバ部と、試験信号に応じて被試験デバイスが出力する信号に基づいて、ドライバ部が出力する信号の直流電圧を検出する電圧測定部と、電圧測定部が検出した直流電圧に応じて、ドライバ部が出力する信号のデューティー比を調整する出力側調整部とを有し、それぞれのレベル測定部は、被試験デバイスに所定の電流を供給したときに、被試験デバイスに印加される電圧レベルを測定可能に設けられる。
PCT/JP2008/071928 2007-12-06 2008-12-03 試験装置およびキャリブレーション方法 WO2009072509A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009544686A JP5279724B2 (ja) 2007-12-06 2008-12-03 試験装置およびキャリブレーション方法
CN2008801194929A CN101889212A (zh) 2007-12-06 2008-12-03 测试装置及校准方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/951,335 2007-12-06
US11/951,335 US7802160B2 (en) 2007-12-06 2007-12-06 Test apparatus and calibration method

Publications (1)

Publication Number Publication Date
WO2009072509A1 true WO2009072509A1 (ja) 2009-06-11

Family

ID=40717688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071928 WO2009072509A1 (ja) 2007-12-06 2008-12-03 試験装置およびキャリブレーション方法

Country Status (6)

Country Link
US (1) US7802160B2 (ja)
JP (1) JP5279724B2 (ja)
KR (1) KR20100081352A (ja)
CN (1) CN101889212A (ja)
TW (1) TW200931030A (ja)
WO (1) WO2009072509A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012156709A (ja) * 2011-01-25 2012-08-16 Advantest Corp 信号発生装置および試験装置

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US8793091B2 (en) * 2008-04-10 2014-07-29 Nvidia Corporation System and method for integrated circuit calibration
CN103592613B (zh) * 2013-11-22 2016-09-28 上海华岭集成电路技术股份有限公司 测试校正仪、测试系统及测试方法
KR102037231B1 (ko) * 2013-12-23 2019-10-29 한국전자통신연구원 복수의 샘플들을 테스트하는 테스트 장치 및 그것의 동작 방법
CN105572564A (zh) * 2015-12-17 2016-05-11 中广核核电运营有限公司 核电站核级逆变器卡件集成测试系统及方法
CN105510858A (zh) * 2015-12-17 2016-04-20 中广核核电运营有限公司 一种逆变器静态旁路开关电压监测卡工作性能测试系统及方法
CN105629188A (zh) * 2015-12-22 2016-06-01 中广核核电运营有限公司 核电站逆变电压监测卡一体化测试系统及测试方法
CN105572513A (zh) * 2016-02-03 2016-05-11 中广核核电运营有限公司 一种逆变器触发卡测试系统及方法
CN105629040A (zh) * 2016-02-03 2016-06-01 中广核核电运营有限公司 不间断电源的整流监测控制板的报警定值监测系统、方法
CN105759138A (zh) * 2016-02-03 2016-07-13 中广核核电运营有限公司 核电站用磁饱和逆变器静态开关卡拷机测试系统及方法
CN105572514A (zh) * 2016-02-03 2016-05-11 中广核核电运营有限公司 不间断电源静态旁路开关接口板板件独立测试系统及方法
CN105572515A (zh) * 2016-02-03 2016-05-11 中广核核电运营有限公司 核电站逆变器相位比较卡工作性能测试系统及测试方法
JP6688665B2 (ja) * 2016-04-11 2020-04-28 横河電機株式会社 機器保全装置、機器保全方法、機器保全プログラム及び記録媒体
WO2018162049A1 (en) * 2017-03-07 2018-09-13 Advantest Corporation Test apparatus for performing a test on a device under test and data set filter for filtering a data set to obtain a best setting of a device under test
WO2018162050A1 (en) * 2017-03-07 2018-09-13 Advantest Corporation Tester and method for testing a device under test using relevance scores
CN107422212B (zh) * 2017-08-23 2023-08-08 国网电力科学研究院武汉南瑞有限责任公司 一种电子式直流互感器暂态特性试验装置及控制方法
CN109709474B (zh) * 2019-02-28 2021-06-04 西安太乙电子有限公司 一种射频混合信号集成电路测试系统与测试方法
CN110261806B (zh) * 2019-06-14 2021-08-31 杭州优迈科技有限公司 驱动器、变频器以及驱动器的校准方法、控制方法
CN117111576B (zh) * 2023-08-16 2024-06-18 深圳市新力川电气有限公司 驱动器测试设备及使用其进行的驱动器测试方法

Citations (5)

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JPH0578037U (ja) * 1992-03-26 1993-10-22 日本電気ホームエレクトロニクス株式会社 波形整形装置
US5315164A (en) * 1993-05-26 1994-05-24 Nec America, Inc. Adaptive clock duty cycle controller
JP2000009804A (ja) * 1998-06-23 2000-01-14 Advantest Corp 半導体デバイス試験装置および信号出力装置
JP2002156422A (ja) * 2000-11-17 2002-05-31 Advantest Corp 半導体試験装置
JP2007174669A (ja) * 2005-12-21 2007-07-05 Internatl Business Mach Corp <Ibm> 差動クロック信号のデューティサイクル歪みを補正する回路および方法

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Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH0578037U (ja) * 1992-03-26 1993-10-22 日本電気ホームエレクトロニクス株式会社 波形整形装置
US5315164A (en) * 1993-05-26 1994-05-24 Nec America, Inc. Adaptive clock duty cycle controller
JP2000009804A (ja) * 1998-06-23 2000-01-14 Advantest Corp 半導体デバイス試験装置および信号出力装置
JP2002156422A (ja) * 2000-11-17 2002-05-31 Advantest Corp 半導体試験装置
JP2007174669A (ja) * 2005-12-21 2007-07-05 Internatl Business Mach Corp <Ibm> 差動クロック信号のデューティサイクル歪みを補正する回路および方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012156709A (ja) * 2011-01-25 2012-08-16 Advantest Corp 信号発生装置および試験装置

Also Published As

Publication number Publication date
TWI379086B (ja) 2012-12-11
US20090150733A1 (en) 2009-06-11
JPWO2009072509A1 (ja) 2011-04-21
US7802160B2 (en) 2010-09-21
KR20100081352A (ko) 2010-07-14
JP5279724B2 (ja) 2013-09-04
CN101889212A (zh) 2010-11-17
TW200931030A (en) 2009-07-16

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