WO2009037769A1 - 半導体集積回路装置および半導体集積回路装置の試験方法 - Google Patents
半導体集積回路装置および半導体集積回路装置の試験方法 Download PDFInfo
- Publication number
- WO2009037769A1 WO2009037769A1 PCT/JP2007/068257 JP2007068257W WO2009037769A1 WO 2009037769 A1 WO2009037769 A1 WO 2009037769A1 JP 2007068257 W JP2007068257 W JP 2007068257W WO 2009037769 A1 WO2009037769 A1 WO 2009037769A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- semiconductor integrated
- integrated circuit
- same
- circuit device
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31707—Test strategies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
論理回路と、メモリ回路と、メモリ回路にデータを書き込む際に当該データを保持するレジスタ回路と、レジスタ回路からの出力とメモリ回路からの出力とのうちのいずれかを選択して論理回路に出力するセレクタ回路とよりなり、セレクタ回路で前記レジスタ回路からの出力を選択して論理回路に出力することで論理回路の動作試験を行う構成である。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009533001A JP5158087B2 (ja) | 2007-09-20 | 2007-09-20 | 半導体集積回路装置および半導体集積回路装置の試験方法 |
PCT/JP2007/068257 WO2009037769A1 (ja) | 2007-09-20 | 2007-09-20 | 半導体集積回路装置および半導体集積回路装置の試験方法 |
US12/656,696 US7843210B2 (en) | 2007-09-20 | 2010-02-12 | Semiconductor integrated circuit device and testing method of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/068257 WO2009037769A1 (ja) | 2007-09-20 | 2007-09-20 | 半導体集積回路装置および半導体集積回路装置の試験方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/656,696 Continuation US7843210B2 (en) | 2007-09-20 | 2010-02-12 | Semiconductor integrated circuit device and testing method of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009037769A1 true WO2009037769A1 (ja) | 2009-03-26 |
Family
ID=40467600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/068257 WO2009037769A1 (ja) | 2007-09-20 | 2007-09-20 | 半導体集積回路装置および半導体集積回路装置の試験方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7843210B2 (ja) |
JP (1) | JP5158087B2 (ja) |
WO (1) | WO2009037769A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018137024A (ja) * | 2017-02-21 | 2018-08-30 | 株式会社東芝 | 半導体集積回路 |
JP2020098182A (ja) * | 2018-12-19 | 2020-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01267475A (ja) * | 1988-04-19 | 1989-10-25 | Fujitsu Ltd | 論理集積回路 |
JPH1073641A (ja) * | 1996-08-30 | 1998-03-17 | Mitsubishi Electric Corp | テスト回路 |
JPH11101858A (ja) * | 1997-09-29 | 1999-04-13 | Toshiba Microelectronics Corp | 半導体集積回路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3132424B2 (ja) | 1997-06-13 | 2001-02-05 | 日本電気株式会社 | データ処理装置 |
JP2003100100A (ja) * | 2001-07-19 | 2003-04-04 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JP4481588B2 (ja) * | 2003-04-28 | 2010-06-16 | 株式会社東芝 | 半導体集積回路装置 |
JP2006155682A (ja) * | 2004-11-25 | 2006-06-15 | Matsushita Electric Ind Co Ltd | Lsiテスト回路 |
JP4707053B2 (ja) * | 2005-06-06 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
-
2007
- 2007-09-20 WO PCT/JP2007/068257 patent/WO2009037769A1/ja active Application Filing
- 2007-09-20 JP JP2009533001A patent/JP5158087B2/ja not_active Expired - Fee Related
-
2010
- 2010-02-12 US US12/656,696 patent/US7843210B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01267475A (ja) * | 1988-04-19 | 1989-10-25 | Fujitsu Ltd | 論理集積回路 |
JPH1073641A (ja) * | 1996-08-30 | 1998-03-17 | Mitsubishi Electric Corp | テスト回路 |
JPH11101858A (ja) * | 1997-09-29 | 1999-04-13 | Toshiba Microelectronics Corp | 半導体集積回路 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018137024A (ja) * | 2017-02-21 | 2018-08-30 | 株式会社東芝 | 半導体集積回路 |
JP2020098182A (ja) * | 2018-12-19 | 2020-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5158087B2 (ja) | 2013-03-06 |
US20100148816A1 (en) | 2010-06-17 |
US7843210B2 (en) | 2010-11-30 |
JPWO2009037769A1 (ja) | 2011-01-06 |
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