WO2009034963A1 - 半導体製造方法、半導体製造装置および表示装置 - Google Patents

半導体製造方法、半導体製造装置および表示装置 Download PDF

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Publication number
WO2009034963A1
WO2009034963A1 PCT/JP2008/066217 JP2008066217W WO2009034963A1 WO 2009034963 A1 WO2009034963 A1 WO 2009034963A1 JP 2008066217 W JP2008066217 W JP 2008066217W WO 2009034963 A1 WO2009034963 A1 WO 2009034963A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor manufacturing
crystal silicon
silicon film
fine crystal
display apparatus
Prior art date
Application number
PCT/JP2008/066217
Other languages
English (en)
French (fr)
Inventor
Akihiko Hiroe
Tadahiro Ohmi
Original Assignee
Tokyo Electron Limited
National University Corporation Tohoku University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited, National University Corporation Tohoku University filed Critical Tokyo Electron Limited
Priority to KR1020107002509A priority Critical patent/KR101046625B1/ko
Publication of WO2009034963A1 publication Critical patent/WO2009034963A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

ｎチャネル薄膜トランジスタおよびｐチャネル薄膜トランジスタの少なくともいずれかを製造する半導体製造方法であって、高密度プラズマを用いて少なくとも（２２０）の結晶方位配列に成長させるように微結晶シリコン膜を形成する第１の工程と、水素含有プラズマにより微結晶シリコン膜を水素にて終端させる第２の工程と、を有する。これにより、ダングリングボンドの少ない微結晶シリコン膜を形成して、移動度を高めることができる。
PCT/JP2008/066217 2007-09-14 2008-09-09 半導体製造方法、半導体製造装置および表示装置 WO2009034963A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020107002509A KR101046625B1 (ko) 2007-09-14 2008-09-09 반도체 제조 방법, 반도체 제조 장치 및 표시 장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007239646A JP2009071163A (ja) 2007-09-14 2007-09-14 半導体製造方法、半導体製造装置および表示装置
JP2007-239646 2007-09-14

Publications (1)

Publication Number Publication Date
WO2009034963A1 true WO2009034963A1 (ja) 2009-03-19

Family

ID=40451970

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/066217 WO2009034963A1 (ja) 2007-09-14 2008-09-09 半導体製造方法、半導体製造装置および表示装置

Country Status (3)

Country Link
JP (1) JP2009071163A (ja)
KR (1) KR101046625B1 (ja)
WO (1) WO2009034963A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011007682A1 (en) * 2009-07-17 2011-01-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP6172660B2 (ja) * 2012-08-23 2017-08-02 東京エレクトロン株式会社 成膜装置、及び、低誘電率膜を形成する方法
JP6194850B2 (ja) * 2014-05-21 2017-09-13 株式会社島津製作所 薄膜形成装置
WO2023234150A1 (ja) * 2022-05-31 2023-12-07 京セラ株式会社 流路構造体、半導体製造装置および流路構造体の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159021A (ja) * 1988-12-13 1990-06-19 Agency Of Ind Science & Technol 微結晶の配向性制御方法
JPH04152626A (ja) * 1990-10-17 1992-05-26 Seiko Epson Corp 半導体装置の製造方法
JP2002371357A (ja) * 2001-06-14 2002-12-26 Canon Inc シリコン系薄膜の形成方法、シリコン系薄膜及び半導体素子並びにシリコン系薄膜の形成装置
JP2007048982A (ja) * 2005-08-10 2007-02-22 Tokyo Electron Ltd プラズマ処理装置の制御方法およびプラズマ処理装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079312A (ja) * 2003-08-29 2005-03-24 Mitsubishi Electric Corp 半導体装置の製造方法およびそれに用いられる半導体製造装置並びに液晶表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159021A (ja) * 1988-12-13 1990-06-19 Agency Of Ind Science & Technol 微結晶の配向性制御方法
JPH04152626A (ja) * 1990-10-17 1992-05-26 Seiko Epson Corp 半導体装置の製造方法
JP2002371357A (ja) * 2001-06-14 2002-12-26 Canon Inc シリコン系薄膜の形成方法、シリコン系薄膜及び半導体素子並びにシリコン系薄膜の形成装置
JP2007048982A (ja) * 2005-08-10 2007-02-22 Tokyo Electron Ltd プラズマ処理装置の制御方法およびプラズマ処理装置

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHUAN JIE ZHONG: "Effect of power density on the structure properties of microcrystalline silicon films prepared by high-density low-ion-energy microwave plasma", THIN SOLID FILMS, vol. 493, no. 1-2, 25 July 2005 (2005-07-25), pages 54 - 59 *
KOICHI YOSHINO: "Fast deposition of microcrystalline silicon films with preferred (2 2 0)crystallographic texture using the high-density microwave plasma", SOLAR ENERGY MATERIALS AND SOLAR CELLS, vol. 74, no. 1-4, 16 April 2002 (2002-04-16), pages 505 - 511 *
SANG-MYEON HAN: "Hydrongenation of nanocrystalline Si thin film transistors employing inductively coupled plasma chemical vapor deposition for flexible electronics", THIN SOLID FILMS, vol. 515, no. 19, 9 January 2007 (2007-01-09), pages 7442 - 7445 *

Also Published As

Publication number Publication date
KR101046625B1 (ko) 2011-07-05
KR20100047859A (ko) 2010-05-10
JP2009071163A (ja) 2009-04-02

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