WO2009033871A1 - Verfahren zum herstellen einer vielzahl von chips und entsprechend hergestellter chip - Google Patents
Verfahren zum herstellen einer vielzahl von chips und entsprechend hergestellter chip Download PDFInfo
- Publication number
- WO2009033871A1 WO2009033871A1 PCT/EP2008/059688 EP2008059688W WO2009033871A1 WO 2009033871 A1 WO2009033871 A1 WO 2009033871A1 EP 2008059688 W EP2008059688 W EP 2008059688W WO 2009033871 A1 WO2009033871 A1 WO 2009033871A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chips
- surface layer
- substrate
- plastic
- chip
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000002344 surface layer Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 229920003023 plastic Polymers 0.000 claims abstract description 35
- 239000004033 plastic Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000725 suspension Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 6
- 150000001875 compounds Chemical class 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 235000010290 biphenyl Nutrition 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 claims 2
- 239000004593 Epoxy Substances 0.000 claims 1
- 239000004305 biphenyl Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000002131 composite material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- QFLWZFQWSBQYPS-AWRAUJHKSA-N (3S)-3-[[(2S)-2-[[(2S)-2-[5-[(3aS,6aR)-2-oxo-1,3,3a,4,6,6a-hexahydrothieno[3,4-d]imidazol-4-yl]pentanoylamino]-3-methylbutanoyl]amino]-3-(4-hydroxyphenyl)propanoyl]amino]-4-[1-bis(4-chlorophenoxy)phosphorylbutylamino]-4-oxobutanoic acid Chemical compound CCCC(NC(=O)[C@H](CC(O)=O)NC(=O)[C@H](Cc1ccc(O)cc1)NC(=O)[C@@H](NC(=O)CCCCC1SC[C@@H]2NC(=O)N[C@H]12)C(C)C)P(=O)(Oc1ccc(Cl)cc1)Oc1ccc(Cl)cc1 QFLWZFQWSBQYPS-AWRAUJHKSA-N 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000004074 biphenyls Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000006223 plastic coating Substances 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00865—Multistep processes for the separation of wafers into individual elements
- B81C1/00896—Temporary protection during separation into individual elements
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/05—Temporary protection of devices or parts of the devices during manufacturing
- B81C2201/053—Depositing a protective layers
Definitions
- the invention relates to a method for producing a plurality of chips whose functionality is based on the
- the surface layer of a substrate is realized.
- the surface layer of the substrate is structured and at least one cavity below the
- the suspension stays and / or support elements are separated.
- German patent application DE 103 50 036 A1 describes a method with which the singulation of the chips should be simplified. This method can also be used in particular in the production of thinned chips whose functionality is realized only in a surface layer of the semiconductor substrate.
- the lateral chip boundaries are defined here by means of etching trenches, which completely penetrate the surface layer of the substrate.
- cavities are produced below the surface layer using surface micromechanical methods, so that the individual chip areas are connected to the substrate layer underneath this cavity only via support elements in the region of a cavity. For separating the chips these support elements are then mechanically separated, for example in a tapping process in the context of the single-chip assembly.
- the surfaces of the chips produced by the known method are unprotected. They have to be subsequently passivated individually, ie sequentially. This proves to be problematic in practice, especially for extremely thin chips.
- the structured and undermined surface layer of the substrate is embedded in a plastic compound before the chips are singulated.
- all the chips are provided with a plastic package at the end of the processing in a single process step at the wafer level.
- a surface layer structured as described above which is connected to the carrier substrate only via suspensions and / or support elements, can be embedded so extensively in plastic that the resulting plastic coating forms a good surface passivation for the chips.
- This plastic casing also simplifies the handling of the subsequent separation and assembly significantly, especially with extremely thin chips.
- the chips are not only packaged in the wafer composite but also prepared in the wafer composite for a flip-chip assembly.
- the chip areas are provided with solder bumps before embedding in the plastic compound. Only then is the structured and undermined surface layer of the substrate embedded in the plastic compound, specifically so that the solder bumps protrude from the plastic compound.
- the so-packaged chips can be electrically contacted and mounted after singulation using the solder bumps.
- FIG. Ia shows a schematic longitudinal section through a substrate after the creation of cavities under a surface layer and FIG. 1b shows a horizontal section through the substrate shown in FIG. 1a in the region of the cavities under the surface layer.
- Fig. 4 shows the substrate shown in Fig. 3 in longitudinal section when removing the plastic-coated surface layer.
- Fig. 5 shows the chips obtained from the composite shown in Fig. 4 after singulation.
- FIGS. 1 to 5 show, by way of example for a multiplicity of chips, two chip areas in successive stages of the production method according to the invention. Accordingly, the same reference numerals are used for all figures.
- the embodiment described below relates to the production of extremely thinned chips, without the invention in question being limited to this type of chips. It is only essential that the functionality of the chips, ie the electrical circuit elements and possibly the mechanical Structural elements, starting from a surface layer 2 of a substrate 1 can be realized. For this purpose, these circuit and structural elements can be integrated either directly into the surface layer 2, as in the embodiment described here, or in a layer structure on this surface layer.
- FIGS. 1a and 1b show the substrate 1 after two cavities 3 have been produced under the surface layer 2, namely under the areas of the surface layer 2 in which a chip is to be realized in each case.
- These two square, membrane-like chip areas 5 are bounded by a border 6 of the substrate material and are each supported by five arranged in the region of the cavities 3 supporting elements 7 of substrate material and fixed for subsequent processing.
- the shape, number and position of the support elements can be chosen arbitrarily, as long as their diameter is in the order of magnitude of the membrane thickness.
- the cavities 3 are preferably processed by surface micromachining techniques, such as e.g. The APSM (Advanced Porous Silicon Membrane) method, wherein the support elements 7 are formed as a compound of the respective chip area 5 with the substrate layer 4 below the cavity 3.
- APSM Advanced Porous Silicon Membrane
- the chip edges are also exposed by the surface layer 2 is patterned accordingly.
- a trench process is preferably used, since this structuring method, the realization of any Chip shapes with or without thin suspension or connecting webs in the surface layer 2 allowed. Only then are semiconductor circuits 8 with conductor tracks and bond pads diffused into the chip areas 5 of the surface layer 2. The result of this process step is shown in FIG. 2, where the trench trenches are labeled 9.
- the semiconductor circuits 8 are each provided with solder bumps 10 on the chip surfaces, before the structured and undermined surface layer 2 of the substrate 1 according to the invention is embedded in a plastic compound 11.
- the substrate 1 can simply be overmolded in a wafer molding process with a suitable plastic compound.
- the mold tool is advantageously evacuated.
- FIG. 3 illustrates that the solder bumps 10 are protected as electrical contacting of the chips during overmolding, so that they protrude from the plastic casing 11 and can later still be soldered during chip assembly.
- the molded block with all embedded in plastic compound 11 chips is then lifted in a process step from the rest of the substrate 1, which is shown in Fig. 4.
- the support elements 7 and any formed in the surface layer 2 Auf rehabilitationstege be separated. Since the adhesion of mold compound on bare silicon, which is often used as a substrate material, is not very good, the molded block can be solved in these cases with relatively little effort from the rest of the substrate.
- the lifting of the plastic block can also by a Shearing or peeling motion or supported by the use of ultrasound.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
- Wire Bonding (AREA)
- Micromachines (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08786380A EP2191503A1 (de) | 2007-09-12 | 2008-07-24 | Verfahren zum herstellen einer vielzahl von chips und entsprechend hergestellter chip |
CN200880106772A CN101803003A (zh) | 2007-09-12 | 2008-07-24 | 用于制造多个芯片的方法和相应地制造的芯片 |
US12/677,068 US8405210B2 (en) | 2007-09-12 | 2008-07-24 | Method for producing a plurality of chips and a chip produced accordingly |
JP2010524430A JP2010538847A (ja) | 2007-09-12 | 2008-07-24 | 複数のチップの製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102007043526.8 | 2007-09-12 | ||
DE102007043526.8A DE102007043526B4 (de) | 2007-09-12 | 2007-09-12 | Verfahren zum Herstellen einer Vielzahl von Chips und entsprechend hergestellter Chip |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009033871A1 true WO2009033871A1 (de) | 2009-03-19 |
Family
ID=39942422
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2008/059688 WO2009033871A1 (de) | 2007-09-12 | 2008-07-24 | Verfahren zum herstellen einer vielzahl von chips und entsprechend hergestellter chip |
Country Status (7)
Country | Link |
---|---|
US (1) | US8405210B2 (de) |
EP (1) | EP2191503A1 (de) |
JP (1) | JP2010538847A (de) |
KR (1) | KR20100061469A (de) |
CN (1) | CN101803003A (de) |
DE (1) | DE102007043526B4 (de) |
WO (1) | WO2009033871A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102009027180A1 (de) | 2009-06-25 | 2010-12-30 | Robert Bosch Gmbh | Mikromechanisches Element sowie Verfahren zu dessen Herstelllung |
DE102009046081B4 (de) * | 2009-10-28 | 2021-08-26 | Robert Bosch Gmbh | Eutektische Bondung von Dünnchips auf einem Trägersubstrat |
CN103229290B (zh) | 2010-11-23 | 2016-10-05 | 罗伯特·博世有限公司 | 薄芯片在载体衬底上的低共熔压焊 |
WO2013162504A2 (en) | 2012-04-23 | 2013-10-31 | Apple Inc. | Methods and systems for forming a glass insert in an amorphous metal alloy bezel |
FR3009887B1 (fr) * | 2013-08-20 | 2015-09-25 | Commissariat Energie Atomique | Procede ameliore de separation entre une zone active d'un substrat et sa face arriere ou une portion de sa face arriere |
CN107238785B (zh) * | 2016-03-25 | 2020-12-29 | 联芯科技有限公司 | 芯片测试基座 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050087843A1 (en) * | 2003-10-27 | 2005-04-28 | Hubert Benzel | Method for dicing semiconductor chips and corresponding semiconductor chip system |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5950070A (en) * | 1997-05-15 | 1999-09-07 | Kulicke & Soffa Investments | Method of forming a chip scale package, and a tool used in forming the chip scale package |
US6429530B1 (en) * | 1998-11-02 | 2002-08-06 | International Business Machines Corporation | Miniaturized chip scale ball grid array semiconductor package |
US6656765B1 (en) * | 2000-02-02 | 2003-12-02 | Amkor Technology, Inc. | Fabricating very thin chip size semiconductor packages |
TW559960B (en) * | 2002-09-19 | 2003-11-01 | Siliconware Precision Industries Co Ltd | Fabrication method for ball grid array semiconductor package |
US7064010B2 (en) * | 2003-10-20 | 2006-06-20 | Micron Technology, Inc. | Methods of coating and singulating wafers |
JP4801337B2 (ja) * | 2004-09-21 | 2011-10-26 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
-
2007
- 2007-09-12 DE DE102007043526.8A patent/DE102007043526B4/de not_active Expired - Fee Related
-
2008
- 2008-07-24 EP EP08786380A patent/EP2191503A1/de not_active Withdrawn
- 2008-07-24 KR KR1020107005407A patent/KR20100061469A/ko not_active Application Discontinuation
- 2008-07-24 WO PCT/EP2008/059688 patent/WO2009033871A1/de active Application Filing
- 2008-07-24 CN CN200880106772A patent/CN101803003A/zh active Pending
- 2008-07-24 JP JP2010524430A patent/JP2010538847A/ja not_active Withdrawn
- 2008-07-24 US US12/677,068 patent/US8405210B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050087843A1 (en) * | 2003-10-27 | 2005-04-28 | Hubert Benzel | Method for dicing semiconductor chips and corresponding semiconductor chip system |
Also Published As
Publication number | Publication date |
---|---|
CN101803003A (zh) | 2010-08-11 |
DE102007043526B4 (de) | 2020-10-08 |
DE102007043526A1 (de) | 2009-03-19 |
JP2010538847A (ja) | 2010-12-16 |
US20100283147A1 (en) | 2010-11-11 |
US8405210B2 (en) | 2013-03-26 |
KR20100061469A (ko) | 2010-06-07 |
EP2191503A1 (de) | 2010-06-02 |
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