WO2009020023A1 - 出力調整方法、シリコンエピタキシャルウェーハの製造方法、及びサセプタ - Google Patents

出力調整方法、シリコンエピタキシャルウェーハの製造方法、及びサセプタ Download PDF

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Publication number
WO2009020023A1
WO2009020023A1 PCT/JP2008/063657 JP2008063657W WO2009020023A1 WO 2009020023 A1 WO2009020023 A1 WO 2009020023A1 JP 2008063657 W JP2008063657 W JP 2008063657W WO 2009020023 A1 WO2009020023 A1 WO 2009020023A1
Authority
WO
WIPO (PCT)
Prior art keywords
susceptor
epitaxial wafer
silicon substrate
silicon epitaxial
power adjusting
Prior art date
Application number
PCT/JP2008/063657
Other languages
English (en)
French (fr)
Inventor
Tsuyoshi Nishizawa
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Publication of WO2009020023A1 publication Critical patent/WO2009020023A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

第１サセプタ１３として、シリコン基板Ｗを載置する面に複数の凹部１３ｂが形成されたものを用い、シリコン基板Ｗの主表面のうち、凹部１３ｂに対応する位置に形成される凸状又は凹状の複数のエピタキシャル層の高さ又は深さ同士が略一定となるよう、加熱装置１７ａ，１７ｂの出力を調整する。これにより、シリコン基板とサセプタとの温度差をシリコン基板全面にわたり略均一にすることができる。
PCT/JP2008/063657 2007-08-03 2008-07-30 出力調整方法、シリコンエピタキシャルウェーハの製造方法、及びサセプタ WO2009020023A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-203049 2007-08-03
JP2007203049A JP2009038294A (ja) 2007-08-03 2007-08-03 出力調整方法、シリコンエピタキシャルウェーハの製造方法、及びサセプタ

Publications (1)

Publication Number Publication Date
WO2009020023A1 true WO2009020023A1 (ja) 2009-02-12

Family

ID=40341257

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/063657 WO2009020023A1 (ja) 2007-08-03 2008-07-30 出力調整方法、シリコンエピタキシャルウェーハの製造方法、及びサセプタ

Country Status (2)

Country Link
JP (1) JP2009038294A (ja)
WO (1) WO2009020023A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109791097A (zh) * 2017-07-18 2019-05-21 埃耶士株式会社 基板分析用管嘴及基板分析方法
EP3951027A4 (en) * 2019-03-29 2022-12-28 Kwansei Gakuin Educational Foundation SUBSTRATE PREPARATION DEVICE FOR LARGE DIAMETER SEMICONDUCTOR SUBSTRATES

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4978608B2 (ja) * 2008-10-17 2012-07-18 信越半導体株式会社 エピタキシャルウエーハの製造方法
JP5776090B2 (ja) * 2010-07-21 2015-09-09 株式会社 天谷製作所 成膜プロセス
KR102011146B1 (ko) * 2012-12-18 2019-08-14 에스케이실트론 주식회사 에피택셜 웨이퍼 제조장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001126995A (ja) * 1999-10-29 2001-05-11 Applied Materials Inc 半導体製造装置
JP2004200436A (ja) * 2002-12-19 2004-07-15 Toshiba Ceramics Co Ltd サセプタ及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001126995A (ja) * 1999-10-29 2001-05-11 Applied Materials Inc 半導体製造装置
JP2004200436A (ja) * 2002-12-19 2004-07-15 Toshiba Ceramics Co Ltd サセプタ及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109791097A (zh) * 2017-07-18 2019-05-21 埃耶士株式会社 基板分析用管嘴及基板分析方法
CN109791097B (zh) * 2017-07-18 2022-01-04 埃耶士株式会社 基板分析用管嘴及基板分析方法
EP3951027A4 (en) * 2019-03-29 2022-12-28 Kwansei Gakuin Educational Foundation SUBSTRATE PREPARATION DEVICE FOR LARGE DIAMETER SEMICONDUCTOR SUBSTRATES
US11955354B2 (en) 2019-03-29 2024-04-09 Kwansei Gakuin Educational Foundation Semiconductor substrate manufacturing device applicable to large-diameter semiconductor substrate

Also Published As

Publication number Publication date
JP2009038294A (ja) 2009-02-19

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