WO2009011303A1 - Ｓｉ層凝集抑制方法、半導体装置の製造方法及び真空処理装置 - Google Patents

Ｓｉ層凝集抑制方法、半導体装置の製造方法及び真空処理装置 Download PDF

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Publication number
WO2009011303A1
WO2009011303A1 PCT/JP2008/062569 JP2008062569W WO2009011303A1 WO 2009011303 A1 WO2009011303 A1 WO 2009011303A1 JP 2008062569 W JP2008062569 W JP 2008062569W WO 2009011303 A1 WO2009011303 A1 WO 2009011303A1
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WIPO (PCT)
Prior art keywords
layer
aggregation
soi substrate
heating
vacuum processing
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Ceased
Application number
PCT/JP2008/062569
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English (en)
French (fr)
Inventor
Junko Nakatsuru
Hiroki Date
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Canon Anelva Corp
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Canon Anelva Corp
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Publication date
Application filed by Canon Anelva Corp filed Critical Canon Anelva Corp
Priority to JP2009523630A priority Critical patent/JP4519947B2/ja
Publication of WO2009011303A1 publication Critical patent/WO2009011303A1/ja
Priority to US12/683,183 priority patent/US7919397B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0434—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0436—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0602—Temperature monitoring

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

ＳＯＩ基板の最表面の露出状態のＳｉ層を加熱昇温するとき、加熱昇温過程でのＳｉ層の凝集を防止でき、さらにＳＯＩ基板上に保護膜を形成することなく凝集を抑制することができるＳＯＩ基板のＳｉ層凝集抑制方法を提供する。このＳＯＩ基板のＳｉ層凝集抑制方法は、Ｓｉ基板３１上に絶縁層３２とＳｉ層３３が順次積層されて成るＳＯＩ基板２７で、露出状態にあるＳｉ層を加熱昇温するとき、加熱昇温過程で水素化物ガスを供給する方法である。この方法では、Ｓｉ層が凝集する前に、凝集前の温度で水素化物ガスが解離してＳｉ層のダングリングボンド４１をＨ等の所定原子で終端させる。
PCT/JP2008/062569 2007-07-13 2008-07-11 Ｓｉ層凝集抑制方法、半導体装置の製造方法及び真空処理装置 Ceased WO2009011303A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009523630A JP4519947B2 (ja) 2007-07-13 2008-07-11 Ｓｉ層凝集抑制方法、半導体装置の製造方法及び真空処理装置
US12/683,183 US7919397B2 (en) 2007-07-13 2010-01-06 Method for reducing agglomeration of Si layer, method for manufacturing semiconductor device and vacuum treatment apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007184043 2007-07-13
JP2007-184043 2007-07-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/683,183 Continuation US7919397B2 (en) 2007-07-13 2010-01-06 Method for reducing agglomeration of Si layer, method for manufacturing semiconductor device and vacuum treatment apparatus

Publications (1)

Publication Number Publication Date
WO2009011303A1 true WO2009011303A1 (ja) 2009-01-22

Family

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PCT/JP2008/062569 Ceased WO2009011303A1 (ja) 2007-07-13 2008-07-11 Ｓｉ層凝集抑制方法、半導体装置の製造方法及び真空処理装置

Country Status (3)

Country Link
US (1) US7919397B2 (ja)
JP (2) JP4519947B2 (ja)
WO (1) WO2009011303A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018520510A (ja) * 2015-06-01 2018-07-26 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ シリコンゲルマニウム・オン・インシュレータの製造方法
JP2019145735A (ja) * 2018-02-23 2019-08-29 東京エレクトロン株式会社 シリコン膜またはゲルマニウム膜またはシリコンゲルマニウム膜を成膜する方法および装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8664741B2 (en) 2011-06-14 2014-03-04 Taiwan Semiconductor Manufacturing Company Ltd. High voltage resistor with pin diode isolation
JP5569831B1 (ja) * 2013-05-15 2014-08-13 国立大学法人東北大学 マイクロ空室の内壁面処理方法
JP6240440B2 (ja) * 2013-08-30 2017-11-29 東京応化工業株式会社 チャンバー装置及び加熱方法
CN110890303A (zh) * 2019-11-18 2020-03-17 华虹半导体(无锡)有限公司 抗腐蚀传送装置、传送装置的抗腐蚀方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855842A (ja) * 1994-03-31 1996-02-27 Applied Materials Inc 裏面を被覆したサセプタを有する半導体ウエ−ハ処理チャンバ
JPH08100264A (ja) * 1994-09-30 1996-04-16 Nec Corp 薄膜の形成方法およびその装置
JPH1041321A (ja) * 1996-07-26 1998-02-13 Sony Corp バイポーラトランジスタの製造方法
JP2001244469A (ja) * 2000-03-02 2001-09-07 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002353426A (ja) * 2001-05-29 2002-12-06 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2007096137A (ja) * 2005-09-29 2007-04-12 Denso Corp 半導体基板の製造方法およびエピタキシャル成長装置

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JP2000349081A (ja) * 1999-06-07 2000-12-15 Sony Corp 酸化膜形成方法
DE102006045912B4 (de) 2005-09-29 2011-07-21 Sumco Corp. Verfahren zur Fertigung einer Halbleitervorrichtung und Epitaxialwachstumseinrichtung

Patent Citations (6)

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JPH0855842A (ja) * 1994-03-31 1996-02-27 Applied Materials Inc 裏面を被覆したサセプタを有する半導体ウエ−ハ処理チャンバ
JPH08100264A (ja) * 1994-09-30 1996-04-16 Nec Corp 薄膜の形成方法およびその装置
JPH1041321A (ja) * 1996-07-26 1998-02-13 Sony Corp バイポーラトランジスタの製造方法
JP2001244469A (ja) * 2000-03-02 2001-09-07 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002353426A (ja) * 2001-05-29 2002-12-06 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP2007096137A (ja) * 2005-09-29 2007-04-12 Denso Corp 半導体基板の製造方法およびエピタキシャル成長装置

Non-Patent Citations (1)

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Title
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018520510A (ja) * 2015-06-01 2018-07-26 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ シリコンゲルマニウム・オン・インシュレータの製造方法
JP2019195066A (ja) * 2015-06-01 2019-11-07 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層構造体
JP2019145735A (ja) * 2018-02-23 2019-08-29 東京エレクトロン株式会社 シリコン膜またはゲルマニウム膜またはシリコンゲルマニウム膜を成膜する方法および装置

Also Published As

Publication number Publication date
JP4519947B2 (ja) 2010-08-04
JPWO2009011303A1 (ja) 2010-09-24
JP2010135808A (ja) 2010-06-17
US20100144127A1 (en) 2010-06-10
US7919397B2 (en) 2011-04-05

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