WO2008155806A1 - Procédé et dispositif de synchronisation par barrière et processeur multicœur - Google Patents

Procédé et dispositif de synchronisation par barrière et processeur multicœur Download PDF

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Publication number
WO2008155806A1
WO2008155806A1 PCT/JP2007/000664 JP2007000664W WO2008155806A1 WO 2008155806 A1 WO2008155806 A1 WO 2008155806A1 JP 2007000664 W JP2007000664 W JP 2007000664W WO 2008155806 A1 WO2008155806 A1 WO 2008155806A1
Authority
WO
WIPO (PCT)
Prior art keywords
barrier synchronization
multicore processor
processor
processor cores
multicore
Prior art date
Application number
PCT/JP2007/000664
Other languages
English (en)
Japanese (ja)
Inventor
Hideyuki Unno
Masaki Ukai
Matthew Depetro
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000664 priority Critical patent/WO2008155806A1/fr
Priority to EP07790190.8A priority patent/EP2159694B1/fr
Priority to JP2009520147A priority patent/JP5273045B2/ja
Publication of WO2008155806A1 publication Critical patent/WO2008155806A1/fr
Priority to US12/638,746 priority patent/US7971029B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/522—Barrier synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

Sur un processeur multicœur ayant une pluralité de cœurs de processeur, un dispositif de synchronisation par barrière est installé de façon à effectuer une synchronisation par barrière de deux processeurs multicœur ou plus appartenant au même groupe de synchronisation parmi cette pluralité de cœurs de processeur. Lorsque deux cœurs de processeur ou plus sur le processeur multicœur appartiennent uniquement au même groupe de synchronisation, la synchronisation par barrière de ces cœurs de processeur est exécutée à l'aide du dispositif de synchronisation par barrières qui est installé.
PCT/JP2007/000664 2007-06-20 2007-06-20 Procédé et dispositif de synchronisation par barrière et processeur multicœur WO2008155806A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/000664 WO2008155806A1 (fr) 2007-06-20 2007-06-20 Procédé et dispositif de synchronisation par barrière et processeur multicœur
EP07790190.8A EP2159694B1 (fr) 2007-06-20 2007-06-20 Procédé et dispositif de synchronisation par barrière et processeur multic ur
JP2009520147A JP5273045B2 (ja) 2007-06-20 2007-06-20 バリア同期方法、装置、及びプロセッサ
US12/638,746 US7971029B2 (en) 2007-06-20 2009-12-15 Barrier synchronization method, device, and multi-core processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000664 WO2008155806A1 (fr) 2007-06-20 2007-06-20 Procédé et dispositif de synchronisation par barrière et processeur multicœur

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/638,746 Continuation US7971029B2 (en) 2007-06-20 2009-12-15 Barrier synchronization method, device, and multi-core processor

Publications (1)

Publication Number Publication Date
WO2008155806A1 true WO2008155806A1 (fr) 2008-12-24

Family

ID=40155971

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000664 WO2008155806A1 (fr) 2007-06-20 2007-06-20 Procédé et dispositif de synchronisation par barrière et processeur multicœur

Country Status (4)

Country Link
US (1) US7971029B2 (fr)
EP (1) EP2159694B1 (fr)
JP (1) JP5273045B2 (fr)
WO (1) WO2008155806A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011039666A (ja) * 2009-08-07 2011-02-24 Hitachi Ltd バリア同期方法及び計算機
WO2012127534A1 (fr) * 2011-03-23 2012-09-27 富士通株式会社 Procédé de synchronisation de barrières, dispositif de synchronisation de barrières et dispositif de traitement
JP2014021820A (ja) * 2012-07-20 2014-02-03 Fujitsu Ltd 情報処理装置およびバリア同期方法
JP2017016250A (ja) * 2015-06-29 2017-01-19 日本電気株式会社 バリア同期装置、バリア同期方法及びプログラム
US10503512B2 (en) 2014-11-13 2019-12-10 Arm Limited Context sensitive barriers with an implicit access ordering constraint for a victim context

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US8214662B2 (en) * 2007-04-09 2012-07-03 Panasonic Corporation Multiprocessor control unit, control method performed by the same, and integrated circuit
JP5549574B2 (ja) * 2010-12-17 2014-07-16 富士通株式会社 並列計算機システム、同期装置、並列計算機システムの制御方法
DE102011084569B4 (de) * 2011-10-14 2019-02-21 Continental Automotive Gmbh Verfahren zum Betreiben eines informationstechnischen Systems und informationstechnisches System
US9092272B2 (en) 2011-12-08 2015-07-28 International Business Machines Corporation Preparing parallel tasks to use a synchronization register
FR3021433B1 (fr) * 2014-05-21 2016-06-24 Kalray Systeme de synchronisation inter-processeurs
US10042580B2 (en) 2015-11-05 2018-08-07 International Business Machines Corporation Speculatively performing memory move requests with respect to a barrier
US9996298B2 (en) 2015-11-05 2018-06-12 International Business Machines Corporation Memory move instruction sequence enabling software control
US10241945B2 (en) 2015-11-05 2019-03-26 International Business Machines Corporation Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions
US10152322B2 (en) 2015-11-05 2018-12-11 International Business Machines Corporation Memory move instruction sequence including a stream of copy-type and paste-type instructions
US10140052B2 (en) 2015-11-05 2018-11-27 International Business Machines Corporation Memory access in a data processing system utilizing copy and paste instructions
US10346164B2 (en) 2015-11-05 2019-07-09 International Business Machines Corporation Memory move instruction sequence targeting an accelerator switchboard
US10067713B2 (en) 2015-11-05 2018-09-04 International Business Machines Corporation Efficient enforcement of barriers with respect to memory move sequences
US10126952B2 (en) 2015-11-05 2018-11-13 International Business Machines Corporation Memory move instruction sequence targeting a memory-mapped device
US10318355B2 (en) * 2017-01-24 2019-06-11 Oracle International Corporation Distributed graph processing system featuring interactive remote control mechanism including task cancellation
US11353868B2 (en) * 2017-04-24 2022-06-07 Intel Corporation Barriers and synchronization for machine learning at autonomous machines
US10509452B2 (en) * 2017-04-26 2019-12-17 Advanced Micro Devices, Inc. Hierarchical power distribution in large scale computing systems
US11461130B2 (en) 2020-05-26 2022-10-04 Oracle International Corporation Methodology for fast and seamless task cancelation and error handling in distributed processing of large graph data
GB2597078B (en) * 2020-07-14 2022-07-13 Graphcore Ltd Communication between host and accelerator over network

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JPH02144657A (ja) * 1988-11-26 1990-06-04 Hitachi Ltd 並列演算処理装置
JPH08187303A (ja) 1995-01-10 1996-07-23 Toyoda Gosei Co Ltd トレーニング装置
JPH096734A (ja) 1995-06-21 1997-01-10 Nec Corp バリア同期装置
JPH10240549A (ja) * 1997-02-24 1998-09-11 Hitachi Ltd 並列ジョブ多重スケジューリング方法及び装置
JP2005071109A (ja) 2003-08-25 2005-03-17 Hitachi Ltd マルチプロセッサシステムの同期方法
JP2005316679A (ja) * 2004-04-28 2005-11-10 Nec Corp 並列演算処理装置
US20060212868A1 (en) 2005-03-15 2006-09-21 Koichi Takayama Synchronization method and program for a parallel computer

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JP3285629B2 (ja) 1992-12-18 2002-05-27 富士通株式会社 同期処理方法及び同期処理装置
US5940856A (en) * 1997-04-14 1999-08-17 International Business Machines Corporation Cache intervention from only one of many cache lines sharing an unmodified value
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US7340565B2 (en) * 2004-01-13 2008-03-04 Hewlett-Packard Development Company, L.P. Source request arbitration
US7277989B2 (en) * 2004-06-22 2007-10-02 Sun Microsystems, Inc. Selectively performing fetches for store operations during speculative execution
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US7356653B2 (en) * 2005-06-03 2008-04-08 International Business Machines Corporation Reader-initiated shared memory synchronization

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JPH02144657A (ja) * 1988-11-26 1990-06-04 Hitachi Ltd 並列演算処理装置
JPH08187303A (ja) 1995-01-10 1996-07-23 Toyoda Gosei Co Ltd トレーニング装置
JPH096734A (ja) 1995-06-21 1997-01-10 Nec Corp バリア同期装置
JPH10240549A (ja) * 1997-02-24 1998-09-11 Hitachi Ltd 並列ジョブ多重スケジューリング方法及び装置
JP2005071109A (ja) 2003-08-25 2005-03-17 Hitachi Ltd マルチプロセッサシステムの同期方法
JP2005316679A (ja) * 2004-04-28 2005-11-10 Nec Corp 並列演算処理装置
US20060212868A1 (en) 2005-03-15 2006-09-21 Koichi Takayama Synchronization method and program for a parallel computer
JP2006259821A (ja) * 2005-03-15 2006-09-28 Hitachi Ltd 並列計算機の同期方法及びプログラム

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Title
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011039666A (ja) * 2009-08-07 2011-02-24 Hitachi Ltd バリア同期方法及び計算機
WO2012127534A1 (fr) * 2011-03-23 2012-09-27 富士通株式会社 Procédé de synchronisation de barrières, dispositif de synchronisation de barrières et dispositif de traitement
JP2014021820A (ja) * 2012-07-20 2014-02-03 Fujitsu Ltd 情報処理装置およびバリア同期方法
US9336064B2 (en) 2012-07-20 2016-05-10 Fujitsu Limited Information processing device and barrier synchronization method
US9436520B2 (en) 2012-07-20 2016-09-06 Fujitsu Limited Information processing device and barrier synchronization method
US10503512B2 (en) 2014-11-13 2019-12-10 Arm Limited Context sensitive barriers with an implicit access ordering constraint for a victim context
JP2017016250A (ja) * 2015-06-29 2017-01-19 日本電気株式会社 バリア同期装置、バリア同期方法及びプログラム

Also Published As

Publication number Publication date
EP2159694B1 (fr) 2019-03-27
US20100095090A1 (en) 2010-04-15
JP5273045B2 (ja) 2013-08-28
US7971029B2 (en) 2011-06-28
EP2159694A4 (fr) 2012-12-26
EP2159694A1 (fr) 2010-03-03
JPWO2008155806A1 (ja) 2010-08-26

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