WO2008153057A1 - マルチプロセッサシステム及びその制御方法 - Google Patents

マルチプロセッサシステム及びその制御方法 Download PDF

Info

Publication number
WO2008153057A1
WO2008153057A1 PCT/JP2008/060683 JP2008060683W WO2008153057A1 WO 2008153057 A1 WO2008153057 A1 WO 2008153057A1 JP 2008060683 W JP2008060683 W JP 2008060683W WO 2008153057 A1 WO2008153057 A1 WO 2008153057A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
multiprocessor system
control method
allocated
control
Prior art date
Application number
PCT/JP2008/060683
Other languages
English (en)
French (fr)
Inventor
Takashi Inoue
Takeshi Inoguchi
Original Assignee
Toyota Jidosha Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Jidosha Kabushiki Kaisha filed Critical Toyota Jidosha Kabushiki Kaisha
Priority to CN200880019342A priority Critical patent/CN101681286A/zh
Priority to US12/598,989 priority patent/US8090982B2/en
Priority to DE112008001528.7T priority patent/DE112008001528B4/de
Publication of WO2008153057A1 publication Critical patent/WO2008153057A1/ja

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)
  • Safety Devices In Control Systems (AREA)
  • Multi Processors (AREA)

Abstract

　担当すべき制御がそれぞれに割り当てられた複数のプロセッサコア０，１，２，３を有する、マルチプロセッサシステムであって、プロセッサコア１，２，３より優先度の高い制御が割り当てられたプロセッサコア０で発生した異常を検出する監視プロセッサ２０を備え、プロセッサコア０以外のプロセッサコア１，２，３のいずれかに、監視プロセッサ２０によって異常が検出されたプロセッサコア０に割り当てられていた制御を代替させることを特徴とする、マルチプロセッサシステム。
PCT/JP2008/060683 2007-06-11 2008-06-11 マルチプロセッサシステム及びその制御方法 WO2008153057A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200880019342A CN101681286A (zh) 2007-06-11 2008-06-11 多处理器系统及其控制方法
US12/598,989 US8090982B2 (en) 2007-06-11 2008-06-11 Multiprocessor system enabling controlling with specific processor under abnormal operation and control method thereof
DE112008001528.7T DE112008001528B4 (de) 2007-06-11 2008-06-11 Multiprozessorsystem und Steuerverfahren hierfür

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007154050A JP4458119B2 (ja) 2007-06-11 2007-06-11 マルチプロセッサシステム及びその制御方法
JP2007-154050 2007-06-11

Publications (1)

Publication Number Publication Date
WO2008153057A1 true WO2008153057A1 (ja) 2008-12-18

Family

ID=40129662

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060683 WO2008153057A1 (ja) 2007-06-11 2008-06-11 マルチプロセッサシステム及びその制御方法

Country Status (5)

Country Link
US (1) US8090982B2 (ja)
JP (1) JP4458119B2 (ja)
CN (1) CN101681286A (ja)
DE (1) DE112008001528B4 (ja)
WO (1) WO2008153057A1 (ja)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4433006B2 (ja) * 2007-07-04 2010-03-17 株式会社デンソー マルチコアの異常監視装置
JP5641384B2 (ja) 2008-11-28 2014-12-17 独立行政法人物質・材料研究機構 表示装置用照明装置及び表示装置
US8381026B2 (en) * 2009-06-22 2013-02-19 Citrix Systems, Inc. Systems and method for transaction stall detection and propagating the result in a multi-core architecture
US8782469B2 (en) * 2009-09-01 2014-07-15 Hitachi, Ltd. Request processing system provided with multi-core processor
JP2011065645A (ja) 2009-09-18 2011-03-31 Square Enix Co Ltd マルチコアプロセッサシステム
JP2011065528A (ja) * 2009-09-18 2011-03-31 Toyota Motor Corp マルチプロセッサシステム
WO2011117156A2 (de) * 2010-03-23 2011-09-29 Continental Teves Ag & Co. Ohg Kontrollrechnersystem, verfahren zur steuerung eines kontrollrechnersystems, sowie verwendung eines kontrollrechnersystems
JP5601127B2 (ja) * 2010-09-28 2014-10-08 株式会社デンソー 制御装置
JP2012083992A (ja) * 2010-10-13 2012-04-26 Nec Computertechno Ltd データ障害処理装置、及びデータ障害処理方法
JP5644380B2 (ja) * 2010-11-04 2014-12-24 トヨタ自動車株式会社 情報処理装置
EP2672342B1 (en) * 2011-01-31 2017-03-01 Toyota Jidosha Kabushiki Kaisha Safety control device and safety control method
DE102011011755A1 (de) * 2011-02-18 2012-08-23 Conti Temic Microelectronic Gmbh Halbleiterschaltkreis und Verfahren in einem Sicherheitskonzept zum Einsatz in einem Kraftfahrzeug
DE102011005766A1 (de) * 2011-03-18 2012-09-20 Zf Friedrichshafen Ag Steuergerät für ein Kraftfahrzeug
EP2690558B1 (en) * 2011-03-24 2020-01-22 Renesas Electronics Corporation Semiconductor device
JP5533789B2 (ja) 2011-06-14 2014-06-25 株式会社デンソー 車載電子制御装置
DE102011105617A1 (de) * 2011-06-28 2013-01-03 Audi Ag Kraftfahrzeug mit einer Vielzahl von Betriebskomponenten
DE102011116617A1 (de) * 2011-10-20 2013-04-25 Continental Automotive Gmbh Kraftfahrzeugsteuergerät mit einem Doppelkernprozessor
US8949663B2 (en) 2011-12-13 2015-02-03 Toyota Jidosha Kabushiki Kaisha Multi-core processor including a monitored processor core whose process result is to be monitored by a number of processors based on processing load
JP2013225208A (ja) * 2012-04-20 2013-10-31 Toyota Motor Corp 情報処理装置、情報処理方法、及びプログラム
WO2014060470A1 (de) * 2012-10-16 2014-04-24 Continental Teves Ag & Co. Ohg Schnittstelle zum datenaustausch zwischen redundant ausgeführten programmen zur kraftfahrzeugsteuerung
CN103902423A (zh) * 2012-12-26 2014-07-02 联芯科技有限公司 一种调试中央处理器死机的方法和系统
CN104657240B (zh) * 2013-11-18 2018-08-21 华为技术有限公司 多内核操作系统的失效控制方法及装置
US9817670B2 (en) 2013-12-13 2017-11-14 International Business Machines Corporation Framework to provide time bound execution of co-processor commands
CN103870350A (zh) * 2014-03-27 2014-06-18 浪潮电子信息产业股份有限公司 一种基于watchdog的微处理器多核加固方法
JP6165677B2 (ja) * 2014-06-06 2017-07-19 本田技研工業株式会社 電子制御システム
DE102015211837A1 (de) * 2015-06-25 2016-12-29 Volkswagen Aktiengesellschaft Integrierter Baustein mit einem Steuergeräte-Controller und einer Überwachungseinheit
JP5985121B1 (ja) 2015-07-30 2016-09-06 三菱電機株式会社 プログラム実行装置及びプログラム実行システム及びプログラム実行方法
JP2017033236A (ja) * 2015-07-31 2017-02-09 日立オートモティブシステムズ株式会社 車両制御装置
JP2017097633A (ja) * 2015-11-25 2017-06-01 日立オートモティブシステムズ株式会社 車両制御装置
JP2018096273A (ja) * 2016-12-13 2018-06-21 株式会社デンソー 電子制御装置
JP6960453B2 (ja) * 2017-04-25 2021-11-05 株式会社日立製作所 再構成制御装置
KR101988558B1 (ko) 2017-06-07 2019-06-12 현대오트론 주식회사 멀티 코어를 갖는 마이크로콘트롤러 유닛을 감시하는 감시장치 및 그것의 동작 방법
JP7449650B2 (ja) * 2019-05-23 2024-03-14 株式会社デンソー 車両用装置
CN112527541A (zh) * 2019-09-19 2021-03-19 华为技术有限公司 一种确定多核处理器中故障计算核的方法及电子设备
JP7397655B2 (ja) * 2019-12-19 2023-12-13 日立Astemo株式会社 自動車用電子制御装置
JP6998434B2 (ja) * 2020-09-04 2022-01-18 日立Astemo株式会社 自動車用電子制御装置
DE112021005649T5 (de) * 2021-03-22 2023-10-05 Hitachi Astemo, Ltd. Fahrzeugsteuervorrichtung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001506789A (ja) * 1996-12-16 2001-05-22 マイクロソフト コーポレイション フォールト・レジリエント自動車制御システム
JP2002049405A (ja) * 2001-06-01 2002-02-15 Hitachi Ltd 分散制御装置、システム及びコントローラ
JP2002259147A (ja) * 2001-02-27 2002-09-13 Hitachi Ltd 情報処理装置及びリアルタイム分散処理システム

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1344474A (en) * 1971-03-04 1974-01-23 Plessey Co Ltd Fault detection and handling arrangements for use in data proces sing systems
US4330826A (en) * 1980-02-05 1982-05-18 The Bendix Corporation Synchronizer and synchronization system for a multiple computer system
JPH0424838A (ja) 1990-05-21 1992-01-28 Fuji Xerox Co Ltd マルチプロセッサの障害管理方式
JPH04223534A (ja) 1990-12-26 1992-08-13 Nec Field Service Ltd 情報処理システム
JPH0630069A (ja) 1992-07-13 1994-02-04 Nec Corp マルチサブキャリアによるｑａｍ伝送方式
JP3070282B2 (ja) 1992-08-18 2000-07-31 日本電気株式会社 障害処理方式
JPH07175765A (ja) 1993-10-25 1995-07-14 Mitsubishi Electric Corp 計算機の障害回復方法
JP3345626B2 (ja) * 1994-09-29 2002-11-18 富士通株式会社 マルチプロセッサシステムにおけるプロセッサ異常対策装置およびマルチプロセッサシステムにおけるプロセッサ異常対策方法
JP4113934B2 (ja) 1998-07-09 2008-07-09 株式会社豊田中央研究所 フェールセーフ機能付き情報処理装置
JP2000181890A (ja) 1998-12-15 2000-06-30 Fujitsu Ltd マルチプロセッサ交換機及びその主プロセッサ切替方法
US6622260B1 (en) * 1999-12-30 2003-09-16 Suresh Marisetty System abstraction layer, processor abstraction layer, and operating system error handling
DE10101827A1 (de) * 2001-01-17 2002-07-18 Daimler Chrysler Ag Lenkanordnung für Kraftfahrzeuge
JP2003036174A (ja) * 2001-07-25 2003-02-07 Hitachi Ltd 車載端末装置
US6990320B2 (en) * 2002-02-26 2006-01-24 Motorola, Inc. Dynamic reallocation of processing resources for redundant functionality
JP2004318498A (ja) 2003-04-16 2004-11-11 Toyota Central Res & Dev Lab Inc フェールセーフ装置
US7275180B2 (en) * 2003-04-17 2007-09-25 International Business Machines Corporation Transparent replacement of a failing processor
DE102004005128B3 (de) * 2004-02-02 2005-01-05 Fujitsu Siemens Computers Gmbh Anordnung mehrerer Rechner und Verfahren zum Betreiben einer Anordnung mehrerer Rechner bei einem Rechnerausfall
US7426657B2 (en) * 2004-07-09 2008-09-16 International Business Machines Corporation System and method for predictive processor failure recovery
US20060015773A1 (en) * 2004-07-16 2006-01-19 Dell Products L.P. System and method for failure recovery and load balancing in a cluster network
DE102004046288A1 (de) * 2004-09-24 2006-03-30 Robert Bosch Gmbh Verfahren zur Abarbeitung eines Computerprogramms auf einem Computersystem
JP2006139621A (ja) * 2004-11-12 2006-06-01 Nec Electronics Corp マルチプロセッシングシステム及びマルチプロセッシング方法
JP4422596B2 (ja) 2004-11-29 2010-02-24 トヨタ自動車株式会社 再構成可能信号処理システム
JP2006277278A (ja) 2005-03-29 2006-10-12 Nec Corp 自律型コンピュータシステムおよびその自動整合方法
DE102005033463B3 (de) 2005-07-18 2007-02-01 Siemens Ag Piezoaktor
US7493515B2 (en) * 2005-09-30 2009-02-17 International Business Machines Corporation Assigning a processor to a logical partition
JP2007154050A (ja) 2005-12-06 2007-06-21 Hyogo Prefecture 機能性を付与するためのプラスチック表面処理法
US8819483B2 (en) * 2006-09-27 2014-08-26 L-3 Communications Corporation Computing device with redundant, dissimilar operating systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001506789A (ja) * 1996-12-16 2001-05-22 マイクロソフト コーポレイション フォールト・レジリエント自動車制御システム
JP2002259147A (ja) * 2001-02-27 2002-09-13 Hitachi Ltd 情報処理装置及びリアルタイム分散処理システム
JP2002049405A (ja) * 2001-06-01 2002-02-15 Hitachi Ltd 分散制御装置、システム及びコントローラ

Also Published As

Publication number Publication date
DE112008001528T5 (de) 2010-04-29
US20100162042A1 (en) 2010-06-24
CN101681286A (zh) 2010-03-24
US8090982B2 (en) 2012-01-03
JP2008305317A (ja) 2008-12-18
JP4458119B2 (ja) 2010-04-28
DE112008001528B4 (de) 2020-11-19

Similar Documents

Publication Publication Date Title
WO2008153057A1 (ja) マルチプロセッサシステム及びその制御方法
WO2008021414A3 (en) Event-based bandwidth allocation mode switching method and apparatus
WO2007136446A3 (en) Device social-control system
GB2485683A (en) Thread shift: Allocating threads to cores
EP2239662A3 (en) System management mode inter-processor interrupt redirection
WO2012170214A3 (en) System and apparatus for modeling processor workloads using virtual pulse chains
WO2011031357A8 (en) Mapping of computer threads onto heterogeneous resources
EP2465250A4 (en) System, method, computer program for multidirectional pathway selection
EP1998269A4 (en) PROGRAM EXECUTION MONITORING SYSTEM, EXECUTION MONITORING METHOD, COMPUTER CONTROL PROGRAM
GB2520852A (en) Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
WO2013089782A3 (en) Co-location electrical architecture
SG184226A1 (en) System and method for coordinating simultaneous edits of shared digital data
WO2009120981A3 (en) Vector instructions to enable efficient synchronization and parallel reduction operations
EP2738478A3 (en) Intelligent comfort management using natural language processing to interface with a comfort system controller
WO2007067562A3 (en) Methods and apparatus for multi-core processing with dedicated thread management
WO2010036656A3 (en) Directing data units to a core supporting tasks
WO2007078913A3 (en) Cross-architecture execution optimization
WO2014116299A3 (en) Systems and methods for mirroring virtual functions in a chassis configured to receive a plurality of modular information handling systems and a plurality of modular information handling resources
WO2012087587A3 (en) Apparatus, method, and system for early deep sleep state exit of a processing element
WO2008084535A1 (ja) ケーブル曲線生成システム、方法、及びプログラム
WO2008045809A3 (en) Network interface techniques
GB2492739A (en) Evaluating capability of a system to perform a task by comparing models of the system and the task
WO2008085648A3 (en) Selective guarded memory access on a per-instruction basis
WO2014024080A3 (en) Providing service address space for diagnostics collection
WO2013013335A8 (en) Automated document composition using clusters

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880019342.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08765462

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 12598989

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 1120080015287

Country of ref document: DE

RET De translation (de og part 6b)

Ref document number: 112008001528

Country of ref document: DE

Date of ref document: 20100429

Kind code of ref document: P

122 Ep: pct application non-entry in european phase

Ref document number: 08765462

Country of ref document: EP

Kind code of ref document: A1