WO2008152944A1 - Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ - Google Patents

Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ Download PDF

Info

Publication number
WO2008152944A1
WO2008152944A1 PCT/JP2008/060206 JP2008060206W WO2008152944A1 WO 2008152944 A1 WO2008152944 A1 WO 2008152944A1 JP 2008060206 W JP2008060206 W JP 2008060206W WO 2008152944 A1 WO2008152944 A1 WO 2008152944A1
Authority
WO
WIPO (PCT)
Prior art keywords
group iii
iii nitride
nitride semiconductor
emitting device
semiconductor light
Prior art date
Application number
PCT/JP2008/060206
Other languages
English (en)
French (fr)
Inventor
Kenzo Hanawa
Yasumasa Sasaki
Hisayuki Miki
Original Assignee
Showa Denko K.K.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko K.K. filed Critical Showa Denko K.K.
Priority to US12/438,047 priority Critical patent/US8097482B2/en
Publication of WO2008152944A1 publication Critical patent/WO2008152944A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Led Device Packages (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

　本発明のＩＩＩ族窒化物半導体の製造方法は、チャンバ内に基板及びターゲットを配置し、前記基板上にＭｇがドープされたＩＩＩ族窒化物半導体を反応性スパッタ法によって形成するスパッタ工程を備え、前記スパッタ工程は、Ｍｇをドープして半導体薄膜を成膜する成膜工程と、該成膜工程で成膜された半導体薄膜に対して不活性ガスプラズマによる処理を行うプラズマ処理工程の各小工程を含み、前記成膜工程と前記プラズマ処理工程とを交互に繰り返して前記半導体薄膜を積層することにより、ＩＩＩ族窒化物半導体を形成する。
PCT/JP2008/060206 2007-06-11 2008-06-03 Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ WO2008152944A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/438,047 US8097482B2 (en) 2007-06-11 2008-06-03 Method for manufacturing group III nitride semiconductor, method for manufacturing group III nitride semiconductor light-emitting device, group III nitride semiconductor light-emitting device, and lamp

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-154015 2007-06-11
JP2007154015A JP5049659B2 (ja) 2007-06-11 2007-06-11 Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ

Publications (1)

Publication Number Publication Date
WO2008152944A1 true WO2008152944A1 (ja) 2008-12-18

Family

ID=40129554

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/060206 WO2008152944A1 (ja) 2007-06-11 2008-06-03 Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ

Country Status (3)

Country Link
US (1) US8097482B2 (ja)
JP (1) JP5049659B2 (ja)
WO (1) WO2008152944A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012212880A (ja) * 2011-03-23 2012-11-01 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2016066804A (ja) * 2009-11-13 2016-04-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US11713516B2 (en) 2020-06-12 2023-08-01 Panasonic Holdings Corporation Group III nitride crystal, group III nitride substrate, and method of manufacturing group III nitride crystal

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5272390B2 (ja) * 2007-11-29 2013-08-28 豊田合成株式会社 Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
EP2273536B1 (en) * 2008-03-13 2013-10-30 Toyoda Gosei Co., Ltd. Group iii nitride semiconductor device and method for manufacturing the same, group iii nitride semiconductor light-emitting device and method for manufacturing the same, and lamp
JP5361925B2 (ja) * 2011-03-08 2013-12-04 株式会社東芝 半導体発光素子およびその製造方法
JP6054620B2 (ja) * 2012-03-29 2016-12-27 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法
DE112014001272B4 (de) * 2013-03-14 2023-03-30 Canon Anelva Corporation Schichtbildungsverfahren, Verfahren zum Herstellen einer lichtemittierenden Halbleitereinrichtung,lichtemittierende Halbleitereinrichtung und Beleuchtungseinrichtung
JP2014229812A (ja) * 2013-05-24 2014-12-08 住友電気工業株式会社 窒化物半導体発光素子
CN115064621A (zh) 2015-09-11 2022-09-16 国立大学法人三重大学 氮化物半导体衬底的制造方法、氮化物半导体衬底以及其加热装置
US11162189B2 (en) * 2018-03-02 2021-11-02 Dexerials Corporation Semiconductor substrate, gallium nitride single crystal, and method for producing gallium nitride single crystal
CN111628018B (zh) * 2020-06-28 2022-02-08 中国科学院长春光学精密机械与物理研究所 一种Ga2O3紫外探测器及其制备方法
WO2023074374A1 (ja) * 2021-10-28 2023-05-04 株式会社ジャパンディスプレイ 積層構造体及び窒化ガリウム系半導体デバイス
CN114267756B (zh) * 2021-12-20 2024-09-10 江西兆驰半导体有限公司 一种发光二极管外延片制备方法及外延片
WO2024024268A1 (ja) * 2022-07-25 2024-02-01 株式会社ジャパンディスプレイ 成膜装置
CN117604471B (zh) * 2023-11-22 2024-08-27 松山湖材料实验室 一种硅基氮化铝复合衬底及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263749A (ja) * 1994-03-22 1995-10-13 Toyoda Gosei Co Ltd ３族窒化物半導体の製造方法
JPH08181073A (ja) * 1994-12-21 1996-07-12 Canon Inc 半導体ウエハ及び結晶成長方法
JP2000216164A (ja) * 1998-09-09 2000-08-04 Matsushita Electronics Industry Corp 半導体装置の製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039819A (ja) 1983-08-12 1985-03-01 Nippon Telegr & Teleph Corp <Ntt> 化合物半導体薄膜の作製方法
JPS60173829A (ja) 1984-02-14 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> 化合物半導体薄膜の成長方法
US5091018A (en) * 1989-04-17 1992-02-25 The Boeing Company Tandem photovoltaic solar cell with III-V diffused junction booster cell
JP3773282B2 (ja) 1995-03-27 2006-05-10 豊田合成株式会社 窒化ガリウム系化合物半導体の電極形成方法
JP3688843B2 (ja) * 1996-09-06 2005-08-31 株式会社東芝 窒化物系半導体素子の製造方法
JP3700492B2 (ja) 1999-09-21 2005-09-28 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子
US6713789B1 (en) 1999-03-31 2004-03-30 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device and method of producing the same
JP3440873B2 (ja) 1999-03-31 2003-08-25 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子の製造方法
JP3994623B2 (ja) * 2000-04-21 2007-10-24 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子の製造方法
JP4710139B2 (ja) * 2001-01-15 2011-06-29 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体素子
US7217882B2 (en) * 2002-05-24 2007-05-15 Cornell Research Foundation, Inc. Broad spectrum solar cell
US8227284B2 (en) * 2006-08-18 2012-07-24 Showa Denko K.K. Group-III nitride compound semiconductor light-emitting device, method of manufacturing group-III nitride compound semiconductor light-emitting device, and lamp
JP2008177525A (ja) * 2006-12-20 2008-07-31 Showa Denko Kk Ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
US20080223434A1 (en) * 2007-02-19 2008-09-18 Showa Denko K.K. Solar cell and process for producing the same
JP5471440B2 (ja) * 2007-05-02 2014-04-16 豊田合成株式会社 Ｉｉｉ族窒化物半導体発光素子の製造方法
JP5272390B2 (ja) * 2007-11-29 2013-08-28 豊田合成株式会社 Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
JP5262206B2 (ja) * 2008-03-12 2013-08-14 豊田合成株式会社 Ｉｉｉ族窒化物半導体層の製造方法及びｉｉｉ族窒化物半導体発光素子の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263749A (ja) * 1994-03-22 1995-10-13 Toyoda Gosei Co Ltd ３族窒化物半導体の製造方法
JPH08181073A (ja) * 1994-12-21 1996-07-12 Canon Inc 半導体ウエハ及び結晶成長方法
JP2000216164A (ja) * 1998-09-09 2000-08-04 Matsushita Electronics Industry Corp 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016066804A (ja) * 2009-11-13 2016-04-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US10083823B2 (en) 2009-11-13 2018-09-25 Semiconductor Energy Laboratory Co., Ltd. Sputtering target and manufacturing method thereof, and transistor
JP2012212880A (ja) * 2011-03-23 2012-11-01 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US11713516B2 (en) 2020-06-12 2023-08-01 Panasonic Holdings Corporation Group III nitride crystal, group III nitride substrate, and method of manufacturing group III nitride crystal

Also Published As

Publication number Publication date
US8097482B2 (en) 2012-01-17
JP5049659B2 (ja) 2012-10-17
US20100244086A1 (en) 2010-09-30
JP2008306114A (ja) 2008-12-18

Similar Documents

Publication Publication Date Title
WO2008152944A1 (ja) Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
WO2008102646A1 (ja) Ｉｉｉ族窒化物半導体発光素子の製造方法及びｉｉｉ族窒化物半導体発光素子並びにランプ
WO2008136504A1 (ja) Ｉｉｉ族窒化物半導体発光素子の製造方法
WO2010120411A3 (en) Pulsed plasma deposition for forming microcrystalline silicon layer for solar applications
EP1433207B8 (en) A process for large-scale production of cdte/cds thin film solar cells
EP2230703A3 (en) Manufacturing apparatus and manufacturing method of lighting device
TW200741823A (en) Semiconductor device manufacturing method and substrate processing apparatus
TW200731407A (en) Manufacturing method for a semiconductor device and substrate processing apparatus
WO2010080358A3 (en) Edge film removal process for thin film solar cell applications
TW200604093A (en) Silicon nitride film with stress control
WO2012031238A3 (en) Uniform multilayer graphene by chemical vapor deposition
WO2012174260A3 (en) Pinhole-free dielectric thin film fabrication
WO2007024341A3 (en) Method of preparing a film layer-by-layer using plasma enhanced atomic layer deposition
WO2008143885A3 (en) Protection layer for fabricating a solar cell
WO2007118031A3 (en) Silicon oxynitride gate dielectric formation using multiple annealing steps
WO2007117583A3 (en) Cluster tool for epitaxial film formation
WO2009069550A1 (ja) Ｉｉｉ族窒化物半導体の製造方法、ｉｉｉ族窒化物半導体発光素子の製造方法、及びｉｉｉ族窒化物半導体発光素子、並びにランプ
WO2011008925A3 (en) Methods for forming dielectric layers
TW200502888A (en) Manufacturing method of optoelectronic device, optoelectronic device, and electronic machine
WO2007103598A3 (en) Silicon photovoltaic cell junction formed from thin film doping source
WO2012170150A3 (en) Selective deposition of polymer films on bare silicon instead of oxide surface
TW200505280A (en) Manufacturing method and manufacturing apparatus of organic thin film
WO2010080446A3 (en) Microcrystalline silicon alloys for thin film and wafer based solar applications
MY170051A (en) Method for depositing layers on a glass substrate by means of low-pressure pecvd
MX2010007723A (es) Dispositivos fotovoltaicos tratados con plasma.

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08765019

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12438047

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08765019

Country of ref document: EP

Kind code of ref document: A1