WO2008150032A1 - 半導体メモリ装置およびその製造方法 - Google Patents
半導体メモリ装置およびその製造方法 Download PDFInfo
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- WO2008150032A1 WO2008150032A1 PCT/JP2008/060812 JP2008060812W WO2008150032A1 WO 2008150032 A1 WO2008150032 A1 WO 2008150032A1 JP 2008060812 W JP2008060812 W JP 2008060812W WO 2008150032 A1 WO2008150032 A1 WO 2008150032A1
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- Prior art keywords
- film
- memory device
- silicon nitride
- semiconductor memory
- silicon
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 111
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 111
- 238000000034 method Methods 0.000 claims abstract description 76
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 28
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 26
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- 239000010410 layer Substances 0.000 claims description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 14
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 10
- -1 nitrogen-containing compound Chemical class 0.000 claims description 10
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 9
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- 229910021529 ammonia Inorganic materials 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
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- 239000002994 raw material Substances 0.000 claims description 5
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- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical group Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 claims description 2
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- 101100518501 Mus musculus Spp1 gene Proteins 0.000 description 2
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- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 2
- CWGBFIRHYJNILV-UHFFFAOYSA-N (1,4-diphenyl-1,2,4-triazol-4-ium-3-yl)-phenylazanide Chemical compound C=1C=CC=CC=1[N-]C1=NN(C=2C=CC=CC=2)C=[N+]1C1=CC=CC=C1 CWGBFIRHYJNILV-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 241000237503 Pectinidae Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
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- 230000005672 electromagnetic field Effects 0.000 description 1
- 150000002429 hydrazines Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- 239000007921 spray Substances 0.000 description 1
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- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
Definitions
- the present invention relates to a semiconductor memory device and a manufacturing method thereof.
- S ONO S (S i 1 icon-As a non-volatile semiconductor memory device represented by EEPR OM (Electrical 1 y Erasable and Programmable R OM) and Flash EEPR ⁇ M that can be electrically rewritten O xide-N itride-O xide-S i 1 icon) type and MONO S (eta 1 — O xide — N itride — O xide — S i 1 icon) type are known.
- EEPR OM Electrical 1 y Erasable and Programmable R OM
- Flash EEPR ⁇ M Flash EEPR ⁇ M that can be electrically rewritten O xide-N itride-O xide-S i 1 icon
- MONO S eta 1 — O xide — N itride — O xide — S i 1 icon
- non-volatile semiconductor memory devices information is retained by using a silicon nitride film (S i 1 iCon N i tide) sandwiched between silicon dioxide films (S i 1 i c o n i o d i d e) as a charge trapping layer.
- a silicon nitride film S i 1 iCon N i tide
- silicon dioxide films S i 1 i c o n i o d i d e
- Patent Document 1 As a technology related to a nonvolatile semiconductor memory device, for example, in WO 99/0700 (hereinafter referred to as Patent Document 1), a silicon nitride (SiN) film sandwiched between silicon oxide (Si02) films is used.
- the charge trapping layer is used to store charges in two charge trapping regions that are spatially separated from the charge trapping layer. It is described that 2-bit information can be stored in one memory cell.
- information writing and Z reading are performed by alternately switching the functions of the source and drain corresponding to the two charge trapping regions.
- Patent Document 2 Japanese Patent Application Laid-Open No. 2 0 0 7-8 8 4 1 8 (US 2 0 0 7 0 6 3 2 7 0, hereinafter, Patent Document 2), a flask-shaped trench having a round bottom on a silicon substrate is disclosed. It is described that a spherical recess gate transistor obtained by embedding an electrode material therein and securing a sufficient effective channel length while reducing the area of the transistor.
- Patent Document 1 Special Table 2 0 0 1 — 5 1 2 2 9 0 Publication (for example, Fig. 2)
- Patent Document 2 Japanese Laid-Open Patent Publication No. 2 0 0 7 — 8 8 4 1 8 (for example, FIG. 9) Disclosure of Invention
- non-volatile semiconductor memory device that stores information of multiple bits of 2 bits or more in a single cell, a write failure is prevented and high operation reliability is ensured.
- a semiconductor memory device comprising: a semiconductor layer; a trench formed in the semiconductor layer; and a round wall portion having side walls facing each other with a curvature; and an inner wall portion of the trench A first insulating film formed along the surface of the semiconductor layer, and a pair of mutually separated charge trapping regions provided adjacent to the first insulating film in the round wall portion of the trench A gate electrode inserted in the trench of the semiconductor layer, and a semiconductor layer on both sides of the gate electrode, opposite to the semiconductor layer.
- the first and second regions having the conductivity type of the first and second regions, and further, a first electrode formed between the gate electrode, the first insulating film and the respective charge trapping regions. 2 insulation A film may be provided.
- each of the charge trapping regions may be formed to extend from the round wall portion toward the upper portion of the trench.
- each charge trapping region may be formed of a silicon nitride film.
- the gate electrode is formed of metal
- each of the charge trapping regions is formed of a silicon nitride film
- the first insulating film is formed of a silicon dioxide film or a silicon oxynitride film
- the gate electrode is formed of polycrystalline silicon or metal
- the second insulating film is formed of a silicon dioxide film or a silicon oxynitride film
- each of the charge trapping regions is formed of a silicon nitride film
- the first insulating film is formed of a silicon dioxide film or a silicon oxynitride film
- the semiconductor layer is formed of silicon, so that SON O S is formed in a direction crossing the gate electrode inserted in the semiconductor layer. You may make it have a structure or a MNOS structure.
- the S ONS structure or the MONOS structure may be formed symmetrically around the gate electrode.
- a semiconductor memory device includes a semiconductor layer, a gate electrode whose upper portion protrudes from the semiconductor layer, and whose lower portion is inserted into the semiconductor layer, the semiconductor layer and the gate electrode, A first insulating film formed along the semiconductor layer, a pair of mutually separated charge trapping regions formed between the first insulating film and the gate electrode, and the gate A first source Z drain region and a second source / drain region formed in the semiconductor layer on both sides of the electrode may be provided.
- the device may further include a second insulating film formed between the first insulating film and the charge trapping region and the gate electrode.
- a plasma processing apparatus in which the silicon nitride film is generated by introducing a microwave into a processing chamber using a planar antenna having a plurality of holes, and a nitrogen-containing compound and silicon are used in the processing chamber.
- a method for manufacturing a semiconductor memory device comprising: forming a trench having a round wall portion in which a sidewall facing each other is formed with a curvature in a semiconductor layer; and an inner surface of the trench.
- a step of forming a first insulating film on a surface layer of the semiconductor layer a step of forming a silicon nitride film by a plasma CVD method so as to cover the first insulating film, and at least the round wall portion
- a step of etching the silicon nitride film so as to leave a pair of the silicon nitride films separated from each other on a side wall portion of the trench including the inside of the trench and not to remain at the bottom of the trench; and filling the trench Forming a gate electrode by patterning the electrode film protruding outside the trench, and forming the gate electrode in the semiconductor layer.
- the step of etching the silicon nitride film leaves only a pair of the silicon nitride films separated from each other only inside the round wall, and does not remain in other portions.
- the silicon nitride film may be etched.
- a second insulating film is further provided between the step of etching the silicon nitride film and the step of forming the electrode film so as to cover the first insulating film and the silicon nitride film.
- a step of forming may be provided.
- the step of forming the silicon nitride film may be performed by introducing a microwave into a processing chamber using a planar antenna having a plurality of holes.
- a plasma processing apparatus that generates plasma by supplying a source gas containing a nitrogen-containing compound and a silicon-containing compound into the processing chamber, and generating plasma by the microwave to deposit silicon nitride. You may carry out by CVD method.
- ammonia or nitrogen is used as the nitrogen-containing compound, and silane (SiH 4), nitrogen (Si 2) is used as the silicon-containing compound.
- the silicon nitride film may be formed using H 6 ) or trisilane (S i 3 H 8 ), respectively.
- ammonia is used as the nitrogen-containing compound for HU
- disilane is used as the compound containing the U-conductor
- the flow rate ratio is 0.1 to L: 100 a 1 3 3 3
- the silicon nitride film may be formed by generating a plasma with a processing pressure within the range of Pa.
- Disilane is used as a compound, and the flow rate ratio (nitrogen flow rate / nitron flow rate) is in the range of 0 • 1 to 500,000, in the range of 0.1 Pa to 500 ⁇ a.
- Plasma may be generated by the processing pressure in the enclosure to form a silicon nitride film.
- the temperature may be within the range of 0 0 ° c.
- the semiconductor memory device of the present invention since a pair of charge trapping regions separated from each other is provided, a write failure when writing / reading a plurality of information of 2 bits or more in one memory cell is reduced, and a fine Even in this case, high operational reliability can be ensured. Therefore, by integrating this semiconductor memory device, a large-capacity storage device can be realized. In addition, according to the method for manufacturing a semiconductor memory device of the present invention, the semiconductor memory device having the above characteristics can be easily manufactured.
- FIG. 1 is an explanatory diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.
- FIG. 2 is an explanatory view showing an outline of a manufacturing process of the nonvolatile semiconductor memory device shown in FIG.
- FIG. 3 is an explanatory view showing a manufacturing process of the nonvolatile semiconductor memory device shown in FIG.
- FIG. 4 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 5 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 6 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 7 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 8 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 9 is an explanatory diagram for explaining a process following the process illustrated in FIG.
- FIG. 10 is a schematic sectional view showing an example of a plasma processing apparatus suitable for carrying out the method for forming a silicon nitride film of the present invention.
- FIG. 11 shows the structure of the planar antenna member.
- FIG. 12 is an explanatory diagram showing the configuration of the control unit.
- FIG. 13 is an explanatory diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
- FIG. 14 is an explanatory diagram showing a schematic configuration of a modification of the nonvolatile semiconductor memory device according to the second embodiment.
- the nonvolatile semiconductor memory device 200 is capable of writing / reading a plurality of bits of 2 bits or more in, for example, one memory cell having one transistor.
- the non-volatile semiconductor memory device 200 has a trench formed in a p-type silicon substrate (Si substrate) 20 1 as a silicon layer, for example, a trench 2 0 3 having a round bottom cross section, Tunnel oxide film 2 0 5 as the first insulating film formed on the surface layer of Si substrate 2 0 1 including the inner wall portion of trench 2 0 3, and tunnel oxide film 2 0 5 inside trench 2 0 3
- the silicon nitride films 2 0 7 a and 2 0 7 b as charge trapping regions provided on the surface of the silicon oxide film, and the second insulation covering the tunnel oxide films 2 0 5 and the silicon nitride films 2 0 7 a and 2 0 7 b
- the nonvolatile semiconductor memory device 200 may be formed on a p-well or a p-type silicon layer in the Si substrate 2 0 1. Also, the illustration Although omitted, an element isolation film is formed on the Si substrate 20 1. An active region A in which the nonvolatile semiconductor memory device 200 is formed is defined by the element isolation film.
- the trench 20 3 includes a planar wall portion 20 3 a in which opposing sidewalls are formed in a substantially planar shape from the surface side of the Si substrate 20 1 to a predetermined depth, and the planar wall portion 20 3 Side walls facing each other are formed with a curvature in the vicinity of the bottom of the trench 203, and in a lateral direction (a direction intersecting the depth direction of the trench 203) with respect to the planar wall 2003a. It has an expanded (swelled) round wall 2 0 3 b.
- the tunnel oxide film 205 as the first insulating film is formed on the surface layer of the Si substrate 20 01 including the inner wall portion of the trench 20 03.
- the tunnel oxide film 205 can be formed by oxidizing the silicon exposed surface of the Si substrate 201 to a predetermined film thickness by, for example, a thermal oxidation method or a plasma oxidation method.
- the silicon nitride (S i x N y ) films 20 7 a and 20 07 b serving as charge trapping regions are provided in a pair on the inner side of the round wall portion 20 3 b of the trench 20 3.
- the silicon nitride films 2 0 7 a and 2 0 7 b are centered on the lower part 2 1 lb of the gate electrode 2 1 1, and the first source Z drain region 2 1 3 a side on both sides thereof And second source / drain regions 2 1 3 b are formed separately from each other.
- the silicon nitride films 2 07 a and 2 0 7 b are sandwiched between the tunnel oxide film 2 0 5 and the silicon dioxide film 2 0 9.
- the silicon nitride films 2 0 7 a and 2 0 7 b are, for example, about 2 to 10 nm in a direction crossing the lower part 2 1 1 b of the gate electrode 2 1 1 inserted in the Si substrate 2 0 1. It is composed of a S i x N y film or a S i o N film formed with a film thickness.
- the silicon nitride film 2 0 7 a, 2 0 7 b preferably has a trap density of, for example, 5 X 1 0 1 2 ⁇ : LX 1 0 1 3 cm— 2 eV ” 1.
- a plasma processing apparatus that generates plasma by introducing a microwave into a processing chamber using a planar antenna having a plurality of holes, and plasma C VD (Chemical V apor D eposition; chemical vapor deposition).
- plasma C VD Chemical V apor D eposition; chemical vapor deposition.
- the silicon dioxide (S i O 2 ) film 20 09 as the second insulating film is composed of the tunnel oxide film 205 or the silicon nitride films 20 07 a and 20 07 b and the lower part of the gate electrode 2 11 It is interposed between 2 1 1 b.
- the silicon dioxide film 20 9 is a film formed by, for example, the C VD method, particularly the thermal C VD method, and is formed between the gate electrode 2 1 1 and the silicon nitride films 2 0 7 a and 2 0 7 b. Functions as a barrier layer.
- the silicon dioxide film 20 9 has a thickness of about 5 to 15 nm.
- a silicon oxynitride (SiON) film obtained by nitriding the silicon dioxide film 2009 can also be used as the second insulating film.
- the gate electrode 2 1 1 is substantially T-shaped in cross section, and its upper part 2 1 1 a protrudes from the upper surface of the Si substrate 2 0 1, and its lower part 2 1 1 b comes into contact with the silicon dioxide film 2 0 9 In the trench 2 0 3 is inserted.
- the gate electrode 211 is made of, for example, a polycrystalline silicon film formed by the CVD method, and functions as a control gate (CG) electrode. Further, the gate electrode 2 1 1 may be a film containing a metal such as W 1, T i, Ta, Cu, A 1, A u, and Pt.
- the upper part 2 1 1 a of the gate electrode 2 1 1 has a film thickness of, for example, about 0.1 to 50 nm.
- the lower part 2 1 1 b of the gate electrode 2 1 1 has a width of, for example, about 2 to 1 O nm in the transverse direction.
- tungsten, molybdenum, tantalum, titanium, copper, gold, silver, platinum, and their silicides are used for the purpose of reducing the specific resistance of the gate electrode and increasing the speed.
- a laminated structure including a triangle, an alloy, or the like can be formed.
- the gate electrode 2 1 1 is connected to a wiring layer (not shown).
- the first source Z drain region 2 1 3 a and the second source Z drain region 2 1 3 b are both of the same conductivity type and have a conductivity type opposite to that of the Si substrate 2 0 1 As shown, impurities are ion-implanted.
- the first source / drain region 2 1 3 a and the second source Z drain region 2 1 3 b are formed in the Si substrate 2 0 1 on both sides so that the gate electrode 2 1 1 is sandwiched therebetween Has been.
- the first source Z drain region 2 1 3 a and the second source / drain region 2 1 3 b each have a source function and a drain function, one of which is the source. When functioning as the other, the other functions as the drain.
- the region around the trench 20 3 sandwiched between the first source / drain region 2 1 3 a and the second source Z drain region 2 1 3 b is the non-volatile semiconductor memory device 200. It is a channel formation region.
- the first source / drain region 2 1 3 a and the second source / drain region 2 1 3 b are the first source / drain electrode (hereinafter referred to as the first electrode) 2 2 0 a and the second Source / drain electrodes (hereinafter referred to as second electrodes) 2 2 Ob are connected to the respective contacts via contact holes (not shown).
- the first and second electrodes 2 220 a and 2 2 0 b are insulated from the gate electrode 2 1 1 by the third insulating film 2 2 2.
- Reference numeral 2 24 denotes a fourth insulating film for protecting the first and second electrodes 2 20 a and 2 2 0 b or separating them from a wiring layer (not shown).
- the nonvolatile semiconductor memory device 200 has the gate in the transverse direction intersecting with the lower part 2 1 1 b of the gate electrode 2 1 1 inserted in the wrench 20 3.
- SONOS structure or MONO S structure in which electrode 2 1 1, silicon dioxide film 20 9, silicon nitride film 2 0 7 a, 2 0 7 b, tunnel oxide film 2 0 5 and Si substrate 2 0 1 are arranged Have. These S ON OS structure and MON OS structure are formed symmetrically about the lower part 2 1 1 b of the gate electrode 2 1 1.
- the nonvolatile semiconductor memory device 2 0 0 channel, the first source / / drain regions 2 1 3 a and the trench 2 0 3 rounds between the second source / drain regions 2 1 3 b
- the wall is formed with a curvature along the wall 2 0 '3 b. Therefore, a sufficient channel length L can be ensured without increasing the area of the nonvolatile semiconductor memory device 200.
- the nonvolatile semiconductor memory device 200 uses a pair of silicon nitride films 2 0 7 a and 2 0 7 b which are charge trapping regions, and performs not only a 1-bit write Z read but also a single memory. 'It is possible to read / write multiple bits of more than 2 bits in a cell.
- Writing, reading, and erasing in the nonvolatile semiconductor memory device 200 can be performed in the same manner as a known method, for example, Japanese Patent Publication No. 2 0 0 1-5 1 2 2 90 (Patent Document 1). .
- the write voltage VW 1 is applied to the gate electrode 2 1 1, and the write voltage VW 2 is applied to the first source / drain region 2 1 3 a via the first electrode 2 2 0 a
- the second source Z drain region 2 1 3 b is grounded through the second electrode 2 2 0 b.
- the silicon nitride adjacent to the first source / drain region 2 1 3 a using the hot-electron injection phenomenon is used. It is possible to perform 1-bit writing by trapping charges in the base film 2 0 7 a.
- the write voltage VW 3 is applied to the gate electrode 2 1 1
- the write voltage VW4 is applied to the second source / drain region 2 1 3 b through the second electrode
- the first voltage The first source Z drain region 2 1 3 a is grounded through the electrode.
- the write voltages VW 1 and VW4 are preferably set to about 1/2 of V d d (power supply voltage) so as to increase the probability that hot carriers are generated.
- a 1-bit read from the silicon nitride film 20 7 a is performed in the opposite direction to the write. That is, the read voltage VR 1 is applied to the gate electrode 2 1 1, the read voltage VR 2 is applied to the second source / drain region 2 1 3 b, and the first source / drain region 2 1 3 a Is detected, and the presence or absence of current flowing from the second source Z drain region 2 1 3 b to the first source Z drain region 2 1 3 a is detected.
- 1-bit reading from the silicon nitride film 20 7 b is performed in the opposite direction to the writing. That is, the read voltage VR 3 is applied to the gate electrode 2 1 1, the read voltage VR 4 is applied to the first source Z drain region 2 1 3 a, and the second source Z drain region 2 1 3 b And the presence or absence of current flowing from the first source / drain region 2 1 3a to the second source / drain region 2 1 3b is detected.
- the write voltage VW1 to VW4 and the read voltage are used to prevent unintended write or forward read from occurring when the intended write or read is performed.
- VR 1 to VR 4 size and threshold when reading What is necessary is just to set the magnitude
- the nonvolatile semiconductor memory device 2 0 0 includes a pair of silicon nitride films 2 0 7 a and 2 0 7 b that are separated from each other as a charge trapping region.
- the nonvolatile semiconductor memory device 200 can distinguish the charge trapping region when writing / reading a plurality of bits of 2 bits or more with one transistor even if miniaturization is advanced. Therefore, the use of the nonvolatile semiconductor memory device 2 0 0 increases the The effect is that a large amount of information can be stored with reliability.
- FIG. 2 is a flowchart showing an outline of main process steps of the method for manufacturing the nonvolatile semiconductor memory device 200.
- 3 to 9 are explanatory views showing main steps of the method for manufacturing the nonvolatile semiconductor memory device 200.
- the element isolation film is formed on the Si substrate 20 1 by using a technique such as LOC ⁇ S (Loca 1 Oxidation of Silicon; ⁇ STI (Sha 1 low Trenches I solation)).
- impurity doping can be performed by a method such as ion implantation.
- trenches 20 3 are formed (step S 1).
- the trench 20 3 has a planar wall portion 20 3 a and a round wall portion 2 0 3 b.
- the wrench 20 3 having such a cross-sectional shape can be formed by a known method, for example, a procedure described in Japanese Patent Laid-Open No. 20 07-8 8 4 18 (Patent Document 2). .
- Patent Document 2 Japanese Patent Laid-Open No. 20 07-8 8 4 18
- the Si substrate 2 0 1 is anisotropically etched using a predetermined mask pattern as an etching mask.
- a concave portion that forms the upper portion of the trench 20 3 (planar wall portion 20 3 a) is formed.
- a protective film made of a silicon oxide film is formed on the side wall of the formed recess by, for example, the CVD method. Since the protective film formed by the C VD method is formed on the entire surface in the recess, the protective film on the bottom in the recess is removed by anisotropic etching, and later a planar wall portion 203 a is planned. The protective film is left only on the upper part of the recess. Next, using the protective film and mask pattern as an etching mask, the bottom of the exposed recess Is dug by isotropic etching.
- the Si substrate 20 1 is also etched in the lateral direction in the recess, so that the lower part of the recess is formed in a round bottom flask shape that swells wider than the upper part.
- isotropic etching causes side etching to enter the vicinity of the bottom of the recess, and the top of the recess protected by the protective film protrudes inward.
- the vicinity of the bottom of the recess becomes a shape with a rounded wall surface, such as a spherical shape or an elliptical shape.
- the trench 20 3 formed in this manner has a round shape in which the lower part 203b near the bottom part has a round shape with respect to the upper part 203a formed by the substantially vertical wall surface from the surface of the Si substrate 2001. It becomes the shape expanded to. Thereafter, the protective film and the mask pattern are removed.
- a tunnel oxide film as a first insulating film is formed on the inner wall of the trench 20 3 and the upper surface of the Si substrate 2 0 1 by a method such as a thermal oxidation method or a plasma oxidation method. 2 0 5 is formed (step S 2).
- the tunnel oxide film 205 can be formed of a silicon dioxide film, a high dielectric constant film (hig h k film), or the like. The tunnel oxide film 205 is formed to cover the inner wall of the trench 20 3 and the upper surface of the Si substrate 2 0 1 in the active region A with a uniform thickness.
- a silicon oxynitride film (SiO N film) obtained by nitriding the surface of the silicon dioxide film 205 may be used as the tunnel oxide film 205.
- the nitriding treatment can be performed by a plasma nitriding treatment method that can nitride the tunnel oxide film surface at a low temperature. This method can suppress the diffusion of nitrogen in the thickness direction of the tunnel oxide film when forming the nitride film.
- a silicon nitride film 20 7 is formed by plasma CVD so as to cover the surface of the tunnel oxide film 205 (step S 3).
- the silicon nitride film 20 7 is formed on the upper surface of the Si substrate 20 1
- the tunnel oxide film 205 formed on the inner surface of the wrench 20 3 is formed so as to cover with a uniform film thickness.
- the silicon nitride film 20 7 is preferably formed using, for example, a plasma processing apparatus in which a plasma is generated by introducing a microphone mouth wave into the processing chamber using a planar antenna having a plurality of holes. Plasma CV for forming this silicon nitride film 2 0 7
- step S 4 most of the uniformly formed silicon nitride film 20 7 is backed and removed (step S 4).
- anisotropic etching is performed to form a silicon nitride film 20 only on the tunnel oxide film 20 5 inside the round wall 2 0 3 b of the wrench 20 3.
- Silicon nitride films 2 0 7 a and 2 0 7 b separated into left and right within 2 0 3 are formed.
- a silicon dioxide film 20 9 as a second insulating film is formed so as to cover the tunnel oxide film 20 5 and the silicon nitride films 2 0 7 a and 2 0 7 b. (Step S5)
- an electrode film 2 10 is formed so as to fill the trench 20 3 and cover the silicon dioxide film 2 09 (step S 6).
- the electrode film 210 is formed by, for example, a polysilicon layer, a metal layer, or a metal silicide layer by a CVD method.
- the electrode film 2 10 is etched using the resist pattern formed by the photolithography technique as a mask to form a pattern (step S 7). Therefore, as shown in FIG. 9, the cross-sectional view has a substantially letter shape, the upper 2 1 1 a protrudes from the Si substrate 2 0 1, and the lower 2 lib is embedded in the Si substrate 2 0 1. ⁇ Electrode 2 1 1 is formed. Next, n-type impurities are ion-implanted at a high concentration into the silicon in the active region A to form the first source / drain region 2 1 3 a and the second source Z drain region 2 1 3 b ( Step S 8).
- first and second electrodes 2 2 0 a and 2 2 0 b are appropriately formed through an interlayer insulating film, and a wiring layer is formed. In this way, the nonvolatile semiconductor memory device 200 having the structure shown in FIG. 1 can be manufactured.
- the n-channel nonvolatile semiconductor memory device 200 is taken as an example, but in the case of a p-channel semiconductor memory device, the impurity conductivity type may be reversed.
- FIG. 10 is a cross-sectional view schematically showing a schematic configuration of a plasma processing apparatus 100 that can be used for forming the silicon nitride films 20 7 a and 20 7 b as charge trapping regions in the present invention.
- FIG. 11 is a plan view showing a planar antenna member of the plasma processing apparatus 100 of FIG.
- FIG. 12 is a diagram showing a configuration example of a control unit of the plasma processing apparatus 100 of FIG.
- the plasma processing apparatus 100 introduces a microphone antenna into the processing chamber using a planar antenna having a plurality of slot-shaped holes, especially RLSA (Radial Line Slot Antenna).
- RLSA Random Line Slot Antenna
- the plasma processing apparatus 100 is configured as an RLSA microwave plasma processing apparatus capable of generating microwave-excited plasma with high density and low electron temperature by generating plasma.
- the plasma processing apparatus 100 processing with plasma having a plasma density of 1 ⁇ 10 10 ⁇ ⁇ ⁇ ⁇ 12 / cm 3 and a low electron temperature of 0.7 to 2 eV is possible. Therefore, the plasma processing apparatus 100 is a process for forming a silicon nitride film by a plasma CVD method in the manufacturing process of various semiconductor devices. It can be suitably used for the purpose of management.
- the plasma processing apparatus 100 includes, as main components, an airtight chamber (processing chamber) 1, a gas supply mechanism 18 for supplying gas into the chamber 1, and a pressure reduction in the chamber 1.
- An exhaust device 24 as an exhaust mechanism for exhausting, a microwave introduction mechanism 2 7 provided in the upper part of the chamber 1 for introducing microwaves into the chamber 1, and these plasma processing devices 10 0
- a control unit 50 for controlling each of the components.
- the chamber 11 is formed of a substantially cylindrical container that is grounded.
- the chamber 11 may be formed of a rectangular tube container.
- the chamber 1 has a bottom wall 1a and a side wall 1b made of a material such as aluminum.
- a mounting table 2 for horizontally supporting a silicon wafer (hereinafter simply referred to as “wafer”) W which is an object to be processed.
- the mounting table 2 is made of a material having high thermal conductivity, such as ceramics such as A 1 N.
- the mounting table 2 is supported by a cylindrical support member 3 that extends upward from the center of the bottom of the exhaust chamber 11.
- the support member 3 is made of ceramics such as A 1 N, for example.
- the mounting table 2 is provided with a covering 4 for covering the outer edge of the mounting table 2 and guiding the wafer W.
- the Kabari ring 4, for example, quartz is an annular member formed of a material such as A 1 N, A l 2 ⁇ 3, S i N.
- a resistance heating type heater 5 as a temperature adjusting mechanism is embedded in the mounting table 2.
- the heater 5 heats the mounting table 2 by being supplied with power from the heater power source 5a, and uniformly heats the wafer W as a substrate to be processed by the heat.
- the mounting table 2 is provided with a thermocouple (TC) 6. By measuring the temperature with this thermocouple 6, the heating temperature of the wafer W can be controlled in the range from room temperature to 900 ° C., for example.
- the mounting table 2 has wafer support pins (not shown) for supporting the wafer W and moving it up and down. Each wafer support pin is provided so as to protrude and retract with respect to the surface of the mounting table 2.
- An annular upper plate 1 3 is joined to the upper end of the side wall 1 b forming the chamber 1 1.
- the lower part of the inner periphery of the upper plate 1 3 is
- annular support portion 1 3 a Projecting toward the inside (chamber inner space) to form an annular support portion 1 3 a.
- the upper plate 1 1 3 is provided with an annular gas inlet 14. Further, an annular gas introduction portion 15 is provided on the side wall 1 b of the chamber 1. This means that the gas inlets 1 4 and 1 5
- the gas inlets 14 and 15 provided in two upper and lower stages are connected to a gas supply mechanism 18 for supplying a film-forming source gas and a plasma excitation gas.
- the gas introduction parts 14 and 15 may be provided in a nozzle shape or a shared shape.
- a loading / unloading port 16 for loading / unloading the wafer W and a gate valve 17 for opening / closing the loading / unloading port 16 are provided between a transfer chamber (not shown) adjacent to the transfer chamber. .
- the gas supply mechanism 18 is, for example, a nitrogen-containing gas (N-containing gas) supply source. 1 9a, silicon-containing gas (Si-containing gas) supply source 19b and inert gas supply source 19c.
- the nitrogen-containing gas supply source 19 a is connected to the upper gas introduction section 14.
- the silicon-containing gas supply source 19 b and the inert gas supply source 19 c are connected to the lower gas introduction unit 15.
- the gas supply mechanism 18 includes, as gas supply sources (not shown) other than the above, for example, a purge gas supply source used when replacing the atmosphere in the chamber, and a cleaning gas supply source used when cleaning the inside of the chamber 1 Etc. may be included.
- nitrogen-containing gas that is a film forming raw material gas for example, hydrazine derivatives such as nitrogen gas (N 2), ammonia (NH 3 ), and MMH (monomethyl hydrazine) can be used.
- silicon-containing gases which are film forming raw materials, include, for example, silane (S i H 4 ), disilane (S i 2 H 6 ), trisilane (S i 3 H 8 ), and TSA (trisilylamine). can have use etc.
- Jikuroshiran S i C 1 2 H 2 ). Of these, disilane (S i 2 H 6 ) is particularly preferred.
- the inert gas for example, N 2 gas or rare gas can be used as the inert gas.
- the rare gas is a plasma excitation gas.
- Ar gas, Kr gas, Xe gas, He gas, etc. can be used.
- the nitrogen-containing gas is introduced from the nitrogen-containing gas supply source 19a of the gas supply mechanism 18 to the gas introduction unit 14 via the gas line 20 and introduced into the chamber 1 from the gas introduction unit 14 .
- the silicon-containing gas and the inert gas reach the gas introduction unit 15 from the silicon-containing gas supply source 19 b and the inert gas supply source 19 c through the gas line 20, respectively.
- Part 15 is introduced into the chamber 1 1.
- Each gas line 20 connected to each gas supply source is provided with a mass flow controller 21 and opening / closing valves 22 before and after the mass flow controller 21.
- Such a configuration of the gas supply mechanism 18 makes it possible to switch the supplied gas and control the flow rate.
- the rare gas for plasma excitation such as Ar, is an arbitrary gas and does not necessarily have to be supplied simultaneously with the film forming source gas.
- the exhaust device 24 as an exhaust mechanism has a suction mechanism including a high-speed vacuum pump. As described above, the exhaust device 24 is connected to the exhaust chamber 11 of the chamber 1 through the exhaust pipe 12. By operating the exhaust device 24, the gas in the chamber 1 flows uniformly into the space 11a of the exhaust chamber 11 and further exhausts from the space 11a through the exhaust pipe 12 to the outside. Is done. As a result, the inside of the chamber 11 can be depressurized at a high speed to a predetermined vacuum, for example, 0.13 3 Pa.
- Microphone Mouth wave introduction mechanism 2 7 consists mainly of transmission plate 2 8, planar antenna member 3 1, slow wave material 3 3, shield cover 3 4, waveguide 3 7 and microphone mouth wave generator It has 3 9.
- the transmission plate 28 that transmits microwaves is disposed on a support portion 13 a that protrudes to the inner peripheral side of the upper plate 13.
- the transmission plate 28 is made of a dielectric material such as quartz, ceramics such as Al 2 O 3 and A 1 N.
- a space between the transmission plate 2 8 and the support portion 13 a is hermetically sealed through a seal member 29. Therefore, the inside of the Champer 1 is kept airtight.
- the planar antenna member 31 is provided above the transmission plate 28 so as to face the mounting table 2.
- the planar antenna member 3 1 has a disk shape. Note that the shape of the planar antenna member 31 is not limited to a disk shape, and may be a square plate shape, for example.
- the planar antenna member 3 1 is locked to the upper end of the upper plate 13.
- the planar antenna member 31 is made of, for example, a copper plate or an aluminum plate whose surface is plated with gold or silver.
- the planar antenna member 3 1 has a number of slot-like microwave radiation holes 3 2 that radiate microwaves. The microwave radiation hole 3 2 is formed so as to penetrate the planar antenna member 3 1 in a predetermined pattern.
- Each microwave radiation hole 3 2 has an elongated rectangular shape (slot shape) as shown in FIG.
- adjacent microwave radiation holes 32 are arranged in a “T” shape.
- the microphone mouth wave radiation holes 32 arranged in combination in a predetermined shape for example, a letter shape
- a predetermined shape for example, a letter shape
- the length and arrangement interval of the microwave radiation holes 32 are determined according to the wavelength ( ⁇ g) of the microwave.
- the interval between the microphone mouth wave radiation holes 3 2 is arranged such that the wavelength is ⁇ g 4 ⁇ g / 2 or ⁇ g.
- the interval between adjacent microphone mouth wave radiation holes 3 2 formed concentrically is indicated by ⁇ r.
- the microwave radiation hole 32 may have another shape such as a circular shape or an arc shape.
- the arrangement form of the microwave radiation holes 32 is not particularly limited, and the microwave radiation holes 32 can be arranged concentrically, for example, spirally, radially or the like.
- a slow wave member 33 having a dielectric constant larger than that of a vacuum is provided on the upper surface of the planar antenna member 31.
- This slow wave material 33 has a function of adjusting the plasma by shortening the wavelength of the microwave because the wavelength of the microwave becomes longer in vacuum.
- the 3 3 and the planar antenna member 3 1 may be brought into contact with each other or separated from each other, but are preferably brought into contact with each other.
- a shield lid 34 is provided on the upper portion of the chamber 11 so as to cover the planar antenna member 31 and the retardation material 33.
- the shield lid 34 is made of a metal material such as aluminum or stainless steel.
- the upper end of the upper plate 1 3 and the shield lid 3 4 are sealed by a seal member 3 5.
- a cooling water flow path 3 4 a is formed inside the shield cover 3 4. By passing cooling water through the cooling water flow path 3 4 a, the shield lid body 3 4, the slow wave material 3 3, the planar antenna member 3 1, and the transmission plate 2 8 can be cooled.
- the shield lid 3 4 is grounded.
- An opening 3 6 is formed at the center of the upper wall (ceiling) of the shield lid 3 4, and a waveguide 3 7 is connected to the opening 3 6.
- a microwave generator 39 that generates microwaves is connected to the other end of the waveguide 37 via a matching circuit 3 8.
- the waveguide 37 is connected to the coaxial waveguide 37 having a circular cross section extending upward from the opening 36 of the shield lid 34 and the upper end of the coaxial waveguide 37. And a horizontally extending rectangular waveguide 37b. ⁇
- An inner conductor 41 extends in the center of the coaxial waveguide 37a.
- This inner conductor 41 is connected and fixed to the center of the planar antenna member 31 at its lower end. With such a structure, the microwave is efficiently and uniformly propagated radially and uniformly to the planar antenna member 31 via the inner conductor 4 1 of the coaxial waveguide 37 a.
- the microwave generated by the microwave generator 39 is propagated to the planar antenna member 31 via the waveguide 37, and the transmission plate 28 is Through the chamber 1.
- the microwave frequency For example, 2.45 GHz is preferably used.
- G H z 1. 9 8 G H z etc. can also be used.
- the user interface 5 2 is a display for visualizing and displaying the operation status of the plasma processing apparatus 100 and the operation input of the command for the process manager to manage the plasma processing apparatus 100. Has a spray etc.
- the storage unit 53 is a plasma processing apparatus.
- the plasma processing apparatus 100 configured in this way can perform damage-free plasma CVD processing on the underlying film or the like at a low temperature of 80 ° C. or lower, more preferably 600 ° C. or lower. it can.
- the plasma processing apparatus 100 is excellent in plasma uniformity, it is possible to achieve process uniformity on the upper surface of the substrate and the inner wall surface of the trench.
- a silicon nitride film can be deposited on the Si substrate 20 1 by the plasma C VD method according to the following procedure.
- the gate valve 17 is opened, and the wafer W is loaded into the chamber 11 from the loading / unloading port 16 and mounted on the mounting table 2.
- nitrogen-containing gas and silicon-containing gas are supplied at a predetermined flow rate from the nitrogen-containing gas supply source 19a and the silicon-containing gas supply source 19b of the gas supply mechanism 18 while evacuating the chamber 1 under reduced pressure. They are introduced into the chamber 1 through the gas inlets 14 and 15 respectively. In this way, the inside of the chamber 1 is adjusted to a predetermined pressure.
- a microwave having a predetermined frequency, for example, 2.45 GHz generated by the microwave generator 39 is passed through the matching circuit 3 8.
- Guide to waveguide 3 7. The microwave guided to the waveguide 3 7 sequentially passes through the rectangular waveguide 3 7 b and the coaxial waveguide 3 7 a and is supplied to the planar antenna member 3 1 through the inner conductor 4 1. That is, the microwave propagates in the coaxial waveguide 3 7 a toward the planar antenna member 3 1. Then, the microwave is radiated from the slot-like microwave radiation hole 3 2 of the planar antenna member 31 to the space above the wafer W in the chamber 1 through the transmission plate 2 8.
- the microwave output at this time can be, for example, about 500 to 300 W.
- This microwave-excited wave-excited plasma is approximately 1 X 1 0 1 0 to 5 X 1 0 1 2 / cm by radiating microwaves from a large number of microwave radiation holes 3 2 of the planar antenna member 3 1. In the vicinity of wafer W, it has a low electron temperature plasma of about 1.5 eV or less.
- the microwave-excited high-density plasma formed in this way has little plasma damage caused by ions or the like on the underlying film.
- the dissociation of the source gas proceeds in the plasma, and active species such as S ip H q, S i HQ, NH q, N (where p and q are arbitrary numbers, and so on).
- active species such as S ip H q, S i HQ, NH q, N (where p and q are arbitrary numbers, and so on).
- the thin film of silicon nitride S i N y (where x and y are not necessarily stoichiometrically determined and are arbitrary numbers having different values depending on conditions). Is deposited on the wafer W.
- the silicon nitride films 2 0 7 a and 2 0 7 b are selected by selecting the plasma C VD treatment conditions for forming the silicon nitride films 2 0 7 a and 2 0 7 b.
- the trap density can be controlled to a desired size. For example, when the trap density in the silicon nitride films 2 0 7 a and 2 0 7 b to be formed is increased (for example, the trap density is 5 X 1 0 1 2 to 1 X 1 0 1 3 cm— 2 e V— 1 In this range, it is preferable to perform the plasma CVD process under the following conditions. NH 3 gas is used as the nitrogen-containing gas, and Si 2 H 6 gas is used as the silicon-containing gas.
- the flow rate of the NH 3 gas is in the range of 10 to 500 mL / min (secm), preferably 10 0 Within the range of ⁇ 2 0 0 0.mL/min (secm), the flow rate of Si 2 H 6 gas is 0.5 ⁇ ; within the range of LOO mLZm in (sccm), preferably :! Set within the range of ⁇ SO mLZm in (sccm).
- the trap density of the silicon nitride films 2 0 7 a and 2 0 7 b to be formed is reduced (for example, the trap density is 5 X 1 0 1.
- the trap density is 5 X 1 0 1.
- N 2 gas as the nitrogen-containing gas
- Si 2 H 6 gas as the silicon-containing gas.
- the processing pressure is set to 0.1 to 5 to form the silicon nitride films 2 0 7 a and 2 0 7 b having a small trap density.
- 0 OP a is preferable, and 1 to: L 0 0 Pa is more preferable.
- silicon nitride thin films with different trap densities are alternately deposited by performing plasma C VD treatment alternately under the conditions for increasing the trap density and the conditions for decreasing the trap density. It can also be made.
- the plasma CVD process temperature is It is preferable that the temperature of the mounting table 2 is heated to 300 ° C. or higher, preferably from 400 to 600 ° C. Further, the gap (the distance from the lower surface of the transmission plate 28 to the upper surface of the mounting table 2) G in the plasma processing apparatus 100 is an example from the viewpoint of forming the silicon nitride film 20 7 with a uniform film thickness and film quality. For example, it is preferably set to about 50 to 500 mm.
- the nonvolatile semiconductor memory device 200 having the silicon nitride films 20 07 a and 20 07 b as a pair of charge trapping regions can be easily manufactured.
- a non-volatile semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. 13 and FIG.
- the present invention has been described by taking the non-volatile semiconductor memory device 2 0 0 having the S 0 N 0 S structure or the M 0 N 0 S structure as an example.
- the present invention can also be applied to a nonvolatile semiconductor memory device having a structure of MNOS (Metal-Nitride-Oxide-Si1icon).
- MNOS Metal-Nitride-Oxide-Si1icon
- FIG. 13 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment.
- the nonvolatile semiconductor memory device 300 according to the present embodiment includes a trench 2 0 3 having a groove formed in a p-type silicon substrate (S i substrate) 2 0 1 as a silicon layer, and a trench 2 0 3 Tunnel oxide film 205 as the first insulating film formed on the surface layer of the Si substrate 201 including the inner wall portion, and nitridation as a charge trapping region provided inside the trench 203
- the silicon films 2 0 7 a and 2 0 7 b are in contact with the tunnel oxide film 2 0 5 and the silicon nitride films 2 0 7 a and 2 0 7 b so that the lower portions thereof are inserted into the trench 2 0 3.
- the silicon nitride films 2 0 7 a and 2 0 7 b according to the present embodiment have a large trap density, for example, in the range of 5 X 1 0 1 2 to; 1 X 1 0 1 3 cm— 2 e V— 1 . It is preferable to have a trap density of
- the nonvolatile semiconductor memory device 300 includes a gate electrode 2 1 1, nitrided in the transverse direction intersecting the lower part 2 1 1 b of the gate electrode 2 1 1 inserted in the trench 2 0 3. It has a MNOS structure in which silicon films 2 0 7 a and 2 0 7 b, a tunnel oxide film 2 0 5 and a Si substrate 2 0 1 are arranged. This MNO S structure is formed symmetrically about the lower part 2 1 1 b of the gate electrode 2 1 1.
- the nonvolatile semiconductor memory device 300 uses not only a 1-bit write / read but also a single using a pair of silicon nitride films 20 07 a and 20 07 b as charge trapping regions. Multiple memory cells with more than 2 bits can be written to / read from any memory cell.
- the nonvolatile semiconductor memory device 300 includes a silicon dioxide film 20 09 (second insulating film, i.e., a second insulating film) in the nonvolatile semiconductor memory device 200 according to the first embodiment shown in FIG. Except for the point that the upper oxide film) is not provided, it is the same as the first embodiment, and therefore the same components are denoted by the same reference numerals and description thereof is omitted. Further, writing, reading, and erasing in the nonvolatile semiconductor memory device 300 according to the present embodiment can be performed in accordance with the procedure described in the first embodiment. Further, the nonvolatile semiconductor memory device 300 can be manufactured according to the first embodiment, except that the step of forming the silicon dioxide film 20.09 is not provided. Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.
- FIG. 14 shows a modification of the nonvolatile semiconductor memory device 300 according to the present embodiment.
- the upper ends of the pair of silicon nitride films 2 0 7 a and 2 0 7 b which are charge trapping regions are formed along the tunnel oxide film 2 0 5 along the planar wall portion 2 of the trench 2 0 3. It may be extended to the position corresponding to 0 3 a.
- the manufacturing of the nonvolatile semiconductor memory device 300 having such a structure is performed during the anisotropic etching (etchback) of the silicon nitride film 20 7 in step S 4 of the first embodiment.
- the silicon nitride films 2 0 7 a and 2 0 7 b are formed by etching back the single layer silicon nitride film 2 0 7.
- the silicon nitride film 20 7 is formed, a plurality of silicon nitride thin films are sequentially deposited and then etched back, so that a plurality of silicon nitride films 20 7 are formed in the transverse direction intersecting the depth direction of the trench 203.
- silicon nitride films 2 0 7 a and 2 0 7 b having a laminated structure in which silicon nitride thin films are laminated.
- a plurality of silicon nitride thin films having a trap density different from that of at least the adjacent silicon nitride thin film are used to form the silicon nitride film. 2 0 7 a and 2 0 7 b can be formed.
- a plurality of film forming apparatuses including a plasma processing apparatus 100 are connected through a vacuum without being exposed to the atmosphere. It is possible to sequentially form a target film by a film apparatus. For example, the tunnel oxide side Further, a silicon nitride film having a small trap density, a silicon nitride film having a large trap density, a silicon nitride film having a large trap density, and a silicon nitride film having a small trap density are alternately stacked in one cycle at a time.
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
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Abstract
Description
Claims
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US12/663,361 US20100176441A1 (en) | 2007-06-07 | 2008-06-06 | Semiconductor memory device and manufacturing method therefor |
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JP2007151265A JP2008305942A (ja) | 2007-06-07 | 2007-06-07 | 半導体メモリ装置およびその製造方法 |
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JP (1) | JP2008305942A (ja) |
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US20120208376A1 (en) * | 2009-09-30 | 2012-08-16 | Tokyo Electron Limited | Method of forming silicon nitride film and method of manufacturing semiconductor memory device |
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US20090311877A1 (en) * | 2008-06-14 | 2009-12-17 | Applied Materials, Inc. | Post oxidation annealing of low temperature thermal or plasma based oxidation |
JP2010287743A (ja) * | 2009-06-11 | 2010-12-24 | Sony Corp | 半導体装置及びその製造方法、固体撮像素子 |
KR20150062487A (ko) * | 2013-11-29 | 2015-06-08 | 삼성전자주식회사 | 이미지 센서 |
TWI666774B (zh) * | 2018-03-19 | 2019-07-21 | 全宇昕科技股份有限公司 | 高電壓金氧半場效電晶體 |
US10833087B2 (en) * | 2018-08-21 | 2020-11-10 | Micron Technology, Inc. | Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods |
WO2020131296A1 (en) * | 2018-12-21 | 2020-06-25 | Applied Materials, Inc. | Processing system and method of forming a contact |
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JPH0637275A (ja) * | 1992-07-13 | 1994-02-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005116964A (ja) * | 2003-10-10 | 2005-04-28 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2005517301A (ja) * | 2002-02-06 | 2005-06-09 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | メモリセル |
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KR100642650B1 (ko) * | 2005-09-22 | 2006-11-10 | 삼성전자주식회사 | 측방확장 활성영역을 갖는 반도체소자 및 그 제조방법 |
-
2007
- 2007-06-07 JP JP2007151265A patent/JP2008305942A/ja not_active Withdrawn
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2008
- 2008-06-06 WO PCT/JP2008/060812 patent/WO2008150032A1/ja active Application Filing
- 2008-06-06 US US12/663,361 patent/US20100176441A1/en not_active Abandoned
- 2008-06-06 TW TW097121191A patent/TW200915494A/zh unknown
- 2008-06-06 KR KR1020097025325A patent/KR20100018531A/ko not_active Application Discontinuation
Patent Citations (3)
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JPH0637275A (ja) * | 1992-07-13 | 1994-02-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP2005517301A (ja) * | 2002-02-06 | 2005-06-09 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | メモリセル |
JP2005116964A (ja) * | 2003-10-10 | 2005-04-28 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
Cited By (1)
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US20120208376A1 (en) * | 2009-09-30 | 2012-08-16 | Tokyo Electron Limited | Method of forming silicon nitride film and method of manufacturing semiconductor memory device |
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US20100176441A1 (en) | 2010-07-15 |
KR20100018531A (ko) | 2010-02-17 |
JP2008305942A (ja) | 2008-12-18 |
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