WO2008142735A1 - ２進の擬似ランダムデータを生成する方法および装置 - Google Patents

２進の擬似ランダムデータを生成する方法および装置 Download PDF

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Publication number
WO2008142735A1
WO2008142735A1 PCT/JP2007/000542 JP2007000542W WO2008142735A1 WO 2008142735 A1 WO2008142735 A1 WO 2008142735A1 JP 2007000542 W JP2007000542 W JP 2007000542W WO 2008142735 A1 WO2008142735 A1 WO 2008142735A1
Authority
WO
WIPO (PCT)
Prior art keywords
pseudo random
random data
exclusive
inputted
circuits
Prior art date
Application number
PCT/JP2007/000542
Other languages
English (en)
French (fr)
Inventor
Atsuo Hara
Akihide Otonari
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009515007A priority Critical patent/JPWO2008142735A1/ja
Priority to PCT/JP2007/000542 priority patent/WO2008142735A1/ja
Publication of WO2008142735A1 publication Critical patent/WO2008142735A1/ja
Priority to US12/577,998 priority patent/US7812636B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　第１から第ｎ（ｎは３以上の整数）のｎ個のレジスタおよび第１から第ｋ（ｋは２以上の整数）のｋ個の排他的論理和回路を用いてｋビット並列の擬似ランダムデータを生成する装置であって、第ｍのレジスタ（ｍは１からｎ－ｋの整数）の出力は、第（ｍ＋ｋ）のレジスタに入力されており、第１から第（ｋ－１）の排他的論理和回路の出力は、第２から第ｋの排他的論理和回路に入力されており、第１のレジスタの出力は、第１の排他的論理和回路に入力されており、第１から第ｋの排他的論理和回路の出力は、第ｋから第１のレジスタに入力されており、第（ｎ－ｋ＋１）から第ｎのｋ個のレジスタからの出力は、第ｋから第１の排他的論理和回路に入力され、かつ、ｋビット並列の擬似ランダムデータとして取り出される。
PCT/JP2007/000542 2007-05-21 2007-05-21 ２進の擬似ランダムデータを生成する方法および装置 WO2008142735A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009515007A JPWO2008142735A1 (ja) 2007-05-21 2007-05-21 ２進の擬似ランダムデータを生成する方法および装置
PCT/JP2007/000542 WO2008142735A1 (ja) 2007-05-21 2007-05-21 ２進の擬似ランダムデータを生成する方法および装置
US12/577,998 US7812636B2 (en) 2007-05-21 2009-10-13 Method and device for generating pseudo-random binary data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000542 WO2008142735A1 (ja) 2007-05-21 2007-05-21 ２進の擬似ランダムデータを生成する方法および装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/577,998 Continuation US7812636B2 (en) 2007-05-21 2009-10-13 Method and device for generating pseudo-random binary data

Publications (1)

Publication Number Publication Date
WO2008142735A1 true WO2008142735A1 (ja) 2008-11-27

Family

ID=40031462

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000542 WO2008142735A1 (ja) 2007-05-21 2007-05-21 ２進の擬似ランダムデータを生成する方法および装置

Country Status (3)

Country Link
US (1) US7812636B2 (ja)
JP (1) JPWO2008142735A1 (ja)
WO (1) WO2008142735A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190115986A1 (en) * 2017-10-18 2019-04-18 Texas Instruments Incorporated SWITCH MODE DIRECT CURRENT-TO-DIRECT CURRENT (DC-to-DC) CONVERTERS WITH REDUCED SPURIOUS NOISE EMISSION

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104311A (ja) * 1989-09-19 1991-05-01 Fujitsu Ltd Ｐｎパターン発生回路
JPH08181577A (ja) * 1994-12-21 1996-07-12 Sony Tektronix Corp デジタル信号発生器
JPH096596A (ja) * 1995-06-16 1997-01-10 Toshiba Corp 擬似乱数発生装置
JP2000200177A (ja) * 1998-12-29 2000-07-18 Texas Instr Inc <Ti> デ―タの最大長シ―ケンスを発生する方法と装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959832A (en) * 1988-12-09 1990-09-25 International Business Machines Parallel pseudorandom pattern generator with varying phase shift
JP3104311B2 (ja) 1991-08-06 2000-10-30 住友金属工業株式会社 積層型圧電アクチュエータの製造方法
JP3173373B2 (ja) 1996-05-27 2001-06-04 安藤電気株式会社 疑似ランダム２進法シーケンスパターンの発生方法および発生装置
JP2002342072A (ja) 2001-05-14 2002-11-29 Kenwood Corp ランダムデータ生成装置、データランダム化装置、ランダムデータ生成方法及びプログラム
EP1516430A2 (en) * 2001-07-05 2005-03-23 Koninklijke Philips Electronics N.V. Pseudo random generator
JP5231079B2 (ja) * 2008-04-25 2013-07-10 ルネサスエレクトロニクス株式会社 疑似乱数発生器及びデータ通信装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03104311A (ja) * 1989-09-19 1991-05-01 Fujitsu Ltd Ｐｎパターン発生回路
JPH08181577A (ja) * 1994-12-21 1996-07-12 Sony Tektronix Corp デジタル信号発生器
JPH096596A (ja) * 1995-06-16 1997-01-10 Toshiba Corp 擬似乱数発生装置
JP2000200177A (ja) * 1998-12-29 2000-07-18 Texas Instr Inc <Ti> デ―タの最大長シ―ケンスを発生する方法と装置

Also Published As

Publication number Publication date
US7812636B2 (en) 2010-10-12
JPWO2008142735A1 (ja) 2010-08-05
US20100033209A1 (en) 2010-02-11

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