WO2008139613A1 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

Info

Publication number
WO2008139613A1
WO2008139613A1 PCT/JP2007/059889 JP2007059889W WO2008139613A1 WO 2008139613 A1 WO2008139613 A1 WO 2008139613A1 JP 2007059889 W JP2007059889 W JP 2007059889W WO 2008139613 A1 WO2008139613 A1 WO 2008139613A1
Authority
WO
WIPO (PCT)
Prior art keywords
board
wiring board
manufacturing
same
base
Prior art date
Application number
PCT/JP2007/059889
Other languages
English (en)
French (fr)
Inventor
Michimasa Takahashi
Masakazu Aoyama
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Priority to PCT/JP2007/059889 priority Critical patent/WO2008139613A1/ja
Priority to JP2009513946A priority patent/JP5111500B2/ja
Priority to EP07743324A priority patent/EP2150096A4/en
Priority to CN2007800529691A priority patent/CN101675716B/zh
Priority to TW097125942A priority patent/TWI429338B/zh
Publication of WO2008139613A1 publication Critical patent/WO2008139613A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

　配線基板（１９）は、第１基板（１）と、第１基板（１）より実装面積が小さい第２基板（２）と、第１基板（１）と第２基板（２）との間に設けられているベース基板（３）と、を積層して構成される。配線基板（１９）は、第１基板（１）と第２基板（２）の少なくともいずれか一つに設けられたヴィア（４４）と、ベース基板（３）を貫通するスルーホール（６３）と、を有する。また、配線基板（１９）は、第１基板（１）と第２基板（２）とにヴィア（４４）を設けるとともに、ベース基板（３）を貫通するＩＶＨ（Interstitial Via Hole）と、を有する。
PCT/JP2007/059889 2007-05-14 2007-05-14 配線基板及びその製造方法 WO2008139613A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/059889 WO2008139613A1 (ja) 2007-05-14 2007-05-14 配線基板及びその製造方法
JP2009513946A JP5111500B2 (ja) 2007-05-14 2007-05-14 配線基板
EP07743324A EP2150096A4 (en) 2007-05-14 2007-05-14 CONNECTION TABLE AND METHOD FOR MANUFACTURING THE SAME
CN2007800529691A CN101675716B (zh) 2007-05-14 2007-05-14 布线基板及其制造方法
TW097125942A TWI429338B (zh) 2007-05-14 2008-07-09 配線基板及其製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/059889 WO2008139613A1 (ja) 2007-05-14 2007-05-14 配線基板及びその製造方法

Publications (1)

Publication Number Publication Date
WO2008139613A1 true WO2008139613A1 (ja) 2008-11-20

Family

ID=40001843

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/059889 WO2008139613A1 (ja) 2007-05-14 2007-05-14 配線基板及びその製造方法

Country Status (5)

Country Link
EP (1) EP2150096A4 (ja)
JP (1) JP5111500B2 (ja)
CN (1) CN101675716B (ja)
TW (1) TWI429338B (ja)
WO (1) WO2008139613A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107105576B (zh) * 2017-06-20 2019-05-17 广州兴森快捷电路科技有限公司 阶梯凸台印制板的制作方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152693A (ja) 1991-11-30 1993-06-18 Nitto Denko Corp 補強部付フレキシブルプリント基板およびその製法
JPH1174651A (ja) * 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JP2000013019A (ja) * 1998-06-23 2000-01-14 Sharp Corp ビルトアップ多層プリント配線板およびその製造方法
JP2002064271A (ja) * 2000-06-09 2002-02-28 Matsushita Electric Ind Co Ltd 複合配線基板及びその製造方法
JP2004349277A (ja) * 2003-04-28 2004-12-09 Nippon Carbide Ind Co Inc 多層配線基板及びその製造方法
JP2005079402A (ja) * 2003-09-01 2005-03-24 Fujikura Ltd 回路基板およびその製造方法
WO2005029934A1 (ja) 2003-09-19 2005-03-31 Fujitsu Limited プリント基板およびその製造方法
JP2005236205A (ja) * 2004-02-23 2005-09-02 Sharp Corp 多層プリント配線板の製造方法及び多層プリント配線板
JP2005268505A (ja) * 2004-03-18 2005-09-29 Fujikura Ltd 多層配線板およびその製造方法
JP2005336287A (ja) * 2004-05-26 2005-12-08 Matsushita Electric Works Ltd フレキシブルプリント配線板用熱硬化性接着シート、その製造方法及びそれを用いた多層フレキシブルプリント配線板並びにフレックスリジッドプリント配線板
JP2006114741A (ja) * 2004-10-15 2006-04-27 Ibiden Co Ltd 多層コア基板及びその製造方法
JP2006202891A (ja) * 2005-01-19 2006-08-03 Fujikura Ltd リジッドフレックスプリント配線板の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787225B2 (ja) * 1989-11-08 1995-09-20 富士通株式会社 半導体素子実装用基板
US6753483B2 (en) * 2000-06-14 2004-06-22 Matsushita Electric Industrial Co., Ltd. Printed circuit board and method of manufacturing the same
JP2004031682A (ja) * 2002-06-26 2004-01-29 Sony Corp プリント配線基板の製造方法
KR100467825B1 (ko) * 2002-12-12 2005-01-25 삼성전기주식회사 스택형 비아홀을 갖는 빌드업 인쇄회로기판 및 그 제조 방법
JP2004266236A (ja) * 2003-01-09 2004-09-24 Sony Chem Corp 基板素片とその基板素片を用いた複合配線板
JP2005045150A (ja) * 2003-07-25 2005-02-17 Matsushita Electric Ind Co Ltd 中間接続用配線基材および多層配線基板、ならびにこれらの製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152693A (ja) 1991-11-30 1993-06-18 Nitto Denko Corp 補強部付フレキシブルプリント基板およびその製法
JPH1174651A (ja) * 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JP2000013019A (ja) * 1998-06-23 2000-01-14 Sharp Corp ビルトアップ多層プリント配線板およびその製造方法
JP2002064271A (ja) * 2000-06-09 2002-02-28 Matsushita Electric Ind Co Ltd 複合配線基板及びその製造方法
JP2004349277A (ja) * 2003-04-28 2004-12-09 Nippon Carbide Ind Co Inc 多層配線基板及びその製造方法
JP2005079402A (ja) * 2003-09-01 2005-03-24 Fujikura Ltd 回路基板およびその製造方法
WO2005029934A1 (ja) 2003-09-19 2005-03-31 Fujitsu Limited プリント基板およびその製造方法
JP2005236205A (ja) * 2004-02-23 2005-09-02 Sharp Corp 多層プリント配線板の製造方法及び多層プリント配線板
JP2005268505A (ja) * 2004-03-18 2005-09-29 Fujikura Ltd 多層配線板およびその製造方法
JP2005336287A (ja) * 2004-05-26 2005-12-08 Matsushita Electric Works Ltd フレキシブルプリント配線板用熱硬化性接着シート、その製造方法及びそれを用いた多層フレキシブルプリント配線板並びにフレックスリジッドプリント配線板
JP2006114741A (ja) * 2004-10-15 2006-04-27 Ibiden Co Ltd 多層コア基板及びその製造方法
JP2006202891A (ja) * 2005-01-19 2006-08-03 Fujikura Ltd リジッドフレックスプリント配線板の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2150096A4 *

Also Published As

Publication number Publication date
JPWO2008139613A1 (ja) 2010-07-29
EP2150096A4 (en) 2013-02-20
JP5111500B2 (ja) 2013-01-09
CN101675716A (zh) 2010-03-17
EP2150096A1 (en) 2010-02-03
TWI429338B (zh) 2014-03-01
CN101675716B (zh) 2012-09-05
TW201004498A (en) 2010-01-16

Similar Documents

Publication Publication Date Title
USD584251S1 (en) Electronic equipment cabinet
USD584252S1 (en) Electronic equipment cabinet
TW200640325A (en) Wiring board manufacturing method
GB2441265B (en) Method for manufacturing a circuit board structure, and a circuit board structure
WO2007120697A3 (en) Methods and apparatus for integrated circuit having multiple dies with at least one on chip capacitor
EP1478023A4 (en) MODULE PART
WO2006060814A3 (en) Process for making a fibrous structure comprising an additive
WO2009105367A3 (en) Integrated circuit package and method of manufacturing same
WO2006134216A3 (en) Circuit board structure and method for manufacturing a circuit board structure
EP1592061A3 (en) Multilayer substrate including components therein
WO2006039633A3 (en) Structure and method of making interconnect element, and multilayer wiring board including the interconnect element
AU2003303968A8 (en) An interconnection device for a printed circuit board, a method of manufacturing the same, and an interconnection assembly having the same
EP1734068A4 (en) POLYMER COMPOSITE MOLDING BODY, LADDER PLATE WITH THE MOLDING BODY AND METHOD OF MANUFACTURING THEREOF
EP1549118A3 (en) Printed circuit board with low cross-talk noise
FI20050767A (fi) Monikerroksinen langoituslevy ja menetelmä sen valmistamiseksi
ATE535138T1 (de) Elektronisches verbundbauteil und verfahren zu seiner herstellung
WO2009037523A8 (en) An antenna arrangement, a method for manufacturing an antenna arrangement and a printed wiring board for use in an antenna arrangement
TW200635473A (en) Capacitor-embedded PCB having blind via hole and method of manufacturing the same
EP1903840A4 (en) CONDUCTOR PLATE, WELDING MATERIAL, COPPER-COATED LAMINATE AND MANUFACTURING PROCESS FOR A PCB
SG125213A1 (en) Manufacturing method for electronic device
WO2008129480A3 (en) An electronic component, and a method of manufacturing an electronic component
TW200629998A (en) Printed circuit board and forming method thereof
WO2008126564A1 (ja) 放熱部材、それを用いた回路基板、電子部品モジュール及びその製造方法
EP1555862A3 (en) Process for producing circuit board having built-in electronic part
WO2006042029A3 (en) Structure and method of making interconnect element having metal traces embedded in surface of dielectric

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780052969.1

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07743324

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009513946

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007743324

Country of ref document: EP