WO2008122624A3 - Verfahren zur herstellung eines elektrischen trägerscheibenkontakts für einen vorderseitigen anschluss - Google Patents
Verfahren zur herstellung eines elektrischen trägerscheibenkontakts für einen vorderseitigen anschluss Download PDFInfo
- Publication number
- WO2008122624A3 WO2008122624A3 PCT/EP2008/054123 EP2008054123W WO2008122624A3 WO 2008122624 A3 WO2008122624 A3 WO 2008122624A3 EP 2008054123 W EP2008054123 W EP 2008054123W WO 2008122624 A3 WO2008122624 A3 WO 2008122624A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- components
- carrier wafer
- layer
- bonding
- producing
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Element Separation (AREA)
Abstract
Vorgeschlagen wird ein Verfahren zur Herstellung eines elektrischen Trägerscheibenkontaktes mit vorderseitigem Anschluss für CMOS-Bauelemente der SOI-Technologie unter Einsatz dicker Schichten (2) in der Größenordnung von einigen μm auf der Silizium-Trägerscheibe (4). Am Ende des CMOS-Prozesses wird die Trägerscheibe durch Ätzung einer Einsenkung (6a) in der Größe einer Bondinsel freigelegt, welche Ätzung durch den gesamten Stapel aus Zwischenisolatorschichten, aktiver Siliziumschicht (2) und vergrabenem Oxid (3) reicht. In diesem Gebiet wird die Bondinsel mittels einer Metallisierungsebene mit nachfolgender Strukturierung ausgebildet. Von dieser Ebene wird später im Montageprozess durch Drahtbonden (7) eine elektrische Verbindung zu anderen Bondinseln des Bauelementes hergestellt. Durch das Verfahren gelingt es Kosten einzusparen und die Ausbeute zu steigern. Die entstehenden Bauelemente besitzen eine erhöhte Zuverlässigkeit und können für differenziertere Anwendungen gestaltet werden, z.B. auf unterschiedliche elektrische Potenziale von Substratkontakten für SOI-Bauelemente ausgelegt werden.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102007016257.1 | 2007-04-04 | ||
DE200710016257 DE102007016257A1 (de) | 2007-04-04 | 2007-04-04 | Verfahren zur Herstellung eines elektrischen Trägerscheibenkontaktes mit vorderseitigem Anschluss |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008122624A2 WO2008122624A2 (de) | 2008-10-16 |
WO2008122624A3 true WO2008122624A3 (de) | 2009-01-08 |
Family
ID=39736160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2008/054123 WO2008122624A2 (de) | 2007-04-04 | 2008-04-04 | Verfahren zur herstellung eines elektrischen trägerscheibenkontakts für einen vorderseitigen anschluss |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102007016257A1 (de) |
WO (1) | WO2008122624A2 (de) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4076955A (en) * | 1975-03-03 | 1978-02-28 | Hughes Aircraft Company | Package for hermetically sealing electronic circuits |
DE19845294A1 (de) * | 1998-03-13 | 1999-09-23 | Mitsubishi Electric Corp | Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5314841A (en) | 1993-04-30 | 1994-05-24 | International Business Machines Corporation | Method of forming a frontside contact to the silicon substrate of a SOI wafer |
US5479048A (en) | 1994-02-04 | 1995-12-26 | Analog Devices, Inc. | Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level |
US6355511B1 (en) | 2000-06-16 | 2002-03-12 | Advanced Micro Devices, Inc. | Method of providing a frontside contact to substrate of SOI device |
US7485926B2 (en) | 2003-01-30 | 2009-02-03 | X-Fab Semiconductor Foundries Ag | SOI contact structures |
-
2007
- 2007-04-04 DE DE200710016257 patent/DE102007016257A1/de not_active Withdrawn
-
2008
- 2008-04-04 WO PCT/EP2008/054123 patent/WO2008122624A2/de active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4076955A (en) * | 1975-03-03 | 1978-02-28 | Hughes Aircraft Company | Package for hermetically sealing electronic circuits |
DE19845294A1 (de) * | 1998-03-13 | 1999-09-23 | Mitsubishi Electric Corp | Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung |
Also Published As
Publication number | Publication date |
---|---|
WO2008122624A2 (de) | 2008-10-16 |
DE102007016257A1 (de) | 2008-10-09 |
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