WO2008120347A1 - 半導体装置およびバイアス生成回路 - Google Patents

半導体装置およびバイアス生成回路 Download PDF

Info

Publication number
WO2008120347A1
WO2008120347A1 PCT/JP2007/056838 JP2007056838W WO2008120347A1 WO 2008120347 A1 WO2008120347 A1 WO 2008120347A1 JP 2007056838 W JP2007056838 W JP 2007056838W WO 2008120347 A1 WO2008120347 A1 WO 2008120347A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
supply voltage
semiconductor device
generating circuit
bias generating
Prior art date
Application number
PCT/JP2007/056838
Other languages
English (en)
French (fr)
Inventor
Motoyuki Tanaka
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07740276A priority Critical patent/EP2133912B1/en
Priority to PCT/JP2007/056838 priority patent/WO2008120347A1/ja
Priority to JP2009507339A priority patent/JP5158076B2/ja
Priority to KR1020097019233A priority patent/KR101114940B1/ko
Priority to CN2007800524151A priority patent/CN101641777B/zh
Publication of WO2008120347A1 publication Critical patent/WO2008120347A1/ja
Priority to US12/567,964 priority patent/US8222951B2/en

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H01L27/0222—Charge pumping, substrate bias generation structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Abstract

　第１の電源電圧を入力可能な第１電源電圧入力部（ＶＤＤ）と、第２の電源電圧を入力可能な第２電源電圧入力部（ＶＤＤ２）と、第２の電源電圧に基づいてバックバイアス電圧を生成するレギュレータ回路（１１）と、このレギュレータ回路（１１）によって生成されたバックバイアス電圧を出力電圧として出力可能な出力部（ＶＢＰ１）とをそなえることにより、基板バイアスの生成を低消費電力で行なうことができるとともに、回路規模を小さく構成する。
PCT/JP2007/056838 2007-03-29 2007-03-29 半導体装置およびバイアス生成回路 WO2008120347A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP07740276A EP2133912B1 (en) 2007-03-29 2007-03-29 Semiconductor device and bias generating circuit
PCT/JP2007/056838 WO2008120347A1 (ja) 2007-03-29 2007-03-29 半導体装置およびバイアス生成回路
JP2009507339A JP5158076B2 (ja) 2007-03-29 2007-03-29 半導体装置およびバイアス生成回路
KR1020097019233A KR101114940B1 (ko) 2007-03-29 2007-03-29 반도체 장치 및 바이어스 생성 회로
CN2007800524151A CN101641777B (zh) 2007-03-29 2007-03-29 半导体装置及偏压产生电路
US12/567,964 US8222951B2 (en) 2007-03-29 2009-09-28 Semiconductor device and bias generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056838 WO2008120347A1 (ja) 2007-03-29 2007-03-29 半導体装置およびバイアス生成回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/567,964 Continuation US8222951B2 (en) 2007-03-29 2009-09-28 Semiconductor device and bias generation circuit

Publications (1)

Publication Number Publication Date
WO2008120347A1 true WO2008120347A1 (ja) 2008-10-09

Family

ID=39807940

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056838 WO2008120347A1 (ja) 2007-03-29 2007-03-29 半導体装置およびバイアス生成回路

Country Status (6)

Country Link
US (1) US8222951B2 (ja)
EP (1) EP2133912B1 (ja)
JP (1) JP5158076B2 (ja)
KR (1) KR101114940B1 (ja)
CN (1) CN101641777B (ja)
WO (1) WO2008120347A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112514227A (zh) * 2018-04-24 2021-03-16 德州仪器公司 栅极驱动适配器

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9084058B2 (en) 2011-12-29 2015-07-14 Sonos, Inc. Sound field calibration using listener localization
US9219460B2 (en) 2014-03-17 2015-12-22 Sonos, Inc. Audio settings based on environment
US9106192B2 (en) 2012-06-28 2015-08-11 Sonos, Inc. System and method for device playback calibration
US9706323B2 (en) 2014-09-09 2017-07-11 Sonos, Inc. Playback device calibration
US9264839B2 (en) 2014-03-17 2016-02-16 Sonos, Inc. Playback device configuration based on proximity detection
US9952825B2 (en) 2014-09-09 2018-04-24 Sonos, Inc. Audio processing algorithms
JP6437695B2 (ja) 2015-09-17 2018-12-12 ソノズ インコーポレイテッド オーディオ再生デバイスのキャリブレーションを容易にする方法
US9693165B2 (en) 2015-09-17 2017-06-27 Sonos, Inc. Validation of audio calibration using multi-dimensional motion check
US9743207B1 (en) 2016-01-18 2017-08-22 Sonos, Inc. Calibration using multiple recording devices
US10003899B2 (en) 2016-01-25 2018-06-19 Sonos, Inc. Calibration with particular locations
US11106423B2 (en) 2016-01-25 2021-08-31 Sonos, Inc. Evaluating calibration of a playback device
US9860662B2 (en) 2016-04-01 2018-01-02 Sonos, Inc. Updating playback device configuration information based on calibration data
US9864574B2 (en) 2016-04-01 2018-01-09 Sonos, Inc. Playback device calibration based on representation spectral characteristics
US9763018B1 (en) 2016-04-12 2017-09-12 Sonos, Inc. Calibration of audio playback devices
US9794710B1 (en) 2016-07-15 2017-10-17 Sonos, Inc. Spatial audio correction
US10372406B2 (en) 2016-07-22 2019-08-06 Sonos, Inc. Calibration interface
US10459684B2 (en) 2016-08-05 2019-10-29 Sonos, Inc. Calibration of a playback device based on an estimated frequency response
US11206484B2 (en) 2018-08-28 2021-12-21 Sonos, Inc. Passive speaker authentication
US10299061B1 (en) 2018-08-28 2019-05-21 Sonos, Inc. Playback device calibration
US10734965B1 (en) 2019-08-12 2020-08-04 Sonos, Inc. Audio calibration of a portable playback device
US11262780B1 (en) * 2020-11-12 2022-03-01 Micron Technology, Inc. Back-bias optimization

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035161A (ja) 1999-05-17 2001-02-09 Hitachi Ltd 半導体集積回路装置
JP2006351633A (ja) * 2005-06-13 2006-12-28 Matsushita Electric Ind Co Ltd 半導体集積回路装置、電子部品実装基板および半導体集積回路装置のレイアウト設計方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1023347C (zh) * 1991-01-24 1993-12-29 清华大学 瞬态电荷测量系统
JP3704188B2 (ja) * 1996-02-27 2005-10-05 株式会社ルネサステクノロジ 半導体記憶装置
JP3814385B2 (ja) * 1997-10-14 2006-08-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP2001156619A (ja) * 1999-11-25 2001-06-08 Texas Instr Japan Ltd 半導体回路
JP3579633B2 (ja) * 2000-05-19 2004-10-20 株式会社ルネサステクノロジ 半導体集積回路
JP4149637B2 (ja) 2000-05-25 2008-09-10 株式会社東芝 半導体装置
TW519794B (en) * 2001-01-16 2003-02-01 Elan Microelectronics Corp Automatic bias circuit of base stand
US6737909B2 (en) * 2001-11-26 2004-05-18 Intel Corporation Integrated circuit current reference
US20060145749A1 (en) * 2004-12-30 2006-07-06 Dipankar Bhattacharya Bias circuit having reduced power-up delay
US7317346B2 (en) * 2005-03-11 2008-01-08 Intel Corporation Selecting a bias for a level shifting device
TWI318344B (en) * 2006-05-10 2009-12-11 Realtek Semiconductor Corp Substrate biasing apparatus
US7598794B1 (en) * 2006-09-28 2009-10-06 Cypress Semiconductor Corporation Well bias architecture for integrated circuit device
US7639067B1 (en) * 2006-12-11 2009-12-29 Altera Corporation Integrated circuit voltage regulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035161A (ja) 1999-05-17 2001-02-09 Hitachi Ltd 半導体集積回路装置
JP2006351633A (ja) * 2005-06-13 2006-12-28 Matsushita Electric Ind Co Ltd 半導体集積回路装置、電子部品実装基板および半導体集積回路装置のレイアウト設計方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2133912A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112514227A (zh) * 2018-04-24 2021-03-16 德州仪器公司 栅极驱动适配器
CN112514227B (zh) * 2018-04-24 2024-05-03 德州仪器公司 栅极驱动适配器

Also Published As

Publication number Publication date
JP5158076B2 (ja) 2013-03-06
EP2133912A1 (en) 2009-12-16
CN101641777B (zh) 2012-05-23
EP2133912A4 (en) 2011-06-22
KR101114940B1 (ko) 2012-03-07
US20100013550A1 (en) 2010-01-21
KR20100005025A (ko) 2010-01-13
US8222951B2 (en) 2012-07-17
EP2133912B1 (en) 2012-11-14
CN101641777A (zh) 2010-02-03
JPWO2008120347A1 (ja) 2010-07-15

Similar Documents

Publication Publication Date Title
WO2008120347A1 (ja) 半導体装置およびバイアス生成回路
TW200709559A (en) Circuits for generating reference current and bias voltages, and bias circuit using the same
TW200715091A (en) Bandgap reference circuit
TW200709566A (en) Level shift circuit and semiconductor device
TW200720878A (en) Bandgap reference circuit
TW200731048A (en) Single feedback input for regulation at both positive and negative voltage levels
TW200742019A (en) IC with on-die power-gating circuit
TW200629033A (en) Low voltage bandgap reference (BGR) circuit
IN2012DN01756A (ja)
TW200707158A (en) Constant current circuit
TW200713303A (en) Internal voltage geneator of semiconductor integrated circuit
JP2011060876A5 (ja) 半導体装置
TW200719112A (en) Reference voltage generator
WO2010104556A3 (en) Power latch
TW200609716A (en) Power-on reset circuit
TW200720877A (en) Regulator circuit
TW200630948A (en) Clock generating circuit and a display device having the same
GB2509855A (en) Rate scalable IO interface with zero stand-by power and fast start-up
IN2014DN08907A (ja)
TW200634836A (en) High-speed, low-power input buffer for an integrated circuit device
MX2009003686A (es) Circuito de inicio para circuito de vacio de banda.
TW200715088A (en) Voltage supply circuit
TW200613942A (en) Integrated circuit with multiple feedback
DE602008002952D1 (de) Integrierte elektronische anordnung mit schaltkreisen zur bereitstellung einer systemversorgungsspannung aus einer primärstromversorgung
ATE534063T1 (de) Spannungsregler mit shunt-rückmeldung

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780052415.1

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07740276

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009507339

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020097019233

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007740276

Country of ref document: EP